Testplan

Randomly assert error bit for instruction fetch and load/store. Expect the core to raise memory access fault exception Verify the fault load instruction won’t modify GPR Verify the context of the exception is captured correctly in privileged CSRs

mstatus, mcause, mepc

`riscv_illegal_instr_test`

Test: riscv_illegal_instr_test

Randomly inject below illegal instructions in the instruction stream

Instructions which not belong to RV32IMC
Reserved instructions as specified in RISC-V user mode spec
CSR instruction to not implemented CSR
Execute S/U mode instructions in machine mode Verify the illlegal instruction exception is raised and the context is captured correctly in privieged mode CSRs
mstatus, mcause, mepc Verify the core can resume execution after returning from trap handling

`riscv_hint_instr_test`

Test: riscv_hint_instr_test

Randomly inject HINT instructions as specified in RISC-V user mode specification 5.4 Verify the core execute it as NOP and no exception is raised

`riscv_ebreak_test`

Test: riscv_ebreak_test

Generate random instructions including ebreak, expect core to raise ebreak exception

`riscv_debug_basic_test`

Test: riscv_debug_basic_test

Randomly assert debug_req_i signal

in debug_rom, insert normal random instruction sequence excluding control transfer instructions
verify wfi instructions act as NOPs
ensure normal execution finishes successfully

`riscv_debug_stress_test`

Test: riscv_debug_stress_test

Randomly assert debug_req signal

debug rom will consist of just a dret instructions, so any switches into debug mode will immediately return
will use this jointly with full instruction checking with spike

`riscv_debug_branch_jump_test`

Test: riscv_debug_branch_jump_test

Randomly assert debug_req_i signal

in debug_rom, insert random instruction sequence, including control transfer instructions and multiple subprograms to jump between

`riscv_debug_wfi_test`

Test: riscv_debug_wfi_test

Insert random generation of wfi instructions

while core is in wfi sleep state, assert debug request
verify core jumps to debug mode
debug rom consists of random generation instructions

`riscv_dret_test`

Test: riscv_dret_test

Randomly insert dret instructions into M mode instructions

verify that ibex treats them as illegal instructions

`riscv_debug_ebreak_test`

Test: riscv_debug_ebreak_test

insert ebreak instructions in M mode code, should be handled normally
assert debug request
in debug mode, insert ebreak instruction, verify that ibex re-enter debug mode

`riscv_debug_ebreakmu_test`

Test: riscv_debug_ebreakmu_test

set dcsr.ebreakm/u at begining of test
randomly insert ebreak instructions in generated code
boot randomly into either M/U modes
verify that ebreak instructions (in either mode) now enter debug mode

`riscv_debug_single_step_test`

Test: riscv_debug_single_step_test

Randomly assert debug_req_i signal to force core into debug mode.

in debug_rom, set dcsr.step
after exiting debug mode, core will execute one instruction and re-enter debug mode

`riscv_debug_csr_entry_test`

Test: riscv_debug_csr_entry_test

Inject debug stimulus during CSR modification operations, core should jump to debug mode and return without any issues

`riscv_irq_in_debug_mode_test`

Test: riscv_irq_in_debug_mode_test

Randomly assert interrupt lines while the core is in debug mode execution, verify that these interrupts are all completely ignored

`riscv_single_interrupt_test`

Test: riscv_single_interrupt_test

Randomly assert a single interrupt line during program execution, core should jump to proper handler

`riscv_multiple_interrupt_test`

Test: riscv_multiple_interrupt_test

Randomly assert multiple interrupt lines during program execution, core should jump to handler of highest priority interrupt

`riscv_interrupt_wfi_test`

Test: riscv_interrupt_wfi_test

Randomly assert interrupt lines while the core is sleeping due to a WFI instruction

`riscv_interrupt_csr_test`

Test: riscv_interrupt_csr_test

Randomly assert interrupt lines during CSR modification operations, core should jump to proper handler

`riscv_csr_test`

Test: riscv_csr_test

Perform all CSR instructions to implemented privileged CSR Verify the reset value of the privileged CSR Verify WARL field can be upated properly

`riscv_reset_test`

Test: riscv_reset_test

Reset the core a random number of times during program execution, core should jump back to start address and re-enter the program. Ensure to flush all testbench state to prevent contamination after reset.

`riscv_perf_counter_test`

Test: riscv_perf_counter_test

Run random instruction test, and dump performance counters for checking

`riscv_rv32im_instr_test`

Test: riscv_rv32im_instr_test

Specify RV32IM architecture to compiler to generate target specific instructions (no compressed instructions).

Stage V2 Testpoints

`riscv_debug_interrupt_test`

Test: riscv_debug_interrupt_test

Randomly assert debug_req_i signal

in debug_rom, insert random instruction sequence
randomly toggle interrupts during debug code
verify that execution of debug_rom continues as normal, interrupts are ignored

`riscv_debug_illegal_instr_test`

Test: riscv_debug_illegal_instr_test

insert illegal instruction into debug rom to trigger internal exception
verify that no registers have been updated
verify that execution of debug rom ends

`riscv_interrupt_nested_test`

Test: riscv_interrupt_nested_test

randomly assert interrupt lines during program execution
verify that jumps to interrupt handler
trigger another interrupt during first intr_handler execution
verify that core takes this nested interrupt and handles it, then restores previous interrupt state and finishes executing first interrupt handler - ibex implements nonstandard MSTACK csrs to save/restore state in case of nested interrupt

`riscv_user_mode_rand_test`

Test: riscv_user_mode_rand_test

Fully randomized RV32IMC instructions, boot in U-mode, test should finish successfully

includes all types of instructions
no external debug/irq stimulus, exceptions, security aspects are checked here

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