- Introduction
- 1. About Pavona
- 2. Getting Started
❱
- 2.1. Intro to Hardware
- 2.2. Intro to Software
- Using Pavona
- 3. Verilator Setup
- 4. FPGA Setup
❱
- 4.1. Vivado Setup
- 4.2. Get a Board
- 4.3. FPGA Reference Manual
❱
- 4.3.1. Using OpenOCD
- 4.3.2. Debugging with an ILA
- 5. Design Verification Setup
❱
- 5.1. Formal Verification Setup
- 6. Synthesis Flow
❱
- 6.1. Linting
- 7. License
- Contributing
- 8. Contributing
❱
- 8.1. Vendoring Philosophy
- 9. Style
❱
- 9.1. Verilog
❱
- 9.1.1. DV
- 9.2. RISC-V Assembly
- 9.3. ACC Assembly
- 9.4. C & C++
- 9.5. Python
- 9.6. Hjson
- 9.7. Markdown
- 10. Directory Structure
- 11. GitHub Notes
- 12. Bazel Notes
- 13. Continuous Integration
❱
- 13.1. FAQs
- 14. Glossary
- Hardware
- 15. Hardware Overview
❱
- 15.1. Comportability
- 15.2. Development Stages
- 15.3. Checklists
- 15.4. Cores
- 15.5. IP Template Generation
- 16. Hardware IP Blocks
❱
- 16.1. Asymmetric Cryptographic Coprocessor (ACC)
❱
- 16.1.1. Introduction to ACC
- 16.1.2. Theory of Operation
- 16.1.3. Developing ACC
❱
- 16.1.3.1. Writing Software
- 16.1.3.2. Example Code Snippets
- 16.1.4. ISA Guide
- 16.1.5. Design Verification
❱
- 16.1.5.1. Testplan
- 16.1.5.2. Random Instruction Generator
❱
- 16.1.5.2.1. Internals
- 16.1.5.2.2. Configuration
- 16.1.5.3. memutil wrapper
- 16.1.5.4. ACC Simulation Software
- 16.1.5.5. Tracer
- 16.1.5.6. Formal Masking Verification Using Alma
- 16.1.6. Functional Coverage
- 16.1.7. Programmer's Guide
- 16.1.8. Hardware Interfaces
- 16.1.9. Registers
- 16.1.10. Hardware Checklist
- 16.1.11. Software Checklist
- 16.2. Access Control Range Check [templated]
- 16.3. Analog to Digital Converter Control
❱
- 16.3.1. Theory of Operation
- 16.3.2. Design Verification
❱
- 16.3.2.1. Testplan
- 16.3.3. Programmer's Guide
- 16.3.4. Hardware Interfaces
- 16.3.5. Registers
- 16.3.6. Device Interface Functions
- 16.3.7. Hardware Checklist
- 16.4. Advanced Encryption Standard (AES)
❱
- 16.4.1. Theory of Operation
- 16.4.2. Design Verification
❱
- 16.4.2.1. Testplan
- 16.4.3. Programmer's Guide
- 16.4.4. Hardware Interfaces
- 16.4.5. Registers
- 16.4.6. Device Interface Functions
- 16.4.7. Hardware Checklist
- 16.4.8. Software Checklist
- 16.5. Alert Handler [templated]
- 16.6. Always-On Timer
❱
- 16.6.1. Theory of Operation
- 16.6.2. Design Verification
❱
- 16.6.2.1. Testplan
- 16.6.3. Programmer's Guide
- 16.6.4. Hardware Interfaces
- 16.6.5. Registers
- 16.6.6. Device Interface Functions
- 16.6.7. Hardware Checklist
- 16.6.8. Software Checklist
- 16.7. Ascon
❱
- 16.7.1. Background
- 16.7.2. Theory of Operation
- 16.7.3. Programmer's Guide
- 16.7.4. Hardware Interfaces
- 16.7.5. Registers
- 16.7.6. Hardware Checklist
- 16.8. Clock Manager [templated]
- 16.9. Cryptographically Secure Random Number Generator (CSRNG)
❱
- 16.9.1. Theory of Operation
- 16.9.2. Design Verification
❱
- 16.9.2.1. Testplan
- 16.9.3. Programmer's Guide
- 16.9.4. Hardware Interfaces
- 16.9.5. Registers
- 16.9.6. Device Interface Functions
- 16.9.7. Hardware Checklist
- 16.9.8. Software Checklist
- 16.10. DMA
❱
- 16.10.1. Theory of Operation
- 16.10.2. Design Verification
❱
- 16.10.2.1. Testplan
- 16.10.3. Programmer's Guide
- 16.10.4. Hardware Interfaces
- 16.10.5. Registers
- 16.10.6. Device Interface Functions
- 16.10.7. Hardware Checklist
- 16.10.8. Software Checklist
- 16.11. Entropy Distribution Network (EDN)
❱
- 16.11.1. Theory of Operation
- 16.11.2. Design Verification
❱
- 16.11.2.1. Testplan
- 16.11.3. Programmer's Guide
- 16.11.4. Hardware Interfaces
- 16.11.5. Registers
- 16.11.6. Device Interface Functions
- 16.11.7. Hardware Checklist
- 16.11.8. Software Checklist
- 16.12. Entropy Source
❱
- 16.12.1. Theory of Operation
- 16.12.2. Design Verification
❱
- 16.12.2.1. Testplan
- 16.12.3. Programmer's Guide
- 16.12.4. Hardware Interfaces
- 16.12.5. Registers
- 16.12.6. Device Interface Functions
- 16.12.7. Hardware Checklist
- 16.12.8. Software Checklist
- 16.13. Flash Controller [templated]
- 16.14. Flash Macro Wrapper
❱
- 16.14.1. Overview
- 16.15. GPIO [templated]
- 16.16. HMAC
❱
- 16.16.1. Theory of Operation
- 16.16.2. Design Verification
❱
- 16.16.2.1. Testplan
- 16.16.3. Programmer's Guide
- 16.16.4. Hardware Interfaces
- 16.16.5. Registers
- 16.16.6. Device Interface Functions
- 16.16.7. Hardware Checklist
- 16.16.8. Software Checklist
- 16.17. I2C
❱
- 16.17.1. Theory of Operation
- 16.17.2. Design Verification
❱
- 16.17.2.1. Testplan
- 16.17.3. Programmer's Guide
- 16.17.4. Hardware Interfaces
- 16.17.5. Registers
- 16.17.6. Device Interface Functions
- 16.17.7. Hardware Checklist
- 16.17.8. Software Checklist
- 16.18. Key Manager
❱
- 16.18.1. Theory of Operation
- 16.18.2. Design Verification
❱
- 16.18.2.1. Testplan
- 16.18.3. Programmer's Guide
- 16.18.4. Hardware Interfaces
- 16.18.5. Registers
- 16.18.6. Device Interface Functions
- 16.18.7. Hardware Checklist
- 16.18.8. Software Checklist
- 16.19. Key Manager DPE
❱
- 16.19.1. Theory of Operation
- 16.19.2. Design Verification
❱
- 16.19.2.1. Testplan
- 16.19.3. Programmer's Guide
- 16.19.4. Hardware Interfaces
- 16.19.5. Registers
- 16.19.6. Device Interface Functions
- 16.19.7. Hardware Checklist
- 16.19.8. Software Checklist
- 16.20. KMAC
❱
- 16.20.1. Theory of Operation
- 16.20.2. Design Verification
❱
- 16.20.2.1. Testplan
- 16.20.3. Programmer's Guide
- 16.20.4. Hardware Interfaces
- 16.20.5. Registers
- 16.20.6. Device Interface Functions
- 16.20.7. Hardware Checklist
- 16.20.8. Software Checklist
- 16.21. Life Cycle Controller
❱
- 16.21.1. Theory of Operation
- 16.21.2. Design Verification
❱
- 16.21.2.1. Testplan
- 16.21.3. Programmer's Guide
- 16.21.4. Hardware Interfaces
- 16.21.5. Registers
- 16.21.6. Device Interface Functions
- 16.21.7. Hardware Checklist
- 16.21.8. Software Checklist
- 16.22. Mailbox
❱
- 16.22.1. Theory of Operation
- 16.22.2. Design Verification
❱
- 16.22.2.1. Testplan
- 16.22.3. Programmer's Guide
- 16.22.4. Hardware Interfaces
- 16.22.5. Registers
- 16.22.6. Device Interface Functions
- 16.22.7. Hardware Checklist
- 16.22.8. Software Checklist
- 16.23. One Time Programmable (OTP) Controller [templated]
- 16.24. Pattern Generator
❱
- 16.24.1. Theory of Operation
- 16.24.2. Design Verification
❱
- 16.24.2.1. Testplan
- 16.24.3. Programmer's Guide
- 16.24.4. Hardware Interfaces
- 16.24.5. Registers
- 16.24.6. Device Interface Functions
- 16.24.7. Hardware Checklist
- 16.24.8. Software Checklist
- 16.25. Pinmux [templated]
- 16.26. Pulse Width Modulation (PWM) [templated]
- 16.27. Power Management [templated]
- 16.28. Register Access Control List (RACL) Control [templated]
❱
- 16.28.1. RACL
- 16.29. ROM Control
❱
- 16.29.1. Theory of Operation
- 16.29.2. Design Verification
❱
- 16.29.2.1. Testplan
- 16.29.3. Programmer's Guide
- 16.29.4. Hardware Interfaces
- 16.29.5. Registers
- 16.29.6. Device Interface Functions
- 16.29.7. Hardware Checklist
- 16.29.8. Software Checklist
- 16.30. Reset Manager [templated]
- 16.31. Ibex RISC-V Core Wrapper [templated]
- 16.32. RISC-V Debug Manager
❱
- 16.32.1. Theory of Operation
- 16.32.2. Design Verification
❱
- 16.32.2.1. Testplan
- 16.32.3. Programmer's Guide
- 16.32.4. Hardware Interfaces
- 16.32.5. Registers
- 16.32.6. Device Interface Functions
- 16.32.7. Hardware Checklist
- 16.33. Interrupt Controller [templated]
- 16.34. Timer
❱
- 16.34.1. Theory of Operation
- 16.34.2. Design Verification
❱
- 16.34.2.1. Testplan
- 16.34.3. Programmer's Guide
- 16.34.4. Hardware Interfaces
- 16.34.5. Registers
- 16.34.6. Device Interface Functions
- 16.34.7. Hardware Checklist
- 16.34.8. Software Checklist
- 16.35. SoC Debug Access Control
❱
- 16.35.1. Theory of Operation
- 16.35.2. Design Verification
❱
- 16.35.2.1. Testplan
- 16.35.3. Programmer's Guide
- 16.35.4. Hardware Interfaces
- 16.35.5. Registers
- 16.35.6. Device Interface Functions
- 16.35.7. Hardware Checklist
- 16.36. SPI Device
❱
- 16.36.1. Theory of Operation
- 16.36.2. Design Verification
❱
- 16.36.2.1. Testplan
- 16.36.3. Programmer's Guide
- 16.36.4. Hardware Interfaces
- 16.36.5. Registers
- 16.36.6. Device Interface Functions
- 16.36.7. Hardware Checklist
- 16.36.8. Software Checklist
- 16.37. SPI Host
❱
- 16.37.1. Theory of Operation
- 16.37.2. Design Verification
❱
- 16.37.2.1. Testplan
- 16.37.3. Programmer's Guide
- 16.37.4. Hardware Interfaces
- 16.37.5. Registers
- 16.37.6. Device Interface Functions
- 16.37.7. Hardware Checklist
- 16.37.8. Software Checklist
- 16.38. SRAM Controller
❱
- 16.38.1. Theory of Operation
- 16.38.2. Design Verification
❱
- 16.38.2.1. Testplan
- 16.38.3. Programmer's Guide
- 16.38.4. Hardware Interfaces
- 16.38.5. Registers
- 16.38.6. Device Interface Functions
- 16.38.7. Hardware Checklist
- 16.38.8. Software Checklist
- 16.39. System Reset Controller
❱
- 16.39.1. Theory of Operation
- 16.39.2. Design Verification
❱
- 16.39.2.1. Testplan
- 16.39.3. Hardware Interfaces
- 16.39.4. Registers
- 16.39.5. Device Interface Functions
- 16.39.6. Hardware Checklist
- 16.39.7. Software Checklist
- 16.40. TL-UL Bus
❱
- 16.40.1. Design Verification
❱
- 16.40.1.1. Testplan
- 16.40.2. Protocol Checker
- 16.41. UART
❱
- 16.41.1. Theory of Operation
- 16.41.2. Design Verification
❱
- 16.41.2.1. Testplan
- 16.41.3. Programmer's Guide
- 16.41.4. Hardware Interfaces
- 16.41.5. Registers
- 16.41.6. Device Interface Functions
- 16.41.7. Hardware Checklist
- 16.41.8. Software Checklist
- 16.42. USB 2.0
❱
- 16.42.1. Theory of Operation
- 16.42.2. Design Verification
❱
- 16.42.2.1. Testplan
- 16.42.3. Programmer's Guide
- 16.42.4. Suspending and Resuming
- 16.42.5. Hardware Interfaces
- 16.42.6. Registers
- 16.42.7. Device Interface Functions
- 16.42.8. Hardware Checklist
- 16.42.9. Software Checklist
- 17. Hardware Primitives
❱
- 17.1. Keccak Permutation
- 17.2. Linear Feedback Shift Register
- 17.3. Packer
- 17.4. Packer FIFO
- 17.5. Present Scrambler
- 17.6. Prince Scrambler
- 17.7. Pseudo Random Number Generator
- 17.8. SRAM Scrambler
- 17.9. Pre-DV
❱
- 17.9.1. Ascon Duplex Testbench
- 17.9.2. Ascon Permutation Testbench
- 17.9.3. CRC32 Testbench
- 17.9.4. REQ/ACK Synchronizer Testbench
- 17.9.5. Trivium/Bivium Testbench
- 18. Common SystemVerilog and UVM Components
❱
- 18.1. Comportable IP Testbench Architecture
- 18.2. ALERT_ESC Agent
- 18.3. Bus Params Package
- 18.4. Common Interfaces
- 18.5. CSR Utils
- 18.6. CSRNG Agent
- 18.7. DV Library Classes
- 18.8. DV Utils
- 18.9. I2C Agent
- 18.10. JTAG Agent
- 18.11. JTAG DMI Agent
- 18.12. JTAG RISCV Agent
- 18.13. KEY_SIDELOAD Agent
- 18.14. KMAC_APP Agent
- 18.15. Memory Backdoor Scoreboard
- 18.16. Memory Backdoor Utility
- 18.17. Memory Model
- 18.18. PATTGEN Agent
- 18.19. PUSH_PULL Agent
- 18.20. PWM Monitor
- 18.21. RNG Agent
- 18.22. Scoreboard
- 18.23. Simulation SRAM
- 18.24. SPI Agent
- 18.25. String Utils
- 18.26. Test Vectors
- 18.27. Tile Link Agent
- 18.28. UART Agent
- 18.29. USB20 Agent
- 19. Vendored Hardware
- 20. Reference Tops
❱
- 20.1. Top Dragonfly
❱
- 20.1.1. Datasheet
- 20.1.2. Memory Map
- 20.1.3. Pinout / Pinmux Tables
❱
- 20.1.3.1. ASIC
- 20.1.4. Analog Sensor Top
❱
- 20.1.4.1. Registers
- 20.1.5. SoC Proxy
- 20.1.6. Access Control Range Check
❱
- 20.1.6.1. Template Configuration
- 20.1.6.2. Theory of Operation
- 20.1.6.3. Design Verification
❱
- 20.1.6.3.1. Testplan
- 20.1.6.4. Hardware Interfaces
- 20.1.6.5. Registers
- 20.1.6.6. Hardware Checklist
- 20.1.6.7. Software Checklist
- 20.1.7. Alert Handler
❱
- 20.1.7.1. Template Configuration
- 20.1.7.2. Theory of Operation
- 20.1.7.3. Design Verification
❱
- 20.1.7.3.1. Testplan
- 20.1.7.4. Programmer's Guide
- 20.1.7.5. Interface and Registers
- 20.1.7.6. Device Interface Functions
- 20.1.7.7. Hardware Checklist
- 20.1.7.8. Software Checklist
- 20.1.8. Clock Manager
❱
- 20.1.8.1. Template Configuration
- 20.1.8.2. Theory of Operation
- 20.1.8.3. Design Verification
❱
- 20.1.8.3.1. Testplan
- 20.1.8.4. Programmer's Guide
- 20.1.8.5. Hardware Interfaces
- 20.1.8.6. Registers
- 20.1.8.7. Device Interface Functions
- 20.1.8.8. Hardware Checklist
- 20.1.8.9. Software Checklist
- 20.1.9. GPIO
❱
- 20.1.9.1. Template Configuration
- 20.1.9.2. Theory of Operation
- 20.1.9.3. Design Verification
❱
- 20.1.9.3.1. Testplan
- 20.1.9.4. Programmer's Guide
- 20.1.9.5. Hardware Interfaces
- 20.1.9.6. Registers
- 20.1.9.7. Device Interface Functions
- 20.1.9.8. Hardware Checklist
- 20.1.9.9. Software Checklist
- 20.1.10. One Time Programmable (OTP) Controller
❱
- 20.1.10.1. Template Configuration
- 20.1.10.2. Theory of Operation
- 20.1.10.3. Design Verification
❱
- 20.1.10.3.1. Testplan
- 20.1.10.4. Programmer's Guide
- 20.1.10.5. Hardware Interfaces
- 20.1.10.6. Registers
- 20.1.10.7. Device Interface Functions
- 20.1.10.8. Hardware Checklist
- 20.1.10.9. Software Checklist
- 20.1.11. Pinmux
❱
- 20.1.11.1. Template Configuration
- 20.1.11.2. Theory of Operation
- 20.1.11.3. Design Verification
❱
- 20.1.11.3.1. Testplan
- 20.1.11.4. Programmer's Guide
- 20.1.11.5. Hardware Interfaces
- 20.1.11.6. Registers
- 20.1.11.7. Device Interface Functions
- 20.1.11.8. Hardware Checklist
- 20.1.11.9. Software Checklist
- 20.1.12. Power Management
❱
- 20.1.12.1. Template Configuration
- 20.1.12.2. Theory of Operation
- 20.1.12.3. Design Verification
❱
- 20.1.12.3.1. Testplan
- 20.1.12.4. Programmer's Guide
- 20.1.12.5. Hardware Interfaces
- 20.1.12.6. Registers
- 20.1.12.7. Device Interface Functions
- 20.1.12.8. Hardware Checklist
- 20.1.12.9. Software Checklist
- 20.1.13. Register Access Control List (RACL) Control
❱
- 20.1.13.1. Template Configuration
- 20.1.13.2. Theory of Operation
- 20.1.13.3. Programmer's Guide
- 20.1.13.4. Hardware Interfaces
- 20.1.13.5. Registers
- 20.1.13.6. RACL Configuration
- 20.1.14. Reset Manager
❱
- 20.1.14.1. Template Configuration
- 20.1.14.2. Theory of Operation
- 20.1.14.3. Design Verification
❱
- 20.1.14.3.1. Testplan
- 20.1.14.4. Programmer's Guide
- 20.1.14.5. Hardware Interfaces
- 20.1.14.6. Registers
- 20.1.14.7. Device Interface Functions
- 20.1.14.8. Hardware Checklist
- 20.1.14.9. Software Checklist
- 20.1.15. Ibex RISC-V Core Wrapper
❱
- 20.1.15.1. Template Configuration
- 20.1.15.2. Theory of Operation
- 20.1.15.3. Design Verification
❱
- 20.1.15.3.1. Testplan
- 20.1.15.4. Programmer's Guide
- 20.1.15.5. Hardware Interfaces
- 20.1.15.6. Registers
- 20.1.15.7. Device Interface Functions
- 20.1.15.8. Hardware Checklist
- 20.1.15.9. Software Checklist
- 20.1.16. Interrupt Controller
❱
- 20.1.16.1. Template Configuration
- 20.1.16.2. Theory of Operation
- 20.1.16.3. Design Verification
❱
- 20.1.16.3.1. Testplan
- 20.1.16.4. Programmer's Guide
- 20.1.16.5. Interface and Registers
- 20.1.16.6. Device Interface Functions
- 20.1.16.7. Hardware Checklist
- 20.1.16.8. Software Checklist
- 20.2. Top Egret
❱
- 20.2.1. Datasheet
- 20.2.2. Memory Map
- 20.2.3. Design
- 20.2.4. Pinout / Pinmux Tables
❱
- 20.2.4.1. ASIC
- 20.2.4.2. CW310
- 20.2.4.3. CW340
- 20.2.5. Design Verification
❱
- 20.2.5.1. Chip Testplan
- 20.2.6. Analog Sensor Top
❱
- 20.2.6.1. Hardware Interfaces
- 20.2.6.2. Registers
- 20.2.7. Sensor Control
❱
- 20.2.7.1. Theory of Operation
- 20.2.7.2. Programmer's Guide
- 20.2.7.3. Hardware Interfaces
- 20.2.7.4. Registers
- 20.2.7.5. Device Interface Functions
- 20.2.7.6. Hardware Checklist
- 20.2.7.7. Software Checklist
- 20.2.8. TL-UL Checklist
- 20.2.9. Alert Handler
❱
- 20.2.9.1. Template Configuration
- 20.2.9.2. Theory of Operation
- 20.2.9.3. Design Verification
❱
- 20.2.9.3.1. Testplan
- 20.2.9.4. Programmer's Guide
- 20.2.9.5. Interface and Registers
- 20.2.9.6. Device Interface Functions
- 20.2.9.7. Hardware Checklist
- 20.2.9.8. Software Checklist
- 20.2.10. Clock Manager
❱
- 20.2.10.1. Template Configuration
- 20.2.10.2. Theory of Operation
- 20.2.10.3. Design Verification
❱
- 20.2.10.3.1. Testplan
- 20.2.10.4. Programmer's Guide
- 20.2.10.5. Hardware Interfaces
- 20.2.10.6. Registers
- 20.2.10.7. Device Interface Functions
- 20.2.10.8. Hardware Checklist
- 20.2.10.9. Software Checklist
- 20.2.11. Flash Controller
❱
- 20.2.11.1. Template Configuration
- 20.2.11.2. Theory of Operation
- 20.2.11.3. Design Verification
❱
- 20.2.11.3.1. Testplan
- 20.2.11.4. Programmer's Guide
- 20.2.11.5. Hardware Interfaces
- 20.2.11.6. Registers
- 20.2.11.7. Device Interface Functions
- 20.2.11.8. Hardware Checklist
- 20.2.11.9. Software Checklist
- 20.2.12. GPIO
❱
- 20.2.12.1. Template Configuration
- 20.2.12.2. Theory of Operation
- 20.2.12.3. Design Verification
❱
- 20.2.12.3.1. Testplan
- 20.2.12.4. Programmer's Guide
- 20.2.12.5. Hardware Interfaces
- 20.2.12.6. Registers
- 20.2.12.7. Device Interface Functions
- 20.2.12.8. Hardware Checklist
- 20.2.12.9. Software Checklist
- 20.2.13. One Time Programmable (OTP) Controller
❱
- 20.2.13.1. Template Configuration
- 20.2.13.2. Theory of Operation
- 20.2.13.3. Design Verification
❱
- 20.2.13.3.1. Testplan
- 20.2.13.4. Programmer's Guide
- 20.2.13.5. Hardware Interfaces
- 20.2.13.6. Registers
- 20.2.13.7. Device Interface Functions
- 20.2.13.8. Hardware Checklist
- 20.2.13.9. Software Checklist
- 20.2.14. Pinmux
❱
- 20.2.14.1. Template Configuration
- 20.2.14.2. Theory of Operation
- 20.2.14.3. Design Verification
❱
- 20.2.14.3.1. Testplan
- 20.2.14.4. Programmer's Guide
- 20.2.14.5. Hardware Interfaces
- 20.2.14.6. Registers
- 20.2.14.7. Device Interface Functions
- 20.2.14.8. Hardware Checklist
- 20.2.14.9. Software Checklist
- 20.2.15. Pulse Width Modulation (PWM)
❱
- 20.2.15.1. Template Configuration
- 20.2.15.2. Theory of Operation
- 20.2.15.3. Design Verification
❱
- 20.2.15.3.1. Testplan
- 20.2.15.4. Programmer's Guide
- 20.2.15.5. Hardware Interfaces
- 20.2.15.6. Registers
- 20.2.15.7. Device Interface Functions
- 20.2.15.8. Hardware Checklist
- 20.2.15.9. Software Checklist
- 20.2.16. Power Management
❱
- 20.2.16.1. Template Configuration
- 20.2.16.2. Theory of Operation
- 20.2.16.3. Design Verification
❱
- 20.2.16.3.1. Testplan
- 20.2.16.4. Programmer's Guide
- 20.2.16.5. Hardware Interfaces
- 20.2.16.6. Registers
- 20.2.16.7. Device Interface Functions
- 20.2.16.8. Hardware Checklist
- 20.2.16.9. Software Checklist
- 20.2.17. Reset Manager
❱
- 20.2.17.1. Template Configuration
- 20.2.17.2. Theory of Operation
- 20.2.17.3. Design Verification
❱
- 20.2.17.3.1. Testplan
- 20.2.17.4. Programmer's Guide
- 20.2.17.5. Hardware Interfaces
- 20.2.17.6. Registers
- 20.2.17.7. Device Interface Functions
- 20.2.17.8. Hardware Checklist
- 20.2.17.9. Software Checklist
- 20.2.18. Ibex RISC-V Core Wrapper
❱
- 20.2.18.1. Template Configuration
- 20.2.18.2. Theory of Operation
- 20.2.18.3. Design Verification
❱
- 20.2.18.3.1. Testplan
- 20.2.18.4. Programmer's Guide
- 20.2.18.5. Hardware Interfaces
- 20.2.18.6. Registers
- 20.2.18.7. Device Interface Functions
- 20.2.18.8. Hardware Checklist
- 20.2.18.9. Software Checklist
- 20.2.19. Interrupt Controller
❱
- 20.2.19.1. Template Configuration
- 20.2.19.2. Theory of Operation
- 20.2.19.3. Design Verification
❱
- 20.2.19.3.1. Testplan
- 20.2.19.4. Programmer's Guide
- 20.2.19.5. Interface and Registers
- 20.2.19.6. Device Interface Functions
- 20.2.19.7. Hardware Checklist
- 20.2.19.8. Software Checklist
- 21. Verification Methodology
❱
- 21.1. Security Countermeasure Verification Framework
- 21.2. Formal Assertions
- Software
- 22. Software Overview
❱
- 22.1. Rust for C Developers
- 23. Build Software
❱
- 23.1. External dependencies
- 23.2. Build & Test Rules
❱
- 23.2.1. Overriding FPGA Bitstream Defaults
- 23.3. Top selection
❱
- 23.3.1. Top Description
- 23.3.2. Creating a new top
- 24. Device Software
❱
- 24.1. Device Libraries
❱
- 24.1.1. Standard Library
❱
- 24.1.1.1. Freestanding C Headers
- 24.1.2. Device Interface Function (DIF) Library
❱
- 24.1.2.1. DIF Development
- 24.1.3. Runtime Library
- 24.1.4. Top-Level Test Libraries
❱
- 24.1.4.1. On-Device Test Framework
- 24.1.4.2. Test Boot ROM
- 24.1.5. Crypto Library
- 24.2. Silicon Creator Software
❱
- 24.2.1. Boot Log
- 24.2.2. Manufacturing Firmware
❱
- 24.2.2.1. Test Plan
- 24.2.2.2. Extensions
- 24.2.2.3. Keys
❱
- 24.2.2.3.1. Fake Keys
- 24.2.3. ROM
❱
- 24.2.3.1. ROM Specification
- 24.2.3.2. Bootstrap
- 24.2.3.3. Memory Protection
- 24.2.3.4. Root Keys
- 24.2.3.5. Signature Verification
❱
- 24.2.3.5.1. Sigverify Test Generation
- 24.2.3.6. Shutdown Specification
- 24.2.3.7. Signoff Test Plan
- 24.2.3.8. E2E tests
❱
- 24.2.3.8.1. Test Plan
- 24.2.3.9. Hooks
- 24.2.3.10. Regenerating Fake Keys
- 24.2.4. ROM_EXT
❱
- 24.2.4.1. ROM_EXT for Silicon Validation
- 24.2.4.2. ROM_EXT Ownership Transfer
- 24.2.4.3. ROM_EXT Rescue Protocol
- 24.2.4.4. Manifest Format
- 24.2.4.5. E2E Tests
- 24.2.4.6. Immutable Section
❱
- 24.2.4.6.1. Prebuilts
- 24.2.4.7. Keys
- 24.2.5. Guidance for Silicon Creator Code
- 24.3. Top-Level Tests
❱
- 24.3.1. Manufacturer Test Hooks
- 24.3.2. Cryptotest
❱
- 24.3.2.1. SPHINCS+ Test Vectors
- 24.3.3. Silicon Validation
❱
- 24.3.3.1. Developer Guide
- 24.3.4. Penetration Tests
- 25. Host Software
❱
- 25.1. OpenTitanLib
❱
- 25.1.1. Bitbanging
- 25.2. OpenTitanTool
- 25.3. OpenTitanSession
- 25.4. Certificate Generator
- 25.5. Hardware Abstraction Layers
- 25.6. Transports
- 25.7. Hardware Security Module (HSM) tool
❱
- 25.7.1. Requirements
- 25.8. TPM2 Test Server
- 25.9. USB Streaming Tests
- 25.10. Penetration Test Utilities
- 26. Vendored Software
- 27. RISC-V toolchain
- Security
- 28. Overview
- 29. Threat Model
- 30. Logical Security Model
- 31. Specifications
❱
- 31.1. Device Life Cycle
- 31.2. Provisioning
- 31.3. Secure Boot
- 31.4. Identities and Root Keys
- 31.5. Attestation
- 31.6. Firmware Update
- 31.7. Ownership Transfer
- 32. Cryptographic Library
❱
- 32.1. API
- 32.2. Contributing
- 33. Implementation Guidelines
❱
- 33.1. Hardware Implementation
- 33.2. Reset/Non-Reset Flops
- Tooling
- 34. Tooling Reference
- 35. Architectural Composition Engine
❱
- 35.1. topgen: Top Generator
- 35.2. ipgen: Generate IP Blocks from IP Templates
- 35.3. reggen & regtool: Register Generator
❱
- 35.3.1. Setup and use of regtool
- 35.4. tlgen: Crossbar Generation
- 35.5. uvmdvgen: Initial Testbench Auto-generation
- 35.6. fpvgen: Initial FPV Testbench Generation
- 35.7. dtgen: Generate Device Tables
- 35.8. ralgen: RAL Model Generation
- 35.9. Design-Related Tooling
- 35.10. i2csvg: Generate SVGs of I2C Commands
❱
- 35.10.1. SMBus
- 36. dvsim
❱
- 36.1. Design Document
- 36.2. Testplanner
- 36.3. Glossary
- 36.4. testplantool: Read and Edit Testplans
- 37. vendor: Vendoring In Tool
- 38. Building Documentation
- 39. Docker Container