1. Introduction
  2. About Pavona
  3. Getting Started
    1. Intro to Hardware
    2. Intro to Software
  4. Using Pavona
  5. Verilator Setup
  6. FPGA Setup
    1. Vivado Setup
    2. Get a Board
    3. FPGA Reference Manual
      1. Using OpenOCD
      2. Debugging with an ILA
  7. Design Verification Setup
    1. Formal Verification Setup
  8. Synthesis Flow
    1. Linting
  9. License
  10. Contributing
  11. Contributing
    1. Vendoring Philosophy
  12. Style
    1. Verilog
      1. DV
    2. RISC-V Assembly
    3. ACC Assembly
    4. C & C++
    5. Python
    6. Hjson
    7. Markdown
  13. Directory Structure
  14. GitHub Notes
  15. Bazel Notes
  16. Continuous Integration
    1. FAQs
  17. Glossary
  18. Hardware
  19. Hardware Overview
    1. Comportability
    2. Development Stages
    3. Checklists
    4. Cores
    5. IP Template Generation
  20. Hardware IP Blocks
    1. Asymmetric Cryptographic Coprocessor (ACC)
      1. Introduction to ACC
      2. Theory of Operation
      3. Developing ACC
        1. Writing Software
        2. Example Code Snippets
      4. ISA Guide
      5. Design Verification
        1. Testplan
        2. Random Instruction Generator
          1. Internals
          2. Configuration
        3. memutil wrapper
        4. ACC Simulation Software
        5. Tracer
        6. Formal Masking Verification Using Alma
      6. Functional Coverage
      7. Programmer's Guide
      8. Hardware Interfaces
      9. Registers
      10. Hardware Checklist
      11. Software Checklist
    2. Access Control Range Check [templated]
    3. Analog to Digital Converter Control
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
    4. Advanced Encryption Standard (AES)
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
      8. Software Checklist
    5. Alert Handler [templated]
    6. Always-On Timer
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
      8. Software Checklist
    7. Ascon
      1. Background
      2. Theory of Operation
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Hardware Checklist
    8. Clock Manager [templated]
    9. Cryptographically Secure Random Number Generator (CSRNG)
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
      8. Software Checklist
    10. DMA
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
      8. Software Checklist
    11. Entropy Distribution Network (EDN)
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
      8. Software Checklist
    12. Entropy Source
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
      8. Software Checklist
    13. Flash Controller [templated]
    14. Flash Macro Wrapper
      1. Overview
    15. GPIO [templated]
    16. HMAC
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
      8. Software Checklist
    17. I2C
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
      8. Software Checklist
    18. Key Manager
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
      8. Software Checklist
    19. Key Manager DPE
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
      8. Software Checklist
    20. KMAC
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
      8. Software Checklist
    21. Life Cycle Controller
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
      8. Software Checklist
    22. Mailbox
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
      8. Software Checklist
    23. One Time Programmable (OTP) Controller [templated]
    24. Pattern Generator
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
      8. Software Checklist
    25. Pinmux [templated]
    26. Pulse Width Modulation (PWM) [templated]
    27. Power Management [templated]
    28. Register Access Control List (RACL) Control [templated]
      1. RACL
    29. ROM Control
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
      8. Software Checklist
    30. Reset Manager [templated]
    31. Ibex RISC-V Core Wrapper [templated]
    32. RISC-V Debug Manager
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
    33. Interrupt Controller [templated]
    34. Timer
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
      8. Software Checklist
    35. SoC Debug Access Control
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
    36. SPI Device
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
      8. Software Checklist
    37. SPI Host
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
      8. Software Checklist
    38. SRAM Controller
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
      8. Software Checklist
    39. System Reset Controller
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Hardware Interfaces
      4. Registers
      5. Device Interface Functions
      6. Hardware Checklist
      7. Software Checklist
    40. TL-UL Bus
      1. Design Verification
        1. Testplan
      2. Protocol Checker
    41. UART
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Hardware Interfaces
      5. Registers
      6. Device Interface Functions
      7. Hardware Checklist
      8. Software Checklist
    42. USB 2.0
      1. Theory of Operation
      2. Design Verification
        1. Testplan
      3. Programmer's Guide
      4. Suspending and Resuming
      5. Hardware Interfaces
      6. Registers
      7. Device Interface Functions
      8. Hardware Checklist
      9. Software Checklist
  21. Hardware Primitives
    1. Keccak Permutation
    2. Linear Feedback Shift Register
    3. Packer
    4. Packer FIFO
    5. Present Scrambler
    6. Prince Scrambler
    7. Pseudo Random Number Generator
    8. SRAM Scrambler
    9. Pre-DV
      1. Ascon Duplex Testbench
      2. Ascon Permutation Testbench
      3. CRC32 Testbench
      4. REQ/ACK Synchronizer Testbench
      5. Trivium/Bivium Testbench
  22. Common SystemVerilog and UVM Components
    1. Comportable IP Testbench Architecture
    2. ALERT_ESC Agent
    3. Bus Params Package
    4. Common Interfaces
    5. CSR Utils
    6. CSRNG Agent
    7. DV Library Classes
    8. DV Utils
    9. I2C Agent
    10. JTAG Agent
    11. JTAG DMI Agent
    12. JTAG RISCV Agent
    13. KEY_SIDELOAD Agent
    14. KMAC_APP Agent
    15. Memory Backdoor Scoreboard
    16. Memory Backdoor Utility
    17. Memory Model
    18. PATTGEN Agent
    19. PUSH_PULL Agent
    20. PWM Monitor
    21. RNG Agent
    22. Scoreboard
    23. Simulation SRAM
    24. SPI Agent
    25. String Utils
    26. Test Vectors
    27. Tile Link Agent
    28. UART Agent
    29. USB20 Agent
  23. Vendored Hardware
  24. Reference Tops
    1. Top Dragonfly
      1. Datasheet
      2. Memory Map
      3. Pinout / Pinmux Tables
        1. ASIC
      4. Analog Sensor Top
        1. Registers
      5. SoC Proxy
      6. Access Control Range Check
        1. Template Configuration
        2. Theory of Operation
        3. Design Verification
          1. Testplan
        4. Hardware Interfaces
        5. Registers
        6. Hardware Checklist
        7. Software Checklist
      7. Alert Handler
        1. Template Configuration
        2. Theory of Operation
        3. Design Verification
          1. Testplan
        4. Programmer's Guide
        5. Interface and Registers
        6. Device Interface Functions
        7. Hardware Checklist
        8. Software Checklist
      8. Clock Manager
        1. Template Configuration
        2. Theory of Operation
        3. Design Verification
          1. Testplan
        4. Programmer's Guide
        5. Hardware Interfaces
        6. Registers
        7. Device Interface Functions
        8. Hardware Checklist
        9. Software Checklist
      9. GPIO
        1. Template Configuration
        2. Theory of Operation
        3. Design Verification
          1. Testplan
        4. Programmer's Guide
        5. Hardware Interfaces
        6. Registers
        7. Device Interface Functions
        8. Hardware Checklist
        9. Software Checklist
      10. One Time Programmable (OTP) Controller
        1. Template Configuration
        2. Theory of Operation
        3. Design Verification
          1. Testplan
        4. Programmer's Guide
        5. Hardware Interfaces
        6. Registers
        7. Device Interface Functions
        8. Hardware Checklist
        9. Software Checklist
      11. Pinmux
        1. Template Configuration
        2. Theory of Operation
        3. Design Verification
          1. Testplan
        4. Programmer's Guide
        5. Hardware Interfaces
        6. Registers
        7. Device Interface Functions
        8. Hardware Checklist
        9. Software Checklist
      12. Power Management
        1. Template Configuration
        2. Theory of Operation
        3. Design Verification
          1. Testplan
        4. Programmer's Guide
        5. Hardware Interfaces
        6. Registers
        7. Device Interface Functions
        8. Hardware Checklist
        9. Software Checklist
      13. Register Access Control List (RACL) Control
        1. Template Configuration
        2. Theory of Operation
        3. Programmer's Guide
        4. Hardware Interfaces
        5. Registers
        6. RACL Configuration
      14. Reset Manager
        1. Template Configuration
        2. Theory of Operation
        3. Design Verification
          1. Testplan
        4. Programmer's Guide
        5. Hardware Interfaces
        6. Registers
        7. Device Interface Functions
        8. Hardware Checklist
        9. Software Checklist
      15. Ibex RISC-V Core Wrapper
        1. Template Configuration
        2. Theory of Operation
        3. Design Verification
          1. Testplan
        4. Programmer's Guide
        5. Hardware Interfaces
        6. Registers
        7. Device Interface Functions
        8. Hardware Checklist
        9. Software Checklist
      16. Interrupt Controller
        1. Template Configuration
        2. Theory of Operation
        3. Design Verification
          1. Testplan
        4. Programmer's Guide
        5. Interface and Registers
        6. Device Interface Functions
        7. Hardware Checklist
        8. Software Checklist
    2. Top Egret
      1. Datasheet
      2. Memory Map
      3. Design
      4. Pinout / Pinmux Tables
        1. ASIC
        2. CW310
        3. CW340
      5. Design Verification
        1. Chip Testplan
      6. Analog Sensor Top
        1. Hardware Interfaces
        2. Registers
      7. Sensor Control
        1. Theory of Operation
        2. Programmer's Guide
        3. Hardware Interfaces
        4. Registers
        5. Device Interface Functions
        6. Hardware Checklist
        7. Software Checklist
      8. TL-UL Checklist
      9. Alert Handler
        1. Template Configuration
        2. Theory of Operation
        3. Design Verification
          1. Testplan
        4. Programmer's Guide
        5. Interface and Registers
        6. Device Interface Functions
        7. Hardware Checklist
        8. Software Checklist
      10. Clock Manager
        1. Template Configuration
        2. Theory of Operation
        3. Design Verification
          1. Testplan
        4. Programmer's Guide
        5. Hardware Interfaces
        6. Registers
        7. Device Interface Functions
        8. Hardware Checklist
        9. Software Checklist
      11. Flash Controller
        1. Template Configuration
        2. Theory of Operation
        3. Design Verification
          1. Testplan
        4. Programmer's Guide
        5. Hardware Interfaces
        6. Registers
        7. Device Interface Functions
        8. Hardware Checklist
        9. Software Checklist
      12. GPIO
        1. Template Configuration
        2. Theory of Operation
        3. Design Verification
          1. Testplan
        4. Programmer's Guide
        5. Hardware Interfaces
        6. Registers
        7. Device Interface Functions
        8. Hardware Checklist
        9. Software Checklist
      13. One Time Programmable (OTP) Controller
        1. Template Configuration
        2. Theory of Operation
        3. Design Verification
          1. Testplan
        4. Programmer's Guide
        5. Hardware Interfaces
        6. Registers
        7. Device Interface Functions
        8. Hardware Checklist
        9. Software Checklist
      14. Pinmux
        1. Template Configuration
        2. Theory of Operation
        3. Design Verification
          1. Testplan
        4. Programmer's Guide
        5. Hardware Interfaces
        6. Registers
        7. Device Interface Functions
        8. Hardware Checklist
        9. Software Checklist
      15. Pulse Width Modulation (PWM)
        1. Template Configuration
        2. Theory of Operation
        3. Design Verification
          1. Testplan
        4. Programmer's Guide
        5. Hardware Interfaces
        6. Registers
        7. Device Interface Functions
        8. Hardware Checklist
        9. Software Checklist
      16. Power Management
        1. Template Configuration
        2. Theory of Operation
        3. Design Verification
          1. Testplan
        4. Programmer's Guide
        5. Hardware Interfaces
        6. Registers
        7. Device Interface Functions
        8. Hardware Checklist
        9. Software Checklist
      17. Reset Manager
        1. Template Configuration
        2. Theory of Operation
        3. Design Verification
          1. Testplan
        4. Programmer's Guide
        5. Hardware Interfaces
        6. Registers
        7. Device Interface Functions
        8. Hardware Checklist
        9. Software Checklist
      18. Ibex RISC-V Core Wrapper
        1. Template Configuration
        2. Theory of Operation
        3. Design Verification
          1. Testplan
        4. Programmer's Guide
        5. Hardware Interfaces
        6. Registers
        7. Device Interface Functions
        8. Hardware Checklist
        9. Software Checklist
      19. Interrupt Controller
        1. Template Configuration
        2. Theory of Operation
        3. Design Verification
          1. Testplan
        4. Programmer's Guide
        5. Interface and Registers
        6. Device Interface Functions
        7. Hardware Checklist
        8. Software Checklist
  25. Verification Methodology
    1. Security Countermeasure Verification Framework
    2. Formal Assertions
  26. Software
  27. Software Overview
    1. Rust for C Developers
  28. Build Software
    1. External dependencies
    2. Build & Test Rules
      1. Overriding FPGA Bitstream Defaults
    3. Top selection
      1. Top Description
      2. Creating a new top
  29. Device Software
    1. Device Libraries
      1. Standard Library
        1. Freestanding C Headers
      2. Device Interface Function (DIF) Library
        1. DIF Development
      3. Runtime Library
      4. Top-Level Test Libraries
        1. On-Device Test Framework
        2. Test Boot ROM
      5. Crypto Library
    2. Silicon Creator Software
      1. Boot Log
      2. Manufacturing Firmware
        1. Test Plan
        2. Extensions
        3. Keys
          1. Fake Keys
      3. ROM
        1. ROM Specification
        2. Bootstrap
        3. Memory Protection
        4. Root Keys
        5. Signature Verification
          1. Sigverify Test Generation
        6. Shutdown Specification
        7. Signoff Test Plan
        8. E2E tests
          1. Test Plan
        9. Hooks
        10. Regenerating Fake Keys
      4. ROM_EXT
        1. ROM_EXT for Silicon Validation
        2. ROM_EXT Ownership Transfer
        3. ROM_EXT Rescue Protocol
        4. Manifest Format
        5. E2E Tests
        6. Immutable Section
          1. Prebuilts
        7. Keys
      5. Guidance for Silicon Creator Code
    3. Top-Level Tests
      1. Manufacturer Test Hooks
      2. Cryptotest
        1. SPHINCS+ Test Vectors
      3. Silicon Validation
        1. Developer Guide
      4. Penetration Tests
  30. Host Software
    1. OpenTitanLib
      1. Bitbanging
    2. OpenTitanTool
    3. OpenTitanSession
    4. Certificate Generator
    5. Hardware Abstraction Layers
    6. Transports
    7. Hardware Security Module (HSM) tool
      1. Requirements
    8. TPM2 Test Server
    9. USB Streaming Tests
    10. Penetration Test Utilities
  31. Vendored Software
  32. RISC-V toolchain
  33. Security
  34. Overview
  35. Threat Model
  36. Logical Security Model
  37. Specifications
    1. Device Life Cycle
    2. Provisioning
    3. Secure Boot
    4. Identities and Root Keys
    5. Attestation
    6. Firmware Update
    7. Ownership Transfer
  38. Cryptographic Library
    1. API
    2. Contributing
  39. Implementation Guidelines
    1. Hardware Implementation
    2. Reset/Non-Reset Flops
  40. Tooling
  41. Tooling Reference
  42. Architectural Composition Engine
    1. topgen: Top Generator
    2. ipgen: Generate IP Blocks from IP Templates
    3. reggen & regtool: Register Generator
      1. Setup and use of regtool
    4. tlgen: Crossbar Generation
    5. uvmdvgen: Initial Testbench Auto-generation
    6. fpvgen: Initial FPV Testbench Generation
    7. dtgen: Generate Device Tables
    8. ralgen: RAL Model Generation
    9. Design-Related Tooling
    10. i2csvg: Generate SVGs of I2C Commands
      1. SMBus
  43. dvsim
    1. Design Document
    2. Testplanner
    3. Glossary
    4. testplantool: Read and Edit Testplans
  44. vendor: Vendoring In Tool
  45. Building Documentation
  46. Docker Container