flash_macro_wrapper_regs.h

Go to the documentation of this file.

/**
 * @file
 * @brief Generated register defines for flash_macro_wrapper
 */
 
// Copyright information found in source file:
// Copyright zeroRISC Inc.
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _FLASH_MACRO_WRAPPER_REG_DEFS_
#define _FLASH_MACRO_WRAPPER_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Register width
#define FLASH_MACRO_WRAPPER_PARAM_REG_WIDTH 32
 
 
#define FLASH_MACRO_WRAPPER_CSR0_REGWEN_REG_OFFSET 0x0
#define FLASH_MACRO_WRAPPER_CSR0_REGWEN_REG_RESVAL 0x1u
#define FLASH_MACRO_WRAPPER_CSR0_REGWEN_FIELD0_BIT 0
 
 
#define FLASH_MACRO_WRAPPER_CSR1_REG_OFFSET 0x4
#define FLASH_MACRO_WRAPPER_CSR1_REG_RESVAL 0x0u
#define FLASH_MACRO_WRAPPER_CSR1_FIELD0_MASK 0xffu
#define FLASH_MACRO_WRAPPER_CSR1_FIELD0_OFFSET 0
#define FLASH_MACRO_WRAPPER_CSR1_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR1_FIELD0_MASK, .index = FLASH_MACRO_WRAPPER_CSR1_FIELD0_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR1_FIELD1_MASK 0x1fu
#define FLASH_MACRO_WRAPPER_CSR1_FIELD1_OFFSET 8
#define FLASH_MACRO_WRAPPER_CSR1_FIELD1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR1_FIELD1_MASK, .index = FLASH_MACRO_WRAPPER_CSR1_FIELD1_OFFSET })
 
 
#define FLASH_MACRO_WRAPPER_CSR2_REG_OFFSET 0x8
#define FLASH_MACRO_WRAPPER_CSR2_REG_RESVAL 0x0u
#define FLASH_MACRO_WRAPPER_CSR2_FIELD0_BIT 0
#define FLASH_MACRO_WRAPPER_CSR2_FIELD1_BIT 1
#define FLASH_MACRO_WRAPPER_CSR2_FIELD2_BIT 2
#define FLASH_MACRO_WRAPPER_CSR2_FIELD3_BIT 3
#define FLASH_MACRO_WRAPPER_CSR2_FIELD4_BIT 4
#define FLASH_MACRO_WRAPPER_CSR2_FIELD5_BIT 5
#define FLASH_MACRO_WRAPPER_CSR2_FIELD6_BIT 6
#define FLASH_MACRO_WRAPPER_CSR2_FIELD7_BIT 7
 
 
#define FLASH_MACRO_WRAPPER_CSR3_REG_OFFSET 0xc
#define FLASH_MACRO_WRAPPER_CSR3_REG_RESVAL 0x0u
#define FLASH_MACRO_WRAPPER_CSR3_FIELD0_MASK 0xfu
#define FLASH_MACRO_WRAPPER_CSR3_FIELD0_OFFSET 0
#define FLASH_MACRO_WRAPPER_CSR3_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR3_FIELD0_MASK, .index = FLASH_MACRO_WRAPPER_CSR3_FIELD0_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR3_FIELD1_MASK 0xfu
#define FLASH_MACRO_WRAPPER_CSR3_FIELD1_OFFSET 4
#define FLASH_MACRO_WRAPPER_CSR3_FIELD1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR3_FIELD1_MASK, .index = FLASH_MACRO_WRAPPER_CSR3_FIELD1_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR3_FIELD2_MASK 0x7u
#define FLASH_MACRO_WRAPPER_CSR3_FIELD2_OFFSET 8
#define FLASH_MACRO_WRAPPER_CSR3_FIELD2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR3_FIELD2_MASK, .index = FLASH_MACRO_WRAPPER_CSR3_FIELD2_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR3_FIELD3_MASK 0x7u
#define FLASH_MACRO_WRAPPER_CSR3_FIELD3_OFFSET 11
#define FLASH_MACRO_WRAPPER_CSR3_FIELD3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR3_FIELD3_MASK, .index = FLASH_MACRO_WRAPPER_CSR3_FIELD3_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR3_FIELD4_MASK 0x7u
#define FLASH_MACRO_WRAPPER_CSR3_FIELD4_OFFSET 14
#define FLASH_MACRO_WRAPPER_CSR3_FIELD4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR3_FIELD4_MASK, .index = FLASH_MACRO_WRAPPER_CSR3_FIELD4_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR3_FIELD5_MASK 0x7u
#define FLASH_MACRO_WRAPPER_CSR3_FIELD5_OFFSET 17
#define FLASH_MACRO_WRAPPER_CSR3_FIELD5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR3_FIELD5_MASK, .index = FLASH_MACRO_WRAPPER_CSR3_FIELD5_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR3_FIELD6_BIT 20
#define FLASH_MACRO_WRAPPER_CSR3_FIELD7_MASK 0x7u
#define FLASH_MACRO_WRAPPER_CSR3_FIELD7_OFFSET 21
#define FLASH_MACRO_WRAPPER_CSR3_FIELD7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR3_FIELD7_MASK, .index = FLASH_MACRO_WRAPPER_CSR3_FIELD7_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR3_FIELD8_MASK 0x3u
#define FLASH_MACRO_WRAPPER_CSR3_FIELD8_OFFSET 24
#define FLASH_MACRO_WRAPPER_CSR3_FIELD8_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR3_FIELD8_MASK, .index = FLASH_MACRO_WRAPPER_CSR3_FIELD8_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR3_FIELD9_MASK 0x3u
#define FLASH_MACRO_WRAPPER_CSR3_FIELD9_OFFSET 26
#define FLASH_MACRO_WRAPPER_CSR3_FIELD9_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR3_FIELD9_MASK, .index = FLASH_MACRO_WRAPPER_CSR3_FIELD9_OFFSET })
 
 
#define FLASH_MACRO_WRAPPER_CSR4_REG_OFFSET 0x10
#define FLASH_MACRO_WRAPPER_CSR4_REG_RESVAL 0x0u
#define FLASH_MACRO_WRAPPER_CSR4_FIELD0_MASK 0x7u
#define FLASH_MACRO_WRAPPER_CSR4_FIELD0_OFFSET 0
#define FLASH_MACRO_WRAPPER_CSR4_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR4_FIELD0_MASK, .index = FLASH_MACRO_WRAPPER_CSR4_FIELD0_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR4_FIELD1_MASK 0x7u
#define FLASH_MACRO_WRAPPER_CSR4_FIELD1_OFFSET 3
#define FLASH_MACRO_WRAPPER_CSR4_FIELD1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR4_FIELD1_MASK, .index = FLASH_MACRO_WRAPPER_CSR4_FIELD1_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR4_FIELD2_MASK 0x7u
#define FLASH_MACRO_WRAPPER_CSR4_FIELD2_OFFSET 6
#define FLASH_MACRO_WRAPPER_CSR4_FIELD2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR4_FIELD2_MASK, .index = FLASH_MACRO_WRAPPER_CSR4_FIELD2_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR4_FIELD3_MASK 0x7u
#define FLASH_MACRO_WRAPPER_CSR4_FIELD3_OFFSET 9
#define FLASH_MACRO_WRAPPER_CSR4_FIELD3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR4_FIELD3_MASK, .index = FLASH_MACRO_WRAPPER_CSR4_FIELD3_OFFSET })
 
 
#define FLASH_MACRO_WRAPPER_CSR5_REG_OFFSET 0x14
#define FLASH_MACRO_WRAPPER_CSR5_REG_RESVAL 0x0u
#define FLASH_MACRO_WRAPPER_CSR5_FIELD0_MASK 0x7u
#define FLASH_MACRO_WRAPPER_CSR5_FIELD0_OFFSET 0
#define FLASH_MACRO_WRAPPER_CSR5_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR5_FIELD0_MASK, .index = FLASH_MACRO_WRAPPER_CSR5_FIELD0_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR5_FIELD1_MASK 0x3u
#define FLASH_MACRO_WRAPPER_CSR5_FIELD1_OFFSET 3
#define FLASH_MACRO_WRAPPER_CSR5_FIELD1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR5_FIELD1_MASK, .index = FLASH_MACRO_WRAPPER_CSR5_FIELD1_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR5_FIELD2_MASK 0x1ffu
#define FLASH_MACRO_WRAPPER_CSR5_FIELD2_OFFSET 5
#define FLASH_MACRO_WRAPPER_CSR5_FIELD2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR5_FIELD2_MASK, .index = FLASH_MACRO_WRAPPER_CSR5_FIELD2_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR5_FIELD3_MASK 0x1fu
#define FLASH_MACRO_WRAPPER_CSR5_FIELD3_OFFSET 14
#define FLASH_MACRO_WRAPPER_CSR5_FIELD3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR5_FIELD3_MASK, .index = FLASH_MACRO_WRAPPER_CSR5_FIELD3_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR5_FIELD4_MASK 0xfu
#define FLASH_MACRO_WRAPPER_CSR5_FIELD4_OFFSET 19
#define FLASH_MACRO_WRAPPER_CSR5_FIELD4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR5_FIELD4_MASK, .index = FLASH_MACRO_WRAPPER_CSR5_FIELD4_OFFSET })
 
 
#define FLASH_MACRO_WRAPPER_CSR6_REG_OFFSET 0x18
#define FLASH_MACRO_WRAPPER_CSR6_REG_RESVAL 0x0u
#define FLASH_MACRO_WRAPPER_CSR6_FIELD0_MASK 0x7u
#define FLASH_MACRO_WRAPPER_CSR6_FIELD0_OFFSET 0
#define FLASH_MACRO_WRAPPER_CSR6_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR6_FIELD0_MASK, .index = FLASH_MACRO_WRAPPER_CSR6_FIELD0_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR6_FIELD1_MASK 0x7u
#define FLASH_MACRO_WRAPPER_CSR6_FIELD1_OFFSET 3
#define FLASH_MACRO_WRAPPER_CSR6_FIELD1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR6_FIELD1_MASK, .index = FLASH_MACRO_WRAPPER_CSR6_FIELD1_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR6_FIELD2_MASK 0xffu
#define FLASH_MACRO_WRAPPER_CSR6_FIELD2_OFFSET 6
#define FLASH_MACRO_WRAPPER_CSR6_FIELD2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR6_FIELD2_MASK, .index = FLASH_MACRO_WRAPPER_CSR6_FIELD2_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR6_FIELD3_MASK 0x7u
#define FLASH_MACRO_WRAPPER_CSR6_FIELD3_OFFSET 14
#define FLASH_MACRO_WRAPPER_CSR6_FIELD3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR6_FIELD3_MASK, .index = FLASH_MACRO_WRAPPER_CSR6_FIELD3_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR6_FIELD4_MASK 0x3u
#define FLASH_MACRO_WRAPPER_CSR6_FIELD4_OFFSET 17
#define FLASH_MACRO_WRAPPER_CSR6_FIELD4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR6_FIELD4_MASK, .index = FLASH_MACRO_WRAPPER_CSR6_FIELD4_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR6_FIELD5_MASK 0x3u
#define FLASH_MACRO_WRAPPER_CSR6_FIELD5_OFFSET 19
#define FLASH_MACRO_WRAPPER_CSR6_FIELD5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR6_FIELD5_MASK, .index = FLASH_MACRO_WRAPPER_CSR6_FIELD5_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR6_FIELD6_MASK 0x3u
#define FLASH_MACRO_WRAPPER_CSR6_FIELD6_OFFSET 21
#define FLASH_MACRO_WRAPPER_CSR6_FIELD6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR6_FIELD6_MASK, .index = FLASH_MACRO_WRAPPER_CSR6_FIELD6_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR6_FIELD7_BIT 23
#define FLASH_MACRO_WRAPPER_CSR6_FIELD8_BIT 24
 
 
#define FLASH_MACRO_WRAPPER_CSR7_REG_OFFSET 0x1c
#define FLASH_MACRO_WRAPPER_CSR7_REG_RESVAL 0x0u
#define FLASH_MACRO_WRAPPER_CSR7_FIELD0_MASK 0xffu
#define FLASH_MACRO_WRAPPER_CSR7_FIELD0_OFFSET 0
#define FLASH_MACRO_WRAPPER_CSR7_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR7_FIELD0_MASK, .index = FLASH_MACRO_WRAPPER_CSR7_FIELD0_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR7_FIELD1_MASK 0x1ffu
#define FLASH_MACRO_WRAPPER_CSR7_FIELD1_OFFSET 8
#define FLASH_MACRO_WRAPPER_CSR7_FIELD1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR7_FIELD1_MASK, .index = FLASH_MACRO_WRAPPER_CSR7_FIELD1_OFFSET })
 
 
#define FLASH_MACRO_WRAPPER_CSR8_REG_OFFSET 0x20
#define FLASH_MACRO_WRAPPER_CSR8_REG_RESVAL 0x0u
 
 
#define FLASH_MACRO_WRAPPER_CSR9_REG_OFFSET 0x24
#define FLASH_MACRO_WRAPPER_CSR9_REG_RESVAL 0x0u
 
 
#define FLASH_MACRO_WRAPPER_CSR10_REG_OFFSET 0x28
#define FLASH_MACRO_WRAPPER_CSR10_REG_RESVAL 0x0u
 
 
#define FLASH_MACRO_WRAPPER_CSR11_REG_OFFSET 0x2c
#define FLASH_MACRO_WRAPPER_CSR11_REG_RESVAL 0x0u
 
 
#define FLASH_MACRO_WRAPPER_CSR12_REG_OFFSET 0x30
#define FLASH_MACRO_WRAPPER_CSR12_REG_RESVAL 0x0u
#define FLASH_MACRO_WRAPPER_CSR12_FIELD0_MASK 0x3ffu
#define FLASH_MACRO_WRAPPER_CSR12_FIELD0_OFFSET 0
#define FLASH_MACRO_WRAPPER_CSR12_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR12_FIELD0_MASK, .index = FLASH_MACRO_WRAPPER_CSR12_FIELD0_OFFSET })
 
 
#define FLASH_MACRO_WRAPPER_CSR13_REG_OFFSET 0x34
#define FLASH_MACRO_WRAPPER_CSR13_REG_RESVAL 0x0u
#define FLASH_MACRO_WRAPPER_CSR13_FIELD0_MASK 0xfffffu
#define FLASH_MACRO_WRAPPER_CSR13_FIELD0_OFFSET 0
#define FLASH_MACRO_WRAPPER_CSR13_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR13_FIELD0_MASK, .index = FLASH_MACRO_WRAPPER_CSR13_FIELD0_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR13_FIELD1_BIT 20
 
 
#define FLASH_MACRO_WRAPPER_CSR14_REG_OFFSET 0x38
#define FLASH_MACRO_WRAPPER_CSR14_REG_RESVAL 0x0u
#define FLASH_MACRO_WRAPPER_CSR14_FIELD0_MASK 0xffu
#define FLASH_MACRO_WRAPPER_CSR14_FIELD0_OFFSET 0
#define FLASH_MACRO_WRAPPER_CSR14_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR14_FIELD0_MASK, .index = FLASH_MACRO_WRAPPER_CSR14_FIELD0_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR14_FIELD1_BIT 8
 
 
#define FLASH_MACRO_WRAPPER_CSR15_REG_OFFSET 0x3c
#define FLASH_MACRO_WRAPPER_CSR15_REG_RESVAL 0x0u
#define FLASH_MACRO_WRAPPER_CSR15_FIELD0_MASK 0xffu
#define FLASH_MACRO_WRAPPER_CSR15_FIELD0_OFFSET 0
#define FLASH_MACRO_WRAPPER_CSR15_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR15_FIELD0_MASK, .index = FLASH_MACRO_WRAPPER_CSR15_FIELD0_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR15_FIELD1_BIT 8
 
 
#define FLASH_MACRO_WRAPPER_CSR16_REG_OFFSET 0x40
#define FLASH_MACRO_WRAPPER_CSR16_REG_RESVAL 0x0u
#define FLASH_MACRO_WRAPPER_CSR16_FIELD0_MASK 0xffu
#define FLASH_MACRO_WRAPPER_CSR16_FIELD0_OFFSET 0
#define FLASH_MACRO_WRAPPER_CSR16_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR16_FIELD0_MASK, .index = FLASH_MACRO_WRAPPER_CSR16_FIELD0_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR16_FIELD1_BIT 8
 
 
#define FLASH_MACRO_WRAPPER_CSR17_REG_OFFSET 0x44
#define FLASH_MACRO_WRAPPER_CSR17_REG_RESVAL 0x0u
#define FLASH_MACRO_WRAPPER_CSR17_FIELD0_MASK 0xffu
#define FLASH_MACRO_WRAPPER_CSR17_FIELD0_OFFSET 0
#define FLASH_MACRO_WRAPPER_CSR17_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_MACRO_WRAPPER_CSR17_FIELD0_MASK, .index = FLASH_MACRO_WRAPPER_CSR17_FIELD0_OFFSET })
#define FLASH_MACRO_WRAPPER_CSR17_FIELD1_BIT 8
 
 
#define FLASH_MACRO_WRAPPER_CSR18_REG_OFFSET 0x48
#define FLASH_MACRO_WRAPPER_CSR18_REG_RESVAL 0x0u
#define FLASH_MACRO_WRAPPER_CSR18_FIELD0_BIT 0
 
 
#define FLASH_MACRO_WRAPPER_CSR19_REG_OFFSET 0x4c
#define FLASH_MACRO_WRAPPER_CSR19_REG_RESVAL 0x0u
#define FLASH_MACRO_WRAPPER_CSR19_FIELD0_BIT 0
 
 
#define FLASH_MACRO_WRAPPER_CSR20_REG_OFFSET 0x50
#define FLASH_MACRO_WRAPPER_CSR20_REG_RESVAL 0x0u
#define FLASH_MACRO_WRAPPER_CSR20_FIELD0_BIT 0
#define FLASH_MACRO_WRAPPER_CSR20_FIELD1_BIT 1
#define FLASH_MACRO_WRAPPER_CSR20_FIELD2_BIT 2
 
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _FLASH_MACRO_WRAPPER_REG_DEFS_
// End generated register defines for flash_macro_wrapper