opentitanlib/otp/
alert_handler_regs.rs

1// Generated register constants for alert_handler
2
3// Copyright information found in source file:
4// Copyright lowRISC contributors (OpenTitan project).
5
6// Licensing information found in source file:
7// Licensed under the Apache License, Version 2.0, see LICENSE for details.
8// SPDX-License-Identifier: Apache-2.0
9
10// Number of alert channels.
11pub const ALERT_HANDLER_PARAM_N_ALERTS: u32 = 65;
12
13// Number of LPGs.
14pub const ALERT_HANDLER_PARAM_N_LPG: u32 = 24;
15
16// Width of LPG ID.
17pub const ALERT_HANDLER_PARAM_N_LPG_WIDTH: u32 = 5;
18
19// Width of the escalation timer.
20pub const ALERT_HANDLER_PARAM_ESC_CNT_DW: u32 = 32;
21
22// Width of the accumulation counter.
23pub const ALERT_HANDLER_PARAM_ACCU_CNT_DW: u32 = 16;
24
25// Number of classes
26pub const ALERT_HANDLER_PARAM_N_CLASSES: u32 = 4;
27
28// Number of escalation severities
29pub const ALERT_HANDLER_PARAM_N_ESC_SEV: u32 = 4;
30
31// Number of escalation phases
32pub const ALERT_HANDLER_PARAM_N_PHASES: u32 = 4;
33
34// Number of local alerts
35pub const ALERT_HANDLER_PARAM_N_LOC_ALERT: u32 = 7;
36
37// Width of ping counter
38pub const ALERT_HANDLER_PARAM_PING_CNT_DW: u32 = 16;
39
40// Width of phase ID
41pub const ALERT_HANDLER_PARAM_PHASE_DW: u32 = 2;
42
43// Width of class ID
44pub const ALERT_HANDLER_PARAM_CLASS_DW: u32 = 2;
45
46// Local alert ID for alert ping failure.
47pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ALERT_PINGFAIL: u32 = 0;
48
49// Local alert ID for escalation ping failure.
50pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ESC_PINGFAIL: u32 = 1;
51
52// Local alert ID for alert integrity failure.
53pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ALERT_INTEGFAIL: u32 = 2;
54
55// Local alert ID for escalation integrity failure.
56pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ESC_INTEGFAIL: u32 = 3;
57
58// Local alert ID for bus integrity failure.
59pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_BUS_INTEGFAIL: u32 = 4;
60
61// Local alert ID for shadow register update error.
62pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_SHADOW_REG_UPDATE_ERROR: u32 = 5;
63
64// Local alert ID for shadow register storage error.
65pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_SHADOW_REG_STORAGE_ERROR: u32 = 6;
66
67// Last local alert ID.
68pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_LAST: u32 = 6;
69
70// Register width
71pub const ALERT_HANDLER_PARAM_REG_WIDTH: u32 = 32;
72
73// Common Interrupt Offsets
74pub const ALERT_HANDLER_INTR_COMMON_CLASSA_BIT: u32 = 0;
75pub const ALERT_HANDLER_INTR_COMMON_CLASSB_BIT: u32 = 1;
76pub const ALERT_HANDLER_INTR_COMMON_CLASSC_BIT: u32 = 2;
77pub const ALERT_HANDLER_INTR_COMMON_CLASSD_BIT: u32 = 3;
78
79// Interrupt State Register
80pub const ALERT_HANDLER_INTR_STATE_REG_OFFSET: usize = 0x0;
81pub const ALERT_HANDLER_INTR_STATE_CLASSA_BIT: u32 = 0;
82pub const ALERT_HANDLER_INTR_STATE_CLASSB_BIT: u32 = 1;
83pub const ALERT_HANDLER_INTR_STATE_CLASSC_BIT: u32 = 2;
84pub const ALERT_HANDLER_INTR_STATE_CLASSD_BIT: u32 = 3;
85
86// Interrupt Enable Register
87pub const ALERT_HANDLER_INTR_ENABLE_REG_OFFSET: usize = 0x4;
88pub const ALERT_HANDLER_INTR_ENABLE_CLASSA_BIT: u32 = 0;
89pub const ALERT_HANDLER_INTR_ENABLE_CLASSB_BIT: u32 = 1;
90pub const ALERT_HANDLER_INTR_ENABLE_CLASSC_BIT: u32 = 2;
91pub const ALERT_HANDLER_INTR_ENABLE_CLASSD_BIT: u32 = 3;
92
93// Interrupt Test Register
94pub const ALERT_HANDLER_INTR_TEST_REG_OFFSET: usize = 0x8;
95pub const ALERT_HANDLER_INTR_TEST_CLASSA_BIT: u32 = 0;
96pub const ALERT_HANDLER_INTR_TEST_CLASSB_BIT: u32 = 1;
97pub const ALERT_HANDLER_INTR_TEST_CLASSC_BIT: u32 = 2;
98pub const ALERT_HANDLER_INTR_TEST_CLASSD_BIT: u32 = 3;
99
100// Register write enable for !!PING_TIMEOUT_CYC_SHADOWED and
101// !!PING_TIMER_EN_SHADOWED.
102pub const ALERT_HANDLER_PING_TIMER_REGWEN_REG_OFFSET: usize = 0xc;
103pub const ALERT_HANDLER_PING_TIMER_REGWEN_PING_TIMER_REGWEN_BIT: u32 = 0;
104
105// Ping timeout cycle count.
106pub const ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_REG_OFFSET: usize = 0x10;
107pub const ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_MASK: u32 = 0xffff;
108pub const ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_OFFSET: usize = 0;
109
110// Ping timer enable.
111pub const ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET: usize = 0x14;
112pub const ALERT_HANDLER_PING_TIMER_EN_SHADOWED_PING_TIMER_EN_SHADOWED_BIT: u32 = 0;
113
114// Register write enable for alert enable bits. (common parameters)
115pub const ALERT_HANDLER_ALERT_REGWEN_EN_FIELD_WIDTH: u32 = 1;
116pub const ALERT_HANDLER_ALERT_REGWEN_EN_FIELDS_PER_REG: u32 = 32;
117pub const ALERT_HANDLER_ALERT_REGWEN_MULTIREG_COUNT: u32 = 65;
118
119// Register write enable for alert enable bits.
120pub const ALERT_HANDLER_ALERT_REGWEN_0_REG_OFFSET: usize = 0x18;
121pub const ALERT_HANDLER_ALERT_REGWEN_0_EN_0_BIT: u32 = 0;
122
123// Register write enable for alert enable bits.
124pub const ALERT_HANDLER_ALERT_REGWEN_1_REG_OFFSET: usize = 0x1c;
125pub const ALERT_HANDLER_ALERT_REGWEN_1_EN_1_BIT: u32 = 0;
126
127// Register write enable for alert enable bits.
128pub const ALERT_HANDLER_ALERT_REGWEN_2_REG_OFFSET: usize = 0x20;
129pub const ALERT_HANDLER_ALERT_REGWEN_2_EN_2_BIT: u32 = 0;
130
131// Register write enable for alert enable bits.
132pub const ALERT_HANDLER_ALERT_REGWEN_3_REG_OFFSET: usize = 0x24;
133pub const ALERT_HANDLER_ALERT_REGWEN_3_EN_3_BIT: u32 = 0;
134
135// Register write enable for alert enable bits.
136pub const ALERT_HANDLER_ALERT_REGWEN_4_REG_OFFSET: usize = 0x28;
137pub const ALERT_HANDLER_ALERT_REGWEN_4_EN_4_BIT: u32 = 0;
138
139// Register write enable for alert enable bits.
140pub const ALERT_HANDLER_ALERT_REGWEN_5_REG_OFFSET: usize = 0x2c;
141pub const ALERT_HANDLER_ALERT_REGWEN_5_EN_5_BIT: u32 = 0;
142
143// Register write enable for alert enable bits.
144pub const ALERT_HANDLER_ALERT_REGWEN_6_REG_OFFSET: usize = 0x30;
145pub const ALERT_HANDLER_ALERT_REGWEN_6_EN_6_BIT: u32 = 0;
146
147// Register write enable for alert enable bits.
148pub const ALERT_HANDLER_ALERT_REGWEN_7_REG_OFFSET: usize = 0x34;
149pub const ALERT_HANDLER_ALERT_REGWEN_7_EN_7_BIT: u32 = 0;
150
151// Register write enable for alert enable bits.
152pub const ALERT_HANDLER_ALERT_REGWEN_8_REG_OFFSET: usize = 0x38;
153pub const ALERT_HANDLER_ALERT_REGWEN_8_EN_8_BIT: u32 = 0;
154
155// Register write enable for alert enable bits.
156pub const ALERT_HANDLER_ALERT_REGWEN_9_REG_OFFSET: usize = 0x3c;
157pub const ALERT_HANDLER_ALERT_REGWEN_9_EN_9_BIT: u32 = 0;
158
159// Register write enable for alert enable bits.
160pub const ALERT_HANDLER_ALERT_REGWEN_10_REG_OFFSET: usize = 0x40;
161pub const ALERT_HANDLER_ALERT_REGWEN_10_EN_10_BIT: u32 = 0;
162
163// Register write enable for alert enable bits.
164pub const ALERT_HANDLER_ALERT_REGWEN_11_REG_OFFSET: usize = 0x44;
165pub const ALERT_HANDLER_ALERT_REGWEN_11_EN_11_BIT: u32 = 0;
166
167// Register write enable for alert enable bits.
168pub const ALERT_HANDLER_ALERT_REGWEN_12_REG_OFFSET: usize = 0x48;
169pub const ALERT_HANDLER_ALERT_REGWEN_12_EN_12_BIT: u32 = 0;
170
171// Register write enable for alert enable bits.
172pub const ALERT_HANDLER_ALERT_REGWEN_13_REG_OFFSET: usize = 0x4c;
173pub const ALERT_HANDLER_ALERT_REGWEN_13_EN_13_BIT: u32 = 0;
174
175// Register write enable for alert enable bits.
176pub const ALERT_HANDLER_ALERT_REGWEN_14_REG_OFFSET: usize = 0x50;
177pub const ALERT_HANDLER_ALERT_REGWEN_14_EN_14_BIT: u32 = 0;
178
179// Register write enable for alert enable bits.
180pub const ALERT_HANDLER_ALERT_REGWEN_15_REG_OFFSET: usize = 0x54;
181pub const ALERT_HANDLER_ALERT_REGWEN_15_EN_15_BIT: u32 = 0;
182
183// Register write enable for alert enable bits.
184pub const ALERT_HANDLER_ALERT_REGWEN_16_REG_OFFSET: usize = 0x58;
185pub const ALERT_HANDLER_ALERT_REGWEN_16_EN_16_BIT: u32 = 0;
186
187// Register write enable for alert enable bits.
188pub const ALERT_HANDLER_ALERT_REGWEN_17_REG_OFFSET: usize = 0x5c;
189pub const ALERT_HANDLER_ALERT_REGWEN_17_EN_17_BIT: u32 = 0;
190
191// Register write enable for alert enable bits.
192pub const ALERT_HANDLER_ALERT_REGWEN_18_REG_OFFSET: usize = 0x60;
193pub const ALERT_HANDLER_ALERT_REGWEN_18_EN_18_BIT: u32 = 0;
194
195// Register write enable for alert enable bits.
196pub const ALERT_HANDLER_ALERT_REGWEN_19_REG_OFFSET: usize = 0x64;
197pub const ALERT_HANDLER_ALERT_REGWEN_19_EN_19_BIT: u32 = 0;
198
199// Register write enable for alert enable bits.
200pub const ALERT_HANDLER_ALERT_REGWEN_20_REG_OFFSET: usize = 0x68;
201pub const ALERT_HANDLER_ALERT_REGWEN_20_EN_20_BIT: u32 = 0;
202
203// Register write enable for alert enable bits.
204pub const ALERT_HANDLER_ALERT_REGWEN_21_REG_OFFSET: usize = 0x6c;
205pub const ALERT_HANDLER_ALERT_REGWEN_21_EN_21_BIT: u32 = 0;
206
207// Register write enable for alert enable bits.
208pub const ALERT_HANDLER_ALERT_REGWEN_22_REG_OFFSET: usize = 0x70;
209pub const ALERT_HANDLER_ALERT_REGWEN_22_EN_22_BIT: u32 = 0;
210
211// Register write enable for alert enable bits.
212pub const ALERT_HANDLER_ALERT_REGWEN_23_REG_OFFSET: usize = 0x74;
213pub const ALERT_HANDLER_ALERT_REGWEN_23_EN_23_BIT: u32 = 0;
214
215// Register write enable for alert enable bits.
216pub const ALERT_HANDLER_ALERT_REGWEN_24_REG_OFFSET: usize = 0x78;
217pub const ALERT_HANDLER_ALERT_REGWEN_24_EN_24_BIT: u32 = 0;
218
219// Register write enable for alert enable bits.
220pub const ALERT_HANDLER_ALERT_REGWEN_25_REG_OFFSET: usize = 0x7c;
221pub const ALERT_HANDLER_ALERT_REGWEN_25_EN_25_BIT: u32 = 0;
222
223// Register write enable for alert enable bits.
224pub const ALERT_HANDLER_ALERT_REGWEN_26_REG_OFFSET: usize = 0x80;
225pub const ALERT_HANDLER_ALERT_REGWEN_26_EN_26_BIT: u32 = 0;
226
227// Register write enable for alert enable bits.
228pub const ALERT_HANDLER_ALERT_REGWEN_27_REG_OFFSET: usize = 0x84;
229pub const ALERT_HANDLER_ALERT_REGWEN_27_EN_27_BIT: u32 = 0;
230
231// Register write enable for alert enable bits.
232pub const ALERT_HANDLER_ALERT_REGWEN_28_REG_OFFSET: usize = 0x88;
233pub const ALERT_HANDLER_ALERT_REGWEN_28_EN_28_BIT: u32 = 0;
234
235// Register write enable for alert enable bits.
236pub const ALERT_HANDLER_ALERT_REGWEN_29_REG_OFFSET: usize = 0x8c;
237pub const ALERT_HANDLER_ALERT_REGWEN_29_EN_29_BIT: u32 = 0;
238
239// Register write enable for alert enable bits.
240pub const ALERT_HANDLER_ALERT_REGWEN_30_REG_OFFSET: usize = 0x90;
241pub const ALERT_HANDLER_ALERT_REGWEN_30_EN_30_BIT: u32 = 0;
242
243// Register write enable for alert enable bits.
244pub const ALERT_HANDLER_ALERT_REGWEN_31_REG_OFFSET: usize = 0x94;
245pub const ALERT_HANDLER_ALERT_REGWEN_31_EN_31_BIT: u32 = 0;
246
247// Register write enable for alert enable bits.
248pub const ALERT_HANDLER_ALERT_REGWEN_32_REG_OFFSET: usize = 0x98;
249pub const ALERT_HANDLER_ALERT_REGWEN_32_EN_32_BIT: u32 = 0;
250
251// Register write enable for alert enable bits.
252pub const ALERT_HANDLER_ALERT_REGWEN_33_REG_OFFSET: usize = 0x9c;
253pub const ALERT_HANDLER_ALERT_REGWEN_33_EN_33_BIT: u32 = 0;
254
255// Register write enable for alert enable bits.
256pub const ALERT_HANDLER_ALERT_REGWEN_34_REG_OFFSET: usize = 0xa0;
257pub const ALERT_HANDLER_ALERT_REGWEN_34_EN_34_BIT: u32 = 0;
258
259// Register write enable for alert enable bits.
260pub const ALERT_HANDLER_ALERT_REGWEN_35_REG_OFFSET: usize = 0xa4;
261pub const ALERT_HANDLER_ALERT_REGWEN_35_EN_35_BIT: u32 = 0;
262
263// Register write enable for alert enable bits.
264pub const ALERT_HANDLER_ALERT_REGWEN_36_REG_OFFSET: usize = 0xa8;
265pub const ALERT_HANDLER_ALERT_REGWEN_36_EN_36_BIT: u32 = 0;
266
267// Register write enable for alert enable bits.
268pub const ALERT_HANDLER_ALERT_REGWEN_37_REG_OFFSET: usize = 0xac;
269pub const ALERT_HANDLER_ALERT_REGWEN_37_EN_37_BIT: u32 = 0;
270
271// Register write enable for alert enable bits.
272pub const ALERT_HANDLER_ALERT_REGWEN_38_REG_OFFSET: usize = 0xb0;
273pub const ALERT_HANDLER_ALERT_REGWEN_38_EN_38_BIT: u32 = 0;
274
275// Register write enable for alert enable bits.
276pub const ALERT_HANDLER_ALERT_REGWEN_39_REG_OFFSET: usize = 0xb4;
277pub const ALERT_HANDLER_ALERT_REGWEN_39_EN_39_BIT: u32 = 0;
278
279// Register write enable for alert enable bits.
280pub const ALERT_HANDLER_ALERT_REGWEN_40_REG_OFFSET: usize = 0xb8;
281pub const ALERT_HANDLER_ALERT_REGWEN_40_EN_40_BIT: u32 = 0;
282
283// Register write enable for alert enable bits.
284pub const ALERT_HANDLER_ALERT_REGWEN_41_REG_OFFSET: usize = 0xbc;
285pub const ALERT_HANDLER_ALERT_REGWEN_41_EN_41_BIT: u32 = 0;
286
287// Register write enable for alert enable bits.
288pub const ALERT_HANDLER_ALERT_REGWEN_42_REG_OFFSET: usize = 0xc0;
289pub const ALERT_HANDLER_ALERT_REGWEN_42_EN_42_BIT: u32 = 0;
290
291// Register write enable for alert enable bits.
292pub const ALERT_HANDLER_ALERT_REGWEN_43_REG_OFFSET: usize = 0xc4;
293pub const ALERT_HANDLER_ALERT_REGWEN_43_EN_43_BIT: u32 = 0;
294
295// Register write enable for alert enable bits.
296pub const ALERT_HANDLER_ALERT_REGWEN_44_REG_OFFSET: usize = 0xc8;
297pub const ALERT_HANDLER_ALERT_REGWEN_44_EN_44_BIT: u32 = 0;
298
299// Register write enable for alert enable bits.
300pub const ALERT_HANDLER_ALERT_REGWEN_45_REG_OFFSET: usize = 0xcc;
301pub const ALERT_HANDLER_ALERT_REGWEN_45_EN_45_BIT: u32 = 0;
302
303// Register write enable for alert enable bits.
304pub const ALERT_HANDLER_ALERT_REGWEN_46_REG_OFFSET: usize = 0xd0;
305pub const ALERT_HANDLER_ALERT_REGWEN_46_EN_46_BIT: u32 = 0;
306
307// Register write enable for alert enable bits.
308pub const ALERT_HANDLER_ALERT_REGWEN_47_REG_OFFSET: usize = 0xd4;
309pub const ALERT_HANDLER_ALERT_REGWEN_47_EN_47_BIT: u32 = 0;
310
311// Register write enable for alert enable bits.
312pub const ALERT_HANDLER_ALERT_REGWEN_48_REG_OFFSET: usize = 0xd8;
313pub const ALERT_HANDLER_ALERT_REGWEN_48_EN_48_BIT: u32 = 0;
314
315// Register write enable for alert enable bits.
316pub const ALERT_HANDLER_ALERT_REGWEN_49_REG_OFFSET: usize = 0xdc;
317pub const ALERT_HANDLER_ALERT_REGWEN_49_EN_49_BIT: u32 = 0;
318
319// Register write enable for alert enable bits.
320pub const ALERT_HANDLER_ALERT_REGWEN_50_REG_OFFSET: usize = 0xe0;
321pub const ALERT_HANDLER_ALERT_REGWEN_50_EN_50_BIT: u32 = 0;
322
323// Register write enable for alert enable bits.
324pub const ALERT_HANDLER_ALERT_REGWEN_51_REG_OFFSET: usize = 0xe4;
325pub const ALERT_HANDLER_ALERT_REGWEN_51_EN_51_BIT: u32 = 0;
326
327// Register write enable for alert enable bits.
328pub const ALERT_HANDLER_ALERT_REGWEN_52_REG_OFFSET: usize = 0xe8;
329pub const ALERT_HANDLER_ALERT_REGWEN_52_EN_52_BIT: u32 = 0;
330
331// Register write enable for alert enable bits.
332pub const ALERT_HANDLER_ALERT_REGWEN_53_REG_OFFSET: usize = 0xec;
333pub const ALERT_HANDLER_ALERT_REGWEN_53_EN_53_BIT: u32 = 0;
334
335// Register write enable for alert enable bits.
336pub const ALERT_HANDLER_ALERT_REGWEN_54_REG_OFFSET: usize = 0xf0;
337pub const ALERT_HANDLER_ALERT_REGWEN_54_EN_54_BIT: u32 = 0;
338
339// Register write enable for alert enable bits.
340pub const ALERT_HANDLER_ALERT_REGWEN_55_REG_OFFSET: usize = 0xf4;
341pub const ALERT_HANDLER_ALERT_REGWEN_55_EN_55_BIT: u32 = 0;
342
343// Register write enable for alert enable bits.
344pub const ALERT_HANDLER_ALERT_REGWEN_56_REG_OFFSET: usize = 0xf8;
345pub const ALERT_HANDLER_ALERT_REGWEN_56_EN_56_BIT: u32 = 0;
346
347// Register write enable for alert enable bits.
348pub const ALERT_HANDLER_ALERT_REGWEN_57_REG_OFFSET: usize = 0xfc;
349pub const ALERT_HANDLER_ALERT_REGWEN_57_EN_57_BIT: u32 = 0;
350
351// Register write enable for alert enable bits.
352pub const ALERT_HANDLER_ALERT_REGWEN_58_REG_OFFSET: usize = 0x100;
353pub const ALERT_HANDLER_ALERT_REGWEN_58_EN_58_BIT: u32 = 0;
354
355// Register write enable for alert enable bits.
356pub const ALERT_HANDLER_ALERT_REGWEN_59_REG_OFFSET: usize = 0x104;
357pub const ALERT_HANDLER_ALERT_REGWEN_59_EN_59_BIT: u32 = 0;
358
359// Register write enable for alert enable bits.
360pub const ALERT_HANDLER_ALERT_REGWEN_60_REG_OFFSET: usize = 0x108;
361pub const ALERT_HANDLER_ALERT_REGWEN_60_EN_60_BIT: u32 = 0;
362
363// Register write enable for alert enable bits.
364pub const ALERT_HANDLER_ALERT_REGWEN_61_REG_OFFSET: usize = 0x10c;
365pub const ALERT_HANDLER_ALERT_REGWEN_61_EN_61_BIT: u32 = 0;
366
367// Register write enable for alert enable bits.
368pub const ALERT_HANDLER_ALERT_REGWEN_62_REG_OFFSET: usize = 0x110;
369pub const ALERT_HANDLER_ALERT_REGWEN_62_EN_62_BIT: u32 = 0;
370
371// Register write enable for alert enable bits.
372pub const ALERT_HANDLER_ALERT_REGWEN_63_REG_OFFSET: usize = 0x114;
373pub const ALERT_HANDLER_ALERT_REGWEN_63_EN_63_BIT: u32 = 0;
374
375// Register write enable for alert enable bits.
376pub const ALERT_HANDLER_ALERT_REGWEN_64_REG_OFFSET: usize = 0x118;
377pub const ALERT_HANDLER_ALERT_REGWEN_64_EN_64_BIT: u32 = 0;
378
379// Enable register for alerts. (common parameters)
380pub const ALERT_HANDLER_ALERT_EN_SHADOWED_EN_A_FIELD_WIDTH: u32 = 1;
381pub const ALERT_HANDLER_ALERT_EN_SHADOWED_EN_A_FIELDS_PER_REG: u32 = 32;
382pub const ALERT_HANDLER_ALERT_EN_SHADOWED_MULTIREG_COUNT: u32 = 65;
383
384// Enable register for alerts.
385pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET: usize = 0x11c;
386pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_EN_A_0_BIT: u32 = 0;
387
388// Enable register for alerts.
389pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_OFFSET: usize = 0x120;
390pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_EN_A_1_BIT: u32 = 0;
391
392// Enable register for alerts.
393pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_OFFSET: usize = 0x124;
394pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_EN_A_2_BIT: u32 = 0;
395
396// Enable register for alerts.
397pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_OFFSET: usize = 0x128;
398pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_EN_A_3_BIT: u32 = 0;
399
400// Enable register for alerts.
401pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_OFFSET: usize = 0x12c;
402pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_EN_A_4_BIT: u32 = 0;
403
404// Enable register for alerts.
405pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_OFFSET: usize = 0x130;
406pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_EN_A_5_BIT: u32 = 0;
407
408// Enable register for alerts.
409pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_OFFSET: usize = 0x134;
410pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_EN_A_6_BIT: u32 = 0;
411
412// Enable register for alerts.
413pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_OFFSET: usize = 0x138;
414pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_EN_A_7_BIT: u32 = 0;
415
416// Enable register for alerts.
417pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_OFFSET: usize = 0x13c;
418pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_EN_A_8_BIT: u32 = 0;
419
420// Enable register for alerts.
421pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_OFFSET: usize = 0x140;
422pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_EN_A_9_BIT: u32 = 0;
423
424// Enable register for alerts.
425pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_OFFSET: usize = 0x144;
426pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_EN_A_10_BIT: u32 = 0;
427
428// Enable register for alerts.
429pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_OFFSET: usize = 0x148;
430pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_EN_A_11_BIT: u32 = 0;
431
432// Enable register for alerts.
433pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_OFFSET: usize = 0x14c;
434pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_EN_A_12_BIT: u32 = 0;
435
436// Enable register for alerts.
437pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_OFFSET: usize = 0x150;
438pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_EN_A_13_BIT: u32 = 0;
439
440// Enable register for alerts.
441pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_OFFSET: usize = 0x154;
442pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_EN_A_14_BIT: u32 = 0;
443
444// Enable register for alerts.
445pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_OFFSET: usize = 0x158;
446pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_EN_A_15_BIT: u32 = 0;
447
448// Enable register for alerts.
449pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_OFFSET: usize = 0x15c;
450pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_EN_A_16_BIT: u32 = 0;
451
452// Enable register for alerts.
453pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_OFFSET: usize = 0x160;
454pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_EN_A_17_BIT: u32 = 0;
455
456// Enable register for alerts.
457pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_OFFSET: usize = 0x164;
458pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_EN_A_18_BIT: u32 = 0;
459
460// Enable register for alerts.
461pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_OFFSET: usize = 0x168;
462pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_EN_A_19_BIT: u32 = 0;
463
464// Enable register for alerts.
465pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_OFFSET: usize = 0x16c;
466pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_EN_A_20_BIT: u32 = 0;
467
468// Enable register for alerts.
469pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_OFFSET: usize = 0x170;
470pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_EN_A_21_BIT: u32 = 0;
471
472// Enable register for alerts.
473pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_OFFSET: usize = 0x174;
474pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_EN_A_22_BIT: u32 = 0;
475
476// Enable register for alerts.
477pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_OFFSET: usize = 0x178;
478pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_EN_A_23_BIT: u32 = 0;
479
480// Enable register for alerts.
481pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_OFFSET: usize = 0x17c;
482pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_EN_A_24_BIT: u32 = 0;
483
484// Enable register for alerts.
485pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_OFFSET: usize = 0x180;
486pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_EN_A_25_BIT: u32 = 0;
487
488// Enable register for alerts.
489pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_OFFSET: usize = 0x184;
490pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_EN_A_26_BIT: u32 = 0;
491
492// Enable register for alerts.
493pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_OFFSET: usize = 0x188;
494pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_EN_A_27_BIT: u32 = 0;
495
496// Enable register for alerts.
497pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_OFFSET: usize = 0x18c;
498pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_EN_A_28_BIT: u32 = 0;
499
500// Enable register for alerts.
501pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_OFFSET: usize = 0x190;
502pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_EN_A_29_BIT: u32 = 0;
503
504// Enable register for alerts.
505pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_OFFSET: usize = 0x194;
506pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_EN_A_30_BIT: u32 = 0;
507
508// Enable register for alerts.
509pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_OFFSET: usize = 0x198;
510pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_EN_A_31_BIT: u32 = 0;
511
512// Enable register for alerts.
513pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_OFFSET: usize = 0x19c;
514pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_EN_A_32_BIT: u32 = 0;
515
516// Enable register for alerts.
517pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_OFFSET: usize = 0x1a0;
518pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_EN_A_33_BIT: u32 = 0;
519
520// Enable register for alerts.
521pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_OFFSET: usize = 0x1a4;
522pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_EN_A_34_BIT: u32 = 0;
523
524// Enable register for alerts.
525pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_OFFSET: usize = 0x1a8;
526pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_EN_A_35_BIT: u32 = 0;
527
528// Enable register for alerts.
529pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_OFFSET: usize = 0x1ac;
530pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_EN_A_36_BIT: u32 = 0;
531
532// Enable register for alerts.
533pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_OFFSET: usize = 0x1b0;
534pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_EN_A_37_BIT: u32 = 0;
535
536// Enable register for alerts.
537pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_OFFSET: usize = 0x1b4;
538pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_EN_A_38_BIT: u32 = 0;
539
540// Enable register for alerts.
541pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_OFFSET: usize = 0x1b8;
542pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_EN_A_39_BIT: u32 = 0;
543
544// Enable register for alerts.
545pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_OFFSET: usize = 0x1bc;
546pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_EN_A_40_BIT: u32 = 0;
547
548// Enable register for alerts.
549pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_OFFSET: usize = 0x1c0;
550pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_EN_A_41_BIT: u32 = 0;
551
552// Enable register for alerts.
553pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_OFFSET: usize = 0x1c4;
554pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_EN_A_42_BIT: u32 = 0;
555
556// Enable register for alerts.
557pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_OFFSET: usize = 0x1c8;
558pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_EN_A_43_BIT: u32 = 0;
559
560// Enable register for alerts.
561pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_OFFSET: usize = 0x1cc;
562pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_EN_A_44_BIT: u32 = 0;
563
564// Enable register for alerts.
565pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_OFFSET: usize = 0x1d0;
566pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_EN_A_45_BIT: u32 = 0;
567
568// Enable register for alerts.
569pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_OFFSET: usize = 0x1d4;
570pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_EN_A_46_BIT: u32 = 0;
571
572// Enable register for alerts.
573pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_OFFSET: usize = 0x1d8;
574pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_EN_A_47_BIT: u32 = 0;
575
576// Enable register for alerts.
577pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_OFFSET: usize = 0x1dc;
578pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_EN_A_48_BIT: u32 = 0;
579
580// Enable register for alerts.
581pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_OFFSET: usize = 0x1e0;
582pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_EN_A_49_BIT: u32 = 0;
583
584// Enable register for alerts.
585pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_OFFSET: usize = 0x1e4;
586pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_EN_A_50_BIT: u32 = 0;
587
588// Enable register for alerts.
589pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_OFFSET: usize = 0x1e8;
590pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_EN_A_51_BIT: u32 = 0;
591
592// Enable register for alerts.
593pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_OFFSET: usize = 0x1ec;
594pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_EN_A_52_BIT: u32 = 0;
595
596// Enable register for alerts.
597pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_OFFSET: usize = 0x1f0;
598pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_EN_A_53_BIT: u32 = 0;
599
600// Enable register for alerts.
601pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_OFFSET: usize = 0x1f4;
602pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_EN_A_54_BIT: u32 = 0;
603
604// Enable register for alerts.
605pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_OFFSET: usize = 0x1f8;
606pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_EN_A_55_BIT: u32 = 0;
607
608// Enable register for alerts.
609pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_OFFSET: usize = 0x1fc;
610pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_EN_A_56_BIT: u32 = 0;
611
612// Enable register for alerts.
613pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_OFFSET: usize = 0x200;
614pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_EN_A_57_BIT: u32 = 0;
615
616// Enable register for alerts.
617pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_OFFSET: usize = 0x204;
618pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_EN_A_58_BIT: u32 = 0;
619
620// Enable register for alerts.
621pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_OFFSET: usize = 0x208;
622pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_EN_A_59_BIT: u32 = 0;
623
624// Enable register for alerts.
625pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_OFFSET: usize = 0x20c;
626pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_EN_A_60_BIT: u32 = 0;
627
628// Enable register for alerts.
629pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_OFFSET: usize = 0x210;
630pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_EN_A_61_BIT: u32 = 0;
631
632// Enable register for alerts.
633pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_OFFSET: usize = 0x214;
634pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_EN_A_62_BIT: u32 = 0;
635
636// Enable register for alerts.
637pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_OFFSET: usize = 0x218;
638pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_EN_A_63_BIT: u32 = 0;
639
640// Enable register for alerts.
641pub const ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_OFFSET: usize = 0x21c;
642pub const ALERT_HANDLER_ALERT_EN_SHADOWED_64_EN_A_64_BIT: u32 = 0;
643
644// Class assignment of alerts. (common parameters)
645pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_CLASS_A_FIELD_WIDTH: u32 = 2;
646pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_CLASS_A_FIELDS_PER_REG: u32 = 16;
647pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT: u32 = 65;
648
649// Class assignment of alerts.
650pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET: usize = 0x220;
651pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_MASK: u32 = 0x3;
652pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_OFFSET: usize = 0;
653pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSA: u32 = 0x0;
654pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSB: u32 = 0x1;
655pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSC: u32 = 0x2;
656pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSD: u32 = 0x3;
657
658// Class assignment of alerts.
659pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_OFFSET: usize = 0x224;
660pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_MASK: u32 = 0x3;
661pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_OFFSET: usize = 0;
662
663// Class assignment of alerts.
664pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_OFFSET: usize = 0x228;
665pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_MASK: u32 = 0x3;
666pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_OFFSET: usize = 0;
667
668// Class assignment of alerts.
669pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_OFFSET: usize = 0x22c;
670pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_MASK: u32 = 0x3;
671pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_OFFSET: usize = 0;
672
673// Class assignment of alerts.
674pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_OFFSET: usize = 0x230;
675pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_MASK: u32 = 0x3;
676pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_OFFSET: usize = 0;
677
678// Class assignment of alerts.
679pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_OFFSET: usize = 0x234;
680pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_MASK: u32 = 0x3;
681pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_OFFSET: usize = 0;
682
683// Class assignment of alerts.
684pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_OFFSET: usize = 0x238;
685pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_MASK: u32 = 0x3;
686pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_OFFSET: usize = 0;
687
688// Class assignment of alerts.
689pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_OFFSET: usize = 0x23c;
690pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_MASK: u32 = 0x3;
691pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_OFFSET: usize = 0;
692
693// Class assignment of alerts.
694pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_OFFSET: usize = 0x240;
695pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_MASK: u32 = 0x3;
696pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_OFFSET: usize = 0;
697
698// Class assignment of alerts.
699pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_OFFSET: usize = 0x244;
700pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_MASK: u32 = 0x3;
701pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_OFFSET: usize = 0;
702
703// Class assignment of alerts.
704pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_OFFSET: usize = 0x248;
705pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_MASK: u32 = 0x3;
706pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_OFFSET: usize = 0;
707
708// Class assignment of alerts.
709pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_OFFSET: usize = 0x24c;
710pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_MASK: u32 = 0x3;
711pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_OFFSET: usize = 0;
712
713// Class assignment of alerts.
714pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_OFFSET: usize = 0x250;
715pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_MASK: u32 = 0x3;
716pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_OFFSET: usize = 0;
717
718// Class assignment of alerts.
719pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_OFFSET: usize = 0x254;
720pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_MASK: u32 = 0x3;
721pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_OFFSET: usize = 0;
722
723// Class assignment of alerts.
724pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_OFFSET: usize = 0x258;
725pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_MASK: u32 = 0x3;
726pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_OFFSET: usize = 0;
727
728// Class assignment of alerts.
729pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_OFFSET: usize = 0x25c;
730pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_MASK: u32 = 0x3;
731pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_OFFSET: usize = 0;
732
733// Class assignment of alerts.
734pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_OFFSET: usize = 0x260;
735pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_MASK: u32 = 0x3;
736pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_OFFSET: usize = 0;
737
738// Class assignment of alerts.
739pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_OFFSET: usize = 0x264;
740pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_MASK: u32 = 0x3;
741pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_OFFSET: usize = 0;
742
743// Class assignment of alerts.
744pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_OFFSET: usize = 0x268;
745pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_MASK: u32 = 0x3;
746pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_OFFSET: usize = 0;
747
748// Class assignment of alerts.
749pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_OFFSET: usize = 0x26c;
750pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_MASK: u32 = 0x3;
751pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_OFFSET: usize = 0;
752
753// Class assignment of alerts.
754pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_OFFSET: usize = 0x270;
755pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_MASK: u32 = 0x3;
756pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_OFFSET: usize = 0;
757
758// Class assignment of alerts.
759pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_OFFSET: usize = 0x274;
760pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_MASK: u32 = 0x3;
761pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_OFFSET: usize = 0;
762
763// Class assignment of alerts.
764pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_OFFSET: usize = 0x278;
765pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_MASK: u32 = 0x3;
766pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_OFFSET: usize = 0;
767
768// Class assignment of alerts.
769pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_OFFSET: usize = 0x27c;
770pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_MASK: u32 = 0x3;
771pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_OFFSET: usize = 0;
772
773// Class assignment of alerts.
774pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_OFFSET: usize = 0x280;
775pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_MASK: u32 = 0x3;
776pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_OFFSET: usize = 0;
777
778// Class assignment of alerts.
779pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_OFFSET: usize = 0x284;
780pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_MASK: u32 = 0x3;
781pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_OFFSET: usize = 0;
782
783// Class assignment of alerts.
784pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_OFFSET: usize = 0x288;
785pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_MASK: u32 = 0x3;
786pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_OFFSET: usize = 0;
787
788// Class assignment of alerts.
789pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_OFFSET: usize = 0x28c;
790pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_MASK: u32 = 0x3;
791pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_OFFSET: usize = 0;
792
793// Class assignment of alerts.
794pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_OFFSET: usize = 0x290;
795pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_MASK: u32 = 0x3;
796pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_OFFSET: usize = 0;
797
798// Class assignment of alerts.
799pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_OFFSET: usize = 0x294;
800pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_MASK: u32 = 0x3;
801pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_OFFSET: usize = 0;
802
803// Class assignment of alerts.
804pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_OFFSET: usize = 0x298;
805pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_MASK: u32 = 0x3;
806pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_OFFSET: usize = 0;
807
808// Class assignment of alerts.
809pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_OFFSET: usize = 0x29c;
810pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_MASK: u32 = 0x3;
811pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_OFFSET: usize = 0;
812
813// Class assignment of alerts.
814pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_OFFSET: usize = 0x2a0;
815pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_MASK: u32 = 0x3;
816pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_OFFSET: usize = 0;
817
818// Class assignment of alerts.
819pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_OFFSET: usize = 0x2a4;
820pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_MASK: u32 = 0x3;
821pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_OFFSET: usize = 0;
822
823// Class assignment of alerts.
824pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_OFFSET: usize = 0x2a8;
825pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_MASK: u32 = 0x3;
826pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_OFFSET: usize = 0;
827
828// Class assignment of alerts.
829pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_OFFSET: usize = 0x2ac;
830pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_MASK: u32 = 0x3;
831pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_OFFSET: usize = 0;
832
833// Class assignment of alerts.
834pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_OFFSET: usize = 0x2b0;
835pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_MASK: u32 = 0x3;
836pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_OFFSET: usize = 0;
837
838// Class assignment of alerts.
839pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_OFFSET: usize = 0x2b4;
840pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_MASK: u32 = 0x3;
841pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_OFFSET: usize = 0;
842
843// Class assignment of alerts.
844pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_OFFSET: usize = 0x2b8;
845pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_MASK: u32 = 0x3;
846pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_OFFSET: usize = 0;
847
848// Class assignment of alerts.
849pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_OFFSET: usize = 0x2bc;
850pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_MASK: u32 = 0x3;
851pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_OFFSET: usize = 0;
852
853// Class assignment of alerts.
854pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_OFFSET: usize = 0x2c0;
855pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_MASK: u32 = 0x3;
856pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_OFFSET: usize = 0;
857
858// Class assignment of alerts.
859pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_OFFSET: usize = 0x2c4;
860pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_MASK: u32 = 0x3;
861pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_OFFSET: usize = 0;
862
863// Class assignment of alerts.
864pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_OFFSET: usize = 0x2c8;
865pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_MASK: u32 = 0x3;
866pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_OFFSET: usize = 0;
867
868// Class assignment of alerts.
869pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_OFFSET: usize = 0x2cc;
870pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_MASK: u32 = 0x3;
871pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_OFFSET: usize = 0;
872
873// Class assignment of alerts.
874pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_OFFSET: usize = 0x2d0;
875pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_MASK: u32 = 0x3;
876pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_OFFSET: usize = 0;
877
878// Class assignment of alerts.
879pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_OFFSET: usize = 0x2d4;
880pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_MASK: u32 = 0x3;
881pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_OFFSET: usize = 0;
882
883// Class assignment of alerts.
884pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_OFFSET: usize = 0x2d8;
885pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_MASK: u32 = 0x3;
886pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_OFFSET: usize = 0;
887
888// Class assignment of alerts.
889pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_OFFSET: usize = 0x2dc;
890pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_MASK: u32 = 0x3;
891pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_OFFSET: usize = 0;
892
893// Class assignment of alerts.
894pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_OFFSET: usize = 0x2e0;
895pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_MASK: u32 = 0x3;
896pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_OFFSET: usize = 0;
897
898// Class assignment of alerts.
899pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_OFFSET: usize = 0x2e4;
900pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_MASK: u32 = 0x3;
901pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_OFFSET: usize = 0;
902
903// Class assignment of alerts.
904pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_OFFSET: usize = 0x2e8;
905pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_MASK: u32 = 0x3;
906pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_OFFSET: usize = 0;
907
908// Class assignment of alerts.
909pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_OFFSET: usize = 0x2ec;
910pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_MASK: u32 = 0x3;
911pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_OFFSET: usize = 0;
912
913// Class assignment of alerts.
914pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_OFFSET: usize = 0x2f0;
915pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_MASK: u32 = 0x3;
916pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_OFFSET: usize = 0;
917
918// Class assignment of alerts.
919pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_OFFSET: usize = 0x2f4;
920pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_MASK: u32 = 0x3;
921pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_OFFSET: usize = 0;
922
923// Class assignment of alerts.
924pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_OFFSET: usize = 0x2f8;
925pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_MASK: u32 = 0x3;
926pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_OFFSET: usize = 0;
927
928// Class assignment of alerts.
929pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_OFFSET: usize = 0x2fc;
930pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_MASK: u32 = 0x3;
931pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_OFFSET: usize = 0;
932
933// Class assignment of alerts.
934pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_OFFSET: usize = 0x300;
935pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_MASK: u32 = 0x3;
936pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_OFFSET: usize = 0;
937
938// Class assignment of alerts.
939pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_OFFSET: usize = 0x304;
940pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_MASK: u32 = 0x3;
941pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_OFFSET: usize = 0;
942
943// Class assignment of alerts.
944pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_OFFSET: usize = 0x308;
945pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_MASK: u32 = 0x3;
946pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_OFFSET: usize = 0;
947
948// Class assignment of alerts.
949pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_OFFSET: usize = 0x30c;
950pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_MASK: u32 = 0x3;
951pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_OFFSET: usize = 0;
952
953// Class assignment of alerts.
954pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_OFFSET: usize = 0x310;
955pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_MASK: u32 = 0x3;
956pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_OFFSET: usize = 0;
957
958// Class assignment of alerts.
959pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_OFFSET: usize = 0x314;
960pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_MASK: u32 = 0x3;
961pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_OFFSET: usize = 0;
962
963// Class assignment of alerts.
964pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_OFFSET: usize = 0x318;
965pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_MASK: u32 = 0x3;
966pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_OFFSET: usize = 0;
967
968// Class assignment of alerts.
969pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_OFFSET: usize = 0x31c;
970pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_MASK: u32 = 0x3;
971pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_OFFSET: usize = 0;
972
973// Class assignment of alerts.
974pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_OFFSET: usize = 0x320;
975pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_MASK: u32 = 0x3;
976pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_OFFSET: usize = 0;
977
978// Alert Cause Register (common parameters)
979pub const ALERT_HANDLER_ALERT_CAUSE_A_FIELD_WIDTH: u32 = 1;
980pub const ALERT_HANDLER_ALERT_CAUSE_A_FIELDS_PER_REG: u32 = 32;
981pub const ALERT_HANDLER_ALERT_CAUSE_MULTIREG_COUNT: u32 = 65;
982
983// Alert Cause Register
984pub const ALERT_HANDLER_ALERT_CAUSE_0_REG_OFFSET: usize = 0x324;
985pub const ALERT_HANDLER_ALERT_CAUSE_0_A_0_BIT: u32 = 0;
986
987// Alert Cause Register
988pub const ALERT_HANDLER_ALERT_CAUSE_1_REG_OFFSET: usize = 0x328;
989pub const ALERT_HANDLER_ALERT_CAUSE_1_A_1_BIT: u32 = 0;
990
991// Alert Cause Register
992pub const ALERT_HANDLER_ALERT_CAUSE_2_REG_OFFSET: usize = 0x32c;
993pub const ALERT_HANDLER_ALERT_CAUSE_2_A_2_BIT: u32 = 0;
994
995// Alert Cause Register
996pub const ALERT_HANDLER_ALERT_CAUSE_3_REG_OFFSET: usize = 0x330;
997pub const ALERT_HANDLER_ALERT_CAUSE_3_A_3_BIT: u32 = 0;
998
999// Alert Cause Register
1000pub const ALERT_HANDLER_ALERT_CAUSE_4_REG_OFFSET: usize = 0x334;
1001pub const ALERT_HANDLER_ALERT_CAUSE_4_A_4_BIT: u32 = 0;
1002
1003// Alert Cause Register
1004pub const ALERT_HANDLER_ALERT_CAUSE_5_REG_OFFSET: usize = 0x338;
1005pub const ALERT_HANDLER_ALERT_CAUSE_5_A_5_BIT: u32 = 0;
1006
1007// Alert Cause Register
1008pub const ALERT_HANDLER_ALERT_CAUSE_6_REG_OFFSET: usize = 0x33c;
1009pub const ALERT_HANDLER_ALERT_CAUSE_6_A_6_BIT: u32 = 0;
1010
1011// Alert Cause Register
1012pub const ALERT_HANDLER_ALERT_CAUSE_7_REG_OFFSET: usize = 0x340;
1013pub const ALERT_HANDLER_ALERT_CAUSE_7_A_7_BIT: u32 = 0;
1014
1015// Alert Cause Register
1016pub const ALERT_HANDLER_ALERT_CAUSE_8_REG_OFFSET: usize = 0x344;
1017pub const ALERT_HANDLER_ALERT_CAUSE_8_A_8_BIT: u32 = 0;
1018
1019// Alert Cause Register
1020pub const ALERT_HANDLER_ALERT_CAUSE_9_REG_OFFSET: usize = 0x348;
1021pub const ALERT_HANDLER_ALERT_CAUSE_9_A_9_BIT: u32 = 0;
1022
1023// Alert Cause Register
1024pub const ALERT_HANDLER_ALERT_CAUSE_10_REG_OFFSET: usize = 0x34c;
1025pub const ALERT_HANDLER_ALERT_CAUSE_10_A_10_BIT: u32 = 0;
1026
1027// Alert Cause Register
1028pub const ALERT_HANDLER_ALERT_CAUSE_11_REG_OFFSET: usize = 0x350;
1029pub const ALERT_HANDLER_ALERT_CAUSE_11_A_11_BIT: u32 = 0;
1030
1031// Alert Cause Register
1032pub const ALERT_HANDLER_ALERT_CAUSE_12_REG_OFFSET: usize = 0x354;
1033pub const ALERT_HANDLER_ALERT_CAUSE_12_A_12_BIT: u32 = 0;
1034
1035// Alert Cause Register
1036pub const ALERT_HANDLER_ALERT_CAUSE_13_REG_OFFSET: usize = 0x358;
1037pub const ALERT_HANDLER_ALERT_CAUSE_13_A_13_BIT: u32 = 0;
1038
1039// Alert Cause Register
1040pub const ALERT_HANDLER_ALERT_CAUSE_14_REG_OFFSET: usize = 0x35c;
1041pub const ALERT_HANDLER_ALERT_CAUSE_14_A_14_BIT: u32 = 0;
1042
1043// Alert Cause Register
1044pub const ALERT_HANDLER_ALERT_CAUSE_15_REG_OFFSET: usize = 0x360;
1045pub const ALERT_HANDLER_ALERT_CAUSE_15_A_15_BIT: u32 = 0;
1046
1047// Alert Cause Register
1048pub const ALERT_HANDLER_ALERT_CAUSE_16_REG_OFFSET: usize = 0x364;
1049pub const ALERT_HANDLER_ALERT_CAUSE_16_A_16_BIT: u32 = 0;
1050
1051// Alert Cause Register
1052pub const ALERT_HANDLER_ALERT_CAUSE_17_REG_OFFSET: usize = 0x368;
1053pub const ALERT_HANDLER_ALERT_CAUSE_17_A_17_BIT: u32 = 0;
1054
1055// Alert Cause Register
1056pub const ALERT_HANDLER_ALERT_CAUSE_18_REG_OFFSET: usize = 0x36c;
1057pub const ALERT_HANDLER_ALERT_CAUSE_18_A_18_BIT: u32 = 0;
1058
1059// Alert Cause Register
1060pub const ALERT_HANDLER_ALERT_CAUSE_19_REG_OFFSET: usize = 0x370;
1061pub const ALERT_HANDLER_ALERT_CAUSE_19_A_19_BIT: u32 = 0;
1062
1063// Alert Cause Register
1064pub const ALERT_HANDLER_ALERT_CAUSE_20_REG_OFFSET: usize = 0x374;
1065pub const ALERT_HANDLER_ALERT_CAUSE_20_A_20_BIT: u32 = 0;
1066
1067// Alert Cause Register
1068pub const ALERT_HANDLER_ALERT_CAUSE_21_REG_OFFSET: usize = 0x378;
1069pub const ALERT_HANDLER_ALERT_CAUSE_21_A_21_BIT: u32 = 0;
1070
1071// Alert Cause Register
1072pub const ALERT_HANDLER_ALERT_CAUSE_22_REG_OFFSET: usize = 0x37c;
1073pub const ALERT_HANDLER_ALERT_CAUSE_22_A_22_BIT: u32 = 0;
1074
1075// Alert Cause Register
1076pub const ALERT_HANDLER_ALERT_CAUSE_23_REG_OFFSET: usize = 0x380;
1077pub const ALERT_HANDLER_ALERT_CAUSE_23_A_23_BIT: u32 = 0;
1078
1079// Alert Cause Register
1080pub const ALERT_HANDLER_ALERT_CAUSE_24_REG_OFFSET: usize = 0x384;
1081pub const ALERT_HANDLER_ALERT_CAUSE_24_A_24_BIT: u32 = 0;
1082
1083// Alert Cause Register
1084pub const ALERT_HANDLER_ALERT_CAUSE_25_REG_OFFSET: usize = 0x388;
1085pub const ALERT_HANDLER_ALERT_CAUSE_25_A_25_BIT: u32 = 0;
1086
1087// Alert Cause Register
1088pub const ALERT_HANDLER_ALERT_CAUSE_26_REG_OFFSET: usize = 0x38c;
1089pub const ALERT_HANDLER_ALERT_CAUSE_26_A_26_BIT: u32 = 0;
1090
1091// Alert Cause Register
1092pub const ALERT_HANDLER_ALERT_CAUSE_27_REG_OFFSET: usize = 0x390;
1093pub const ALERT_HANDLER_ALERT_CAUSE_27_A_27_BIT: u32 = 0;
1094
1095// Alert Cause Register
1096pub const ALERT_HANDLER_ALERT_CAUSE_28_REG_OFFSET: usize = 0x394;
1097pub const ALERT_HANDLER_ALERT_CAUSE_28_A_28_BIT: u32 = 0;
1098
1099// Alert Cause Register
1100pub const ALERT_HANDLER_ALERT_CAUSE_29_REG_OFFSET: usize = 0x398;
1101pub const ALERT_HANDLER_ALERT_CAUSE_29_A_29_BIT: u32 = 0;
1102
1103// Alert Cause Register
1104pub const ALERT_HANDLER_ALERT_CAUSE_30_REG_OFFSET: usize = 0x39c;
1105pub const ALERT_HANDLER_ALERT_CAUSE_30_A_30_BIT: u32 = 0;
1106
1107// Alert Cause Register
1108pub const ALERT_HANDLER_ALERT_CAUSE_31_REG_OFFSET: usize = 0x3a0;
1109pub const ALERT_HANDLER_ALERT_CAUSE_31_A_31_BIT: u32 = 0;
1110
1111// Alert Cause Register
1112pub const ALERT_HANDLER_ALERT_CAUSE_32_REG_OFFSET: usize = 0x3a4;
1113pub const ALERT_HANDLER_ALERT_CAUSE_32_A_32_BIT: u32 = 0;
1114
1115// Alert Cause Register
1116pub const ALERT_HANDLER_ALERT_CAUSE_33_REG_OFFSET: usize = 0x3a8;
1117pub const ALERT_HANDLER_ALERT_CAUSE_33_A_33_BIT: u32 = 0;
1118
1119// Alert Cause Register
1120pub const ALERT_HANDLER_ALERT_CAUSE_34_REG_OFFSET: usize = 0x3ac;
1121pub const ALERT_HANDLER_ALERT_CAUSE_34_A_34_BIT: u32 = 0;
1122
1123// Alert Cause Register
1124pub const ALERT_HANDLER_ALERT_CAUSE_35_REG_OFFSET: usize = 0x3b0;
1125pub const ALERT_HANDLER_ALERT_CAUSE_35_A_35_BIT: u32 = 0;
1126
1127// Alert Cause Register
1128pub const ALERT_HANDLER_ALERT_CAUSE_36_REG_OFFSET: usize = 0x3b4;
1129pub const ALERT_HANDLER_ALERT_CAUSE_36_A_36_BIT: u32 = 0;
1130
1131// Alert Cause Register
1132pub const ALERT_HANDLER_ALERT_CAUSE_37_REG_OFFSET: usize = 0x3b8;
1133pub const ALERT_HANDLER_ALERT_CAUSE_37_A_37_BIT: u32 = 0;
1134
1135// Alert Cause Register
1136pub const ALERT_HANDLER_ALERT_CAUSE_38_REG_OFFSET: usize = 0x3bc;
1137pub const ALERT_HANDLER_ALERT_CAUSE_38_A_38_BIT: u32 = 0;
1138
1139// Alert Cause Register
1140pub const ALERT_HANDLER_ALERT_CAUSE_39_REG_OFFSET: usize = 0x3c0;
1141pub const ALERT_HANDLER_ALERT_CAUSE_39_A_39_BIT: u32 = 0;
1142
1143// Alert Cause Register
1144pub const ALERT_HANDLER_ALERT_CAUSE_40_REG_OFFSET: usize = 0x3c4;
1145pub const ALERT_HANDLER_ALERT_CAUSE_40_A_40_BIT: u32 = 0;
1146
1147// Alert Cause Register
1148pub const ALERT_HANDLER_ALERT_CAUSE_41_REG_OFFSET: usize = 0x3c8;
1149pub const ALERT_HANDLER_ALERT_CAUSE_41_A_41_BIT: u32 = 0;
1150
1151// Alert Cause Register
1152pub const ALERT_HANDLER_ALERT_CAUSE_42_REG_OFFSET: usize = 0x3cc;
1153pub const ALERT_HANDLER_ALERT_CAUSE_42_A_42_BIT: u32 = 0;
1154
1155// Alert Cause Register
1156pub const ALERT_HANDLER_ALERT_CAUSE_43_REG_OFFSET: usize = 0x3d0;
1157pub const ALERT_HANDLER_ALERT_CAUSE_43_A_43_BIT: u32 = 0;
1158
1159// Alert Cause Register
1160pub const ALERT_HANDLER_ALERT_CAUSE_44_REG_OFFSET: usize = 0x3d4;
1161pub const ALERT_HANDLER_ALERT_CAUSE_44_A_44_BIT: u32 = 0;
1162
1163// Alert Cause Register
1164pub const ALERT_HANDLER_ALERT_CAUSE_45_REG_OFFSET: usize = 0x3d8;
1165pub const ALERT_HANDLER_ALERT_CAUSE_45_A_45_BIT: u32 = 0;
1166
1167// Alert Cause Register
1168pub const ALERT_HANDLER_ALERT_CAUSE_46_REG_OFFSET: usize = 0x3dc;
1169pub const ALERT_HANDLER_ALERT_CAUSE_46_A_46_BIT: u32 = 0;
1170
1171// Alert Cause Register
1172pub const ALERT_HANDLER_ALERT_CAUSE_47_REG_OFFSET: usize = 0x3e0;
1173pub const ALERT_HANDLER_ALERT_CAUSE_47_A_47_BIT: u32 = 0;
1174
1175// Alert Cause Register
1176pub const ALERT_HANDLER_ALERT_CAUSE_48_REG_OFFSET: usize = 0x3e4;
1177pub const ALERT_HANDLER_ALERT_CAUSE_48_A_48_BIT: u32 = 0;
1178
1179// Alert Cause Register
1180pub const ALERT_HANDLER_ALERT_CAUSE_49_REG_OFFSET: usize = 0x3e8;
1181pub const ALERT_HANDLER_ALERT_CAUSE_49_A_49_BIT: u32 = 0;
1182
1183// Alert Cause Register
1184pub const ALERT_HANDLER_ALERT_CAUSE_50_REG_OFFSET: usize = 0x3ec;
1185pub const ALERT_HANDLER_ALERT_CAUSE_50_A_50_BIT: u32 = 0;
1186
1187// Alert Cause Register
1188pub const ALERT_HANDLER_ALERT_CAUSE_51_REG_OFFSET: usize = 0x3f0;
1189pub const ALERT_HANDLER_ALERT_CAUSE_51_A_51_BIT: u32 = 0;
1190
1191// Alert Cause Register
1192pub const ALERT_HANDLER_ALERT_CAUSE_52_REG_OFFSET: usize = 0x3f4;
1193pub const ALERT_HANDLER_ALERT_CAUSE_52_A_52_BIT: u32 = 0;
1194
1195// Alert Cause Register
1196pub const ALERT_HANDLER_ALERT_CAUSE_53_REG_OFFSET: usize = 0x3f8;
1197pub const ALERT_HANDLER_ALERT_CAUSE_53_A_53_BIT: u32 = 0;
1198
1199// Alert Cause Register
1200pub const ALERT_HANDLER_ALERT_CAUSE_54_REG_OFFSET: usize = 0x3fc;
1201pub const ALERT_HANDLER_ALERT_CAUSE_54_A_54_BIT: u32 = 0;
1202
1203// Alert Cause Register
1204pub const ALERT_HANDLER_ALERT_CAUSE_55_REG_OFFSET: usize = 0x400;
1205pub const ALERT_HANDLER_ALERT_CAUSE_55_A_55_BIT: u32 = 0;
1206
1207// Alert Cause Register
1208pub const ALERT_HANDLER_ALERT_CAUSE_56_REG_OFFSET: usize = 0x404;
1209pub const ALERT_HANDLER_ALERT_CAUSE_56_A_56_BIT: u32 = 0;
1210
1211// Alert Cause Register
1212pub const ALERT_HANDLER_ALERT_CAUSE_57_REG_OFFSET: usize = 0x408;
1213pub const ALERT_HANDLER_ALERT_CAUSE_57_A_57_BIT: u32 = 0;
1214
1215// Alert Cause Register
1216pub const ALERT_HANDLER_ALERT_CAUSE_58_REG_OFFSET: usize = 0x40c;
1217pub const ALERT_HANDLER_ALERT_CAUSE_58_A_58_BIT: u32 = 0;
1218
1219// Alert Cause Register
1220pub const ALERT_HANDLER_ALERT_CAUSE_59_REG_OFFSET: usize = 0x410;
1221pub const ALERT_HANDLER_ALERT_CAUSE_59_A_59_BIT: u32 = 0;
1222
1223// Alert Cause Register
1224pub const ALERT_HANDLER_ALERT_CAUSE_60_REG_OFFSET: usize = 0x414;
1225pub const ALERT_HANDLER_ALERT_CAUSE_60_A_60_BIT: u32 = 0;
1226
1227// Alert Cause Register
1228pub const ALERT_HANDLER_ALERT_CAUSE_61_REG_OFFSET: usize = 0x418;
1229pub const ALERT_HANDLER_ALERT_CAUSE_61_A_61_BIT: u32 = 0;
1230
1231// Alert Cause Register
1232pub const ALERT_HANDLER_ALERT_CAUSE_62_REG_OFFSET: usize = 0x41c;
1233pub const ALERT_HANDLER_ALERT_CAUSE_62_A_62_BIT: u32 = 0;
1234
1235// Alert Cause Register
1236pub const ALERT_HANDLER_ALERT_CAUSE_63_REG_OFFSET: usize = 0x420;
1237pub const ALERT_HANDLER_ALERT_CAUSE_63_A_63_BIT: u32 = 0;
1238
1239// Alert Cause Register
1240pub const ALERT_HANDLER_ALERT_CAUSE_64_REG_OFFSET: usize = 0x424;
1241pub const ALERT_HANDLER_ALERT_CAUSE_64_A_64_BIT: u32 = 0;
1242
1243// Register write enable for alert enable bits. (common parameters)
1244pub const ALERT_HANDLER_LOC_ALERT_REGWEN_EN_FIELD_WIDTH: u32 = 1;
1245pub const ALERT_HANDLER_LOC_ALERT_REGWEN_EN_FIELDS_PER_REG: u32 = 32;
1246pub const ALERT_HANDLER_LOC_ALERT_REGWEN_MULTIREG_COUNT: u32 = 7;
1247
1248// Register write enable for alert enable bits.
1249pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_OFFSET: usize = 0x428;
1250pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_EN_0_BIT: u32 = 0;
1251
1252// Register write enable for alert enable bits.
1253pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_OFFSET: usize = 0x42c;
1254pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_EN_1_BIT: u32 = 0;
1255
1256// Register write enable for alert enable bits.
1257pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_OFFSET: usize = 0x430;
1258pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_EN_2_BIT: u32 = 0;
1259
1260// Register write enable for alert enable bits.
1261pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_OFFSET: usize = 0x434;
1262pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_EN_3_BIT: u32 = 0;
1263
1264// Register write enable for alert enable bits.
1265pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_OFFSET: usize = 0x438;
1266pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_EN_4_BIT: u32 = 0;
1267
1268// Register write enable for alert enable bits.
1269pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_OFFSET: usize = 0x43c;
1270pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_EN_5_BIT: u32 = 0;
1271
1272// Register write enable for alert enable bits.
1273pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_OFFSET: usize = 0x440;
1274pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_EN_6_BIT: u32 = 0;
1275
1276// Enable register for the local alerts
1277pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_EN_LA_FIELD_WIDTH: u32 = 1;
1278pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_EN_LA_FIELDS_PER_REG: u32 = 32;
1279pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_MULTIREG_COUNT: u32 = 7;
1280
1281// Enable register for the local alerts
1282pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET: usize = 0x444;
1283pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_EN_LA_0_BIT: u32 = 0;
1284
1285// Enable register for the local alerts
1286pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_OFFSET: usize = 0x448;
1287pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_EN_LA_1_BIT: u32 = 0;
1288
1289// Enable register for the local alerts
1290pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_OFFSET: usize = 0x44c;
1291pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_EN_LA_2_BIT: u32 = 0;
1292
1293// Enable register for the local alerts
1294pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_OFFSET: usize = 0x450;
1295pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_EN_LA_3_BIT: u32 = 0;
1296
1297// Enable register for the local alerts
1298pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_OFFSET: usize = 0x454;
1299pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_EN_LA_4_BIT: u32 = 0;
1300
1301// Enable register for the local alerts
1302pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_OFFSET: usize = 0x458;
1303pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_EN_LA_5_BIT: u32 = 0;
1304
1305// Enable register for the local alerts
1306pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_OFFSET: usize = 0x45c;
1307pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_EN_LA_6_BIT: u32 = 0;
1308
1309// Class assignment of the local alerts
1310pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_CLASS_LA_FIELD_WIDTH: u32 = 2;
1311pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_CLASS_LA_FIELDS_PER_REG: u32 = 16;
1312pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_MULTIREG_COUNT: u32 = 7;
1313
1314// Class assignment of the local alerts
1315pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET: usize = 0x460;
1316pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_MASK: u32 = 0x3;
1317pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_OFFSET: usize = 0;
1318pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSA: u32 = 0x0;
1319pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSB: u32 = 0x1;
1320pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSC: u32 = 0x2;
1321pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSD: u32 = 0x3;
1322
1323// Class assignment of the local alerts
1324pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_OFFSET: usize = 0x464;
1325pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_MASK: u32 = 0x3;
1326pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_OFFSET: usize = 0;
1327
1328// Class assignment of the local alerts
1329pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_OFFSET: usize = 0x468;
1330pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_MASK: u32 = 0x3;
1331pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_OFFSET: usize = 0;
1332
1333// Class assignment of the local alerts
1334pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_OFFSET: usize = 0x46c;
1335pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_MASK: u32 = 0x3;
1336pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_OFFSET: usize = 0;
1337
1338// Class assignment of the local alerts
1339pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_OFFSET: usize = 0x470;
1340pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_MASK: u32 = 0x3;
1341pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_OFFSET: usize = 0;
1342
1343// Class assignment of the local alerts
1344pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_OFFSET: usize = 0x474;
1345pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_MASK: u32 = 0x3;
1346pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_OFFSET: usize = 0;
1347
1348// Class assignment of the local alerts
1349pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_OFFSET: usize = 0x478;
1350pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_MASK: u32 = 0x3;
1351pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_OFFSET: usize = 0;
1352
1353// Alert Cause Register for the local alerts
1354pub const ALERT_HANDLER_LOC_ALERT_CAUSE_LA_FIELD_WIDTH: u32 = 1;
1355pub const ALERT_HANDLER_LOC_ALERT_CAUSE_LA_FIELDS_PER_REG: u32 = 32;
1356pub const ALERT_HANDLER_LOC_ALERT_CAUSE_MULTIREG_COUNT: u32 = 7;
1357
1358// Alert Cause Register for the local alerts
1359pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_OFFSET: usize = 0x47c;
1360pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_LA_0_BIT: u32 = 0;
1361
1362// Alert Cause Register for the local alerts
1363pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_OFFSET: usize = 0x480;
1364pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_LA_1_BIT: u32 = 0;
1365
1366// Alert Cause Register for the local alerts
1367pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_OFFSET: usize = 0x484;
1368pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_LA_2_BIT: u32 = 0;
1369
1370// Alert Cause Register for the local alerts
1371pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_OFFSET: usize = 0x488;
1372pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_LA_3_BIT: u32 = 0;
1373
1374// Alert Cause Register for the local alerts
1375pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_OFFSET: usize = 0x48c;
1376pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_LA_4_BIT: u32 = 0;
1377
1378// Alert Cause Register for the local alerts
1379pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_OFFSET: usize = 0x490;
1380pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_LA_5_BIT: u32 = 0;
1381
1382// Alert Cause Register for the local alerts
1383pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_OFFSET: usize = 0x494;
1384pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_LA_6_BIT: u32 = 0;
1385
1386// Lock bit for Class A configuration.
1387pub const ALERT_HANDLER_CLASSA_REGWEN_REG_OFFSET: usize = 0x498;
1388pub const ALERT_HANDLER_CLASSA_REGWEN_CLASSA_REGWEN_BIT: u32 = 0;
1389
1390// Escalation control register for alert Class A. Can not be modified if
1391// !!CLASSA_REGWEN is false.
1392pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET: usize = 0x49c;
1393pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT: u32 = 0;
1394pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT: u32 = 1;
1395pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E0_BIT: u32 = 2;
1396pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E1_BIT: u32 = 3;
1397pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E2_BIT: u32 = 4;
1398pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E3_BIT: u32 = 5;
1399pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_MASK: u32 = 0x3;
1400pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_OFFSET: usize = 6;
1401pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_MASK: u32 = 0x3;
1402pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_OFFSET: usize = 8;
1403pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_MASK: u32 = 0x3;
1404pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET: usize = 10;
1405pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_MASK: u32 = 0x3;
1406pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET: usize = 12;
1407
1408// Clear enable for escalation protocol of Class A alerts.
1409pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_OFFSET: usize = 0x4a0;
1410pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_CLASSA_CLR_REGWEN_BIT: u32 = 0;
1411
1412// Clear for escalation protocol of Class A.
1413pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_OFFSET: usize = 0x4a4;
1414pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_CLASSA_CLR_SHADOWED_BIT: u32 = 0;
1415
1416// Current accumulation value for alert Class A. Software can clear this
1417// register
1418pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_OFFSET: usize = 0x4a8;
1419pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_MASK: u32 = 0xffff;
1420pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_OFFSET: usize = 0;
1421
1422// Accumulation threshold value for alert Class A.
1423pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_OFFSET: usize = 0x4ac;
1424pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_MASK: u32 = 0xffff;
1425pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET: usize = 0;
1426
1427// Interrupt timeout in cycles.
1428pub const ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_OFFSET: usize = 0x4b0;
1429
1430// Crashdump trigger configuration for Class A.
1431pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: usize = 0x4b4;
1432pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_MASK: u32 = 0x3;
1433pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET: usize = 0;
1434
1435// Duration of escalation phase 0 for Class A.
1436pub const ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_OFFSET: usize = 0x4b8;
1437
1438// Duration of escalation phase 1 for Class A.
1439pub const ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_OFFSET: usize = 0x4bc;
1440
1441// Duration of escalation phase 2 for Class A.
1442pub const ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_OFFSET: usize = 0x4c0;
1443
1444// Duration of escalation phase 3 for Class A.
1445pub const ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_OFFSET: usize = 0x4c4;
1446
1447// Escalation counter in cycles for Class A.
1448pub const ALERT_HANDLER_CLASSA_ESC_CNT_REG_OFFSET: usize = 0x4c8;
1449
1450// Current escalation state of Class A. See also !!CLASSA_ESC_CNT.
1451pub const ALERT_HANDLER_CLASSA_STATE_REG_OFFSET: usize = 0x4cc;
1452pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_MASK: u32 = 0x7;
1453pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_OFFSET: usize = 0;
1454pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_IDLE: u32 = 0x0;
1455pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_TIMEOUT: u32 = 0x1;
1456pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_FSMERROR: u32 = 0x2;
1457pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_TERMINAL: u32 = 0x3;
1458pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE0: u32 = 0x4;
1459pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE1: u32 = 0x5;
1460pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE2: u32 = 0x6;
1461pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE3: u32 = 0x7;
1462
1463// Lock bit for Class B configuration.
1464pub const ALERT_HANDLER_CLASSB_REGWEN_REG_OFFSET: usize = 0x4d0;
1465pub const ALERT_HANDLER_CLASSB_REGWEN_CLASSB_REGWEN_BIT: u32 = 0;
1466
1467// Escalation control register for alert Class B. Can not be modified if
1468// !!CLASSB_REGWEN is false.
1469pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_OFFSET: usize = 0x4d4;
1470pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_BIT: u32 = 0;
1471pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_LOCK_BIT: u32 = 1;
1472pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E0_BIT: u32 = 2;
1473pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E1_BIT: u32 = 3;
1474pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E2_BIT: u32 = 4;
1475pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E3_BIT: u32 = 5;
1476pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_MASK: u32 = 0x3;
1477pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_OFFSET: usize = 6;
1478pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_MASK: u32 = 0x3;
1479pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_OFFSET: usize = 8;
1480pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_MASK: u32 = 0x3;
1481pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_OFFSET: usize = 10;
1482pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_MASK: u32 = 0x3;
1483pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_OFFSET: usize = 12;
1484
1485// Clear enable for escalation protocol of Class B alerts.
1486pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_OFFSET: usize = 0x4d8;
1487pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_CLASSB_CLR_REGWEN_BIT: u32 = 0;
1488
1489// Clear for escalation protocol of Class B.
1490pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_OFFSET: usize = 0x4dc;
1491pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_CLASSB_CLR_SHADOWED_BIT: u32 = 0;
1492
1493// Current accumulation value for alert Class B. Software can clear this
1494// register
1495pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_OFFSET: usize = 0x4e0;
1496pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_MASK: u32 = 0xffff;
1497pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_OFFSET: usize = 0;
1498
1499// Accumulation threshold value for alert Class B.
1500pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_OFFSET: usize = 0x4e4;
1501pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_MASK: u32 = 0xffff;
1502pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET: usize = 0;
1503
1504// Interrupt timeout in cycles.
1505pub const ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_OFFSET: usize = 0x4e8;
1506
1507// Crashdump trigger configuration for Class B.
1508pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: usize = 0x4ec;
1509pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_MASK: u32 = 0x3;
1510pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET: usize = 0;
1511
1512// Duration of escalation phase 0 for Class B.
1513pub const ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_OFFSET: usize = 0x4f0;
1514
1515// Duration of escalation phase 1 for Class B.
1516pub const ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_OFFSET: usize = 0x4f4;
1517
1518// Duration of escalation phase 2 for Class B.
1519pub const ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_OFFSET: usize = 0x4f8;
1520
1521// Duration of escalation phase 3 for Class B.
1522pub const ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_OFFSET: usize = 0x4fc;
1523
1524// Escalation counter in cycles for Class B.
1525pub const ALERT_HANDLER_CLASSB_ESC_CNT_REG_OFFSET: usize = 0x500;
1526
1527// Current escalation state of Class B. See also !!CLASSB_ESC_CNT.
1528pub const ALERT_HANDLER_CLASSB_STATE_REG_OFFSET: usize = 0x504;
1529pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_MASK: u32 = 0x7;
1530pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_OFFSET: usize = 0;
1531pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_IDLE: u32 = 0x0;
1532pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_TIMEOUT: u32 = 0x1;
1533pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_FSMERROR: u32 = 0x2;
1534pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_TERMINAL: u32 = 0x3;
1535pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE0: u32 = 0x4;
1536pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE1: u32 = 0x5;
1537pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE2: u32 = 0x6;
1538pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE3: u32 = 0x7;
1539
1540// Lock bit for Class C configuration.
1541pub const ALERT_HANDLER_CLASSC_REGWEN_REG_OFFSET: usize = 0x508;
1542pub const ALERT_HANDLER_CLASSC_REGWEN_CLASSC_REGWEN_BIT: u32 = 0;
1543
1544// Escalation control register for alert Class C. Can not be modified if
1545// !!CLASSC_REGWEN is false.
1546pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_OFFSET: usize = 0x50c;
1547pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_BIT: u32 = 0;
1548pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_LOCK_BIT: u32 = 1;
1549pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E0_BIT: u32 = 2;
1550pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E1_BIT: u32 = 3;
1551pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E2_BIT: u32 = 4;
1552pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E3_BIT: u32 = 5;
1553pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_MASK: u32 = 0x3;
1554pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_OFFSET: usize = 6;
1555pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_MASK: u32 = 0x3;
1556pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_OFFSET: usize = 8;
1557pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_MASK: u32 = 0x3;
1558pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_OFFSET: usize = 10;
1559pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_MASK: u32 = 0x3;
1560pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_OFFSET: usize = 12;
1561
1562// Clear enable for escalation protocol of Class C alerts.
1563pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_OFFSET: usize = 0x510;
1564pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_CLASSC_CLR_REGWEN_BIT: u32 = 0;
1565
1566// Clear for escalation protocol of Class C.
1567pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_OFFSET: usize = 0x514;
1568pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_CLASSC_CLR_SHADOWED_BIT: u32 = 0;
1569
1570// Current accumulation value for alert Class C. Software can clear this
1571// register
1572pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_OFFSET: usize = 0x518;
1573pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_MASK: u32 = 0xffff;
1574pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_OFFSET: usize = 0;
1575
1576// Accumulation threshold value for alert Class C.
1577pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_OFFSET: usize = 0x51c;
1578pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_MASK: u32 = 0xffff;
1579pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET: usize = 0;
1580
1581// Interrupt timeout in cycles.
1582pub const ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_OFFSET: usize = 0x520;
1583
1584// Crashdump trigger configuration for Class C.
1585pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: usize = 0x524;
1586pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_MASK: u32 = 0x3;
1587pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET: usize = 0;
1588
1589// Duration of escalation phase 0 for Class C.
1590pub const ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_OFFSET: usize = 0x528;
1591
1592// Duration of escalation phase 1 for Class C.
1593pub const ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_OFFSET: usize = 0x52c;
1594
1595// Duration of escalation phase 2 for Class C.
1596pub const ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_OFFSET: usize = 0x530;
1597
1598// Duration of escalation phase 3 for Class C.
1599pub const ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_OFFSET: usize = 0x534;
1600
1601// Escalation counter in cycles for Class C.
1602pub const ALERT_HANDLER_CLASSC_ESC_CNT_REG_OFFSET: usize = 0x538;
1603
1604// Current escalation state of Class C. See also !!CLASSC_ESC_CNT.
1605pub const ALERT_HANDLER_CLASSC_STATE_REG_OFFSET: usize = 0x53c;
1606pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_MASK: u32 = 0x7;
1607pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_OFFSET: usize = 0;
1608pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_IDLE: u32 = 0x0;
1609pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_TIMEOUT: u32 = 0x1;
1610pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_FSMERROR: u32 = 0x2;
1611pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_TERMINAL: u32 = 0x3;
1612pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE0: u32 = 0x4;
1613pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE1: u32 = 0x5;
1614pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE2: u32 = 0x6;
1615pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE3: u32 = 0x7;
1616
1617// Lock bit for Class D configuration.
1618pub const ALERT_HANDLER_CLASSD_REGWEN_REG_OFFSET: usize = 0x540;
1619pub const ALERT_HANDLER_CLASSD_REGWEN_CLASSD_REGWEN_BIT: u32 = 0;
1620
1621// Escalation control register for alert Class D. Can not be modified if
1622// !!CLASSD_REGWEN is false.
1623pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_OFFSET: usize = 0x544;
1624pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_BIT: u32 = 0;
1625pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_LOCK_BIT: u32 = 1;
1626pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E0_BIT: u32 = 2;
1627pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E1_BIT: u32 = 3;
1628pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E2_BIT: u32 = 4;
1629pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E3_BIT: u32 = 5;
1630pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_MASK: u32 = 0x3;
1631pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_OFFSET: usize = 6;
1632pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_MASK: u32 = 0x3;
1633pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_OFFSET: usize = 8;
1634pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_MASK: u32 = 0x3;
1635pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_OFFSET: usize = 10;
1636pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_MASK: u32 = 0x3;
1637pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_OFFSET: usize = 12;
1638
1639// Clear enable for escalation protocol of Class D alerts.
1640pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_OFFSET: usize = 0x548;
1641pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_CLASSD_CLR_REGWEN_BIT: u32 = 0;
1642
1643// Clear for escalation protocol of Class D.
1644pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_OFFSET: usize = 0x54c;
1645pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_CLASSD_CLR_SHADOWED_BIT: u32 = 0;
1646
1647// Current accumulation value for alert Class D. Software can clear this
1648// register
1649pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_OFFSET: usize = 0x550;
1650pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_MASK: u32 = 0xffff;
1651pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_OFFSET: usize = 0;
1652
1653// Accumulation threshold value for alert Class D.
1654pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_OFFSET: usize = 0x554;
1655pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_MASK: u32 = 0xffff;
1656pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET: usize = 0;
1657
1658// Interrupt timeout in cycles.
1659pub const ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_OFFSET: usize = 0x558;
1660
1661// Crashdump trigger configuration for Class D.
1662pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: usize = 0x55c;
1663pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_MASK: u32 = 0x3;
1664pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET: usize = 0;
1665
1666// Duration of escalation phase 0 for Class D.
1667pub const ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_OFFSET: usize = 0x560;
1668
1669// Duration of escalation phase 1 for Class D.
1670pub const ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_OFFSET: usize = 0x564;
1671
1672// Duration of escalation phase 2 for Class D.
1673pub const ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_OFFSET: usize = 0x568;
1674
1675// Duration of escalation phase 3 for Class D.
1676pub const ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_OFFSET: usize = 0x56c;
1677
1678// Escalation counter in cycles for Class D.
1679pub const ALERT_HANDLER_CLASSD_ESC_CNT_REG_OFFSET: usize = 0x570;
1680
1681// Current escalation state of Class D. See also !!CLASSD_ESC_CNT.
1682pub const ALERT_HANDLER_CLASSD_STATE_REG_OFFSET: usize = 0x574;
1683pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_MASK: u32 = 0x7;
1684pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_OFFSET: usize = 0;
1685pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_IDLE: u32 = 0x0;
1686pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_TIMEOUT: u32 = 0x1;
1687pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_FSMERROR: u32 = 0x2;
1688pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_TERMINAL: u32 = 0x3;
1689pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE0: u32 = 0x4;
1690pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE1: u32 = 0x5;
1691pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE2: u32 = 0x6;
1692pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE3: u32 = 0x7;
1693
1694// End generated register constants for alert_handler
opentitanlib/otp/alert_handler_regs.rs

opentitanlib/otp/
alert_handler_regs.rs
