Testplan

Testpoints

Stage V1 Testpoints

`smoke`

Test: acc_smoke

Smoke test, running a single fixed binary

This runs the binary from acc/dv/smoke/smoke_test.s, which is designed to check most of the implemented instructions. The unchanging binary should mean this basic test is particularly appropriate for CI.

`single_binary`

Test: acc_single

Run a single randomly-chosen binary

This test drives the main bulk of ACC testing. It picks a random binary from a pre-generated set and runs it, comparing against the model. We’ll run this with a large number of seeds and use functional coverage to track when verification of the internals of the core is done.

Sometimes enable the “done” interrupt to check that it and the error interrupt work correctly.

`csr_hw_reset`

Test: acc_csr_hw_reset

Verify the reset values as indicated in the RAL specification.

Write all CSRs with a random value.
Apply reset to the DUT as well as the RAL model.
Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
It is mandatory to run this test for all available interfaces the CSRs are accessible from.
Shuffle the list of CSRs first to remove the effect of ordering.

`csr_rw`

Test: acc_csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

Loop through each CSR to write it with a random value.
Read the CSR back and check for correctness while adhering to its access policies.
It is mandatory to run this test for all available interfaces the CSRs are accessible from.
Shuffle the list of CSRs first to remove the effect of ordering.

`csr_bit_bash`

Test: acc_csr_bit_bash

Verify no aliasing within individual bits of a CSR.

Walk a 1 through each CSR by flipping 1 bit at a time.
Read the CSR back and check for correctness while adhering to its access policies.
This verify that writing a specific bit within the CSR did not affect any of the other bits.
It is mandatory to run this test for all available interfaces the CSRs are accessible from.
Shuffle the list of CSRs first to remove the effect of ordering.

`csr_aliasing`

Test: acc_csr_aliasing

Verify no aliasing within the CSR address space.

Loop through each CSR to write it with a random value
Shuffle and read ALL CSRs back.
All CSRs except for the one that was written in this iteration should read back the previous value.
The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
It is mandatory to run this test for all available interfaces the CSRs are accessible from.
Shuffle the list of CSRs first to remove the effect of ordering.

`csr_mem_rw_with_rand_reset`

Test: acc_csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

Run csr_rw sequence to randomly access CSRs
If memory exists, run mem_partial_access in parallel with csr_rw
Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
It is mandatory to run this test for all available interfaces the CSRs are accessible from.

`regwen_csr_and_corresponding_lockable_csr`

Tests:

acc_csr_rw
acc_csr_aliasing

Verify regwen CSR and its corresponding lockable CSRs.

Randomly access all CSRs
Test when regwen CSR is set, its corresponding lockable CSRs become read-only registers

Note:

If regwen CSR is HW read-only, this feature can be fully tested by common CSR tests - csr_rw and csr_aliasing.
If regwen CSR is HW updated, a separate test should be created to test it.

This is only applicable if the block contains regwen and locakable CSRs.

`mem_walk`

Test: acc_mem_walk

Verify accessibility of all memories in the design.

Run the standard UVM mem walk sequence on all memories in the RAL model.
It is mandatory to run this test from all available interfaces the memories are accessible from.

`mem_partial_access`

Test: acc_mem_partial_access

Verify partial-accessibility of all memories in the design.

Do partial reads and writes into the memories and verify the outcome for correctness.
Also test outstanding access on memories

Stage V2 Testpoints

`reset_recovery`

Test: acc_reset

Run two binaries, resetting the first at an arbitrary time

Running another binary after a sudden and unexpected reset via the rst_ni signal will check that all state is properly re-initialized after a reset. We’d expect X-propagation checks to catch most problems like this, but an explicit reset sequence also adds the relevant FSM/toggle coverage.

`multi_error`

Test: acc_multi_err

Run instructions that cause multiple SW errors in a cycle

These are directed tests, designed to exhaustively trigger all the cases where a single instruction execution can fail for more than one reason. Since each of these instructions causes the operation to fail, we have to run an ACC operation for each. To do this, we compile and run all the binaries in a collection of ISS unit tests. We have coverage points to ensure we see every event we expect.

`back_to_back`

Test: acc_multi

Run sequences back-to-back

This runs several sequences back-to-back, without resets between them. This should catch initialisation problems where not all state is cleared between programs when there’s no reset.

`stress_all`

Test: acc_stress_all

Run assorted sequences back-to-back.

`lc_escalation`

Test: acc_escalate

Trigger the life cycle escalation input.

`zero_state_err_urnd`

Test: acc_zero_state_err_urnd

Trigger the “state is zero” error in URND, Check that fatal error is asserted.

`sw_errs_fatal_chk`

Test: acc_sw_errs_fatal_chk

Set ctrl.software_errs_fatal. When set software errors produce fatal errors, rather than recoverable errors.

`alert_test`

Test: acc_alert_test

Verify common alert_test CSR that allows SW to mock-inject alert requests.

Enable a random set of alert requests by writing random value to alert_test CSR.
Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
Repeat the above steps a bunch of times.

`intr_test`

Test: acc_intr_test

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
Randomly “turn on” interrupts by writing random value(s) to intr_test CSR(s).
Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
Repeat the above steps a bunch of times.

`tl_d_oob_addr_access`

Test: acc_tl_errors

Access out of bounds address and verify correctness of response / behavior

`tl_d_illegal_access`

Test: acc_tl_errors

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec

TL-UL protocol error cases
- invalid opcode
- some mask bits not set when opcode is PutFullData
- mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
- mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
- address and size aren’t aligned, e.g. a_address = 0x01, a_size != 0
- size is greater than 2
OpenTitan defined error cases
- access unmapped address, expect d_error = 1
- write a CSR with unaligned address, e.g. a_address[1:0] != 0
- write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
- write a memory with a_mask != '1 when it doesn’t support partial accesses
- read a WO (write-only) memory
- write a RO (read-only) memory
- write with instr_type = True

`tl_d_outstanding_access`

Tests:

acc_csr_hw_reset
acc_csr_rw
acc_csr_aliasing
acc_same_csr_outstanding

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

`tl_d_partial_access`

Tests:

acc_csr_hw_reset
acc_csr_rw
acc_csr_aliasing
acc_same_csr_outstanding

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

Stage V2S Testpoints

`mem_integrity`

Tests:

acc_imem_err
acc_dmem_err

Inject ECC errors into DMEM and IMEM and expect an alert

`internal_integrity`

Tests:

acc_alu_bignum_mod_err
acc_controller_ispr_rdata_err
acc_mac_bignum_acc_err
acc_urnd_err

Corrupt internal state and expect an alert

`kmac_error`

Test: acc_kmac_err

Create bad transactions for the AppIntf that force ACC into a fatal error.

`illegal_bus_access`

Test: acc_illegal_mem_acc

Trigger reads and writes to both DMEM and IMEM and expect a fatal alert for ILLEGAL_BUS_ACCESS. Check that *mem_rdata_bus pins are at 0 when reads are done

`acc_mem_gnt_acc_err`

Test: acc_mem_gnt_acc_err

Trigger a fault to cause the IMEM/DMEM grant signal to be false when req is asserted. This in turn should cause dmem_missed_gnt/imem_missed_gnt to get asserted resulting in a fatal alert (a bad_internal_state fatal error).

`acc_non_sec_partial_wipe`

Test: acc_partial_wipe

See a local wipe signal be raised when a secure wipe is not running. When this happens, we expect the RTL to stop with a fatal alert. The signals tracked are:

sec_wipe_mod_urnd_i in acc_alu_bignum
sec_wipe_zero_i in acc_controller
sec_wipe_base in acc_core
sec_wipe_wdr_q in acc_core
sec_wipe_stack_reset_i in acc_rf_base

`tl_intg_err`

Tests:

acc_tl_intg_err
acc_sec_cm

Verify that the data integrity check violation generates an alert.

Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.
Inject a fault at the onehot check in u_reg.u_prim_reg_we_check and verify the corresponding fatal alert occurs

`passthru_mem_tl_intg_err`

Test: acc_passthru_mem_tl_intg_err

Verify data integrity is stored in the passthru memory rather than generated after a read.

Randomly read a memory location and check the data integrity is correct.
Backdoor inject fault into this location.
Check the data integrity is incorrect but there is no d_error as the memory block should just pass the stored data and integrity to the processor where the integrity is compared.
Above sequences will be run with csr_rw_vseq to ensure it won’t affect CSR accesses.

`prim_fsm_check`

Test: acc_sec_cm

Verify that entering to an undefined state generates a fatal alert.

Stimulus:

Backdoor force the FSM to any of the undefined values.
Randomly force the FSM back to a defined state to ensure the error is latched and won’t go away until reset.
Within the next few cycles, the FSM landing in an invalid state should trigger a fatal alert.
Repeat for ALL prim_fsm instances in the DUT.

Checks:

Check that fatal alert is triggered.
Check that err_code/fault_status is updated correctly and preserved until reset.
Verify any operations that follow fail (as applicable).

`prim_count_check`

Test: acc_sec_cm

Verify that violating prim_count counter properties generate a fatal alert.

Stimulus:

At the falling edge (non-active edge), force the counter to a different value than expected.
Randomly force the counter back to a normal value to ensure the error is latched and won’t go away until reset.
Within the next few cycles, the violation of hardened counter property should generate a fatal alert.
Repeat for ALL prim_count instances in the DUT.

Checks:

Check that fatal alert is triggered.
Check that err_code/fault_status is updated correctly and preserved until reset.
Verify any operations that follow fail (as applicable).

`sec_cm_mem_scramble`

Test: acc_smoke

Verify the countermeasure(s) MEM.SCRAMBLE. Scrambling memory reads and writes are used by the DV simulation framework for reading from and writing to memory models. Hence there is no need to have a directed test for this countermeasure.

`sec_cm_data_mem_integrity`

Test: acc_dmem_err

Verify the countermeasure(s) DATA.MEM.INTEGRITY. Run an ACC program multiple times and corrupt the DMEM while the ACC is still running.

`sec_cm_instruction_mem_integrity`

Test: acc_imem_err

Verify the countermeasure(s) INSTRUCTION.MEM.INTEGRITY. Run an ACC program multiple times and corrupt the IMEM while the ACC is still running.

`sec_cm_bus_integrity`

Test: acc_tl_intg_err

Verify the countermeasure(s) BUS.INTEGRITY. This entry is covered by tl_access_test.

`sec_cm_controller_fsm_global_esc`

Test: acc_escalate

Verify the countermeasure(s) CONTROLLER.FSM.GLOBAL_ESC. Run an ACC program, drive lc_escalate_en_i port randomly to see global escalation locking up ACC.

`sec_cm_controller_fsm_local_esc`

Tests:

acc_imem_err
acc_dmem_err
acc_zero_state_err_urnd
acc_illegal_mem_acc
acc_sec_cm

Verify the countermeasure(s) CONTROLLER.FSM.LOCAL_ESC. The controller FSM moves to a terminal error state upon local escalation.

IMEM/DMEM error tests to see local escalation related with integrity Checking
Zero state URND test to see local escalation regarding a URND value of all zeros
Illegal memory access test to see local escalation while having illegal read and write accesses to the IMEM when the ACC is busy.
Bad internal state errors that are triggered by acc_sec_cm test will also cause local escalation to the locked state.

`sec_cm_controller_fsm_sparse`

Test: acc_sec_cm

Verify the countermeasure(s) CONTROLLER.FSM.SPARSE. This countermeasure is verified with a standardized test.

`sec_cm_scramble_key_sideload`

Test: acc_single

Verify the countermeasure(s) SCRAMBLE.KEY.SIDELOAD

Simulation can’t really prove that the sideload key is unreachable by SW. However, from defined CSRs and memory returned data, there is no way to read scramble key by SW.

`sec_cm_scramble_ctrl_fsm_local_esc`

Tests:

acc_imem_err
acc_dmem_err
acc_zero_state_err_urnd
acc_illegal_mem_acc
acc_sec_cm

Verify the countermeasure(s) SCRAMBLE_CTRL.FSM.LOCAL_ESC. The scramble controller FSM moves to a terminal error state upon local escalation.

IMEM/DMEM error tests to see local escalation related with integrity Checking
Zero state URND test to see local escalation regarding a URND value of all zeros
Illegal memory access test to see local escalation while having illegal read and write accesses to the IMEM when the ACC is busy.
Bad internal state errors that are triggered by acc_sec_cm test will also cause local escalation to the locked state.

`sec_cm_scramble_ctrl_fsm_sparse`

Test: acc_sec_cm

Verify the countermeasure(s) SCRAMBLE_CTRL.FSM.SPARSE. This countermeasure is verified with a standardized test.

`sec_cm_start_stop_ctrl_fsm_global_esc`

Test: acc_escalate

Verify the countermeasure(s) START_STOP_CTRL.FSM.GLOBAL_ESC. Run an ACC program, drive lc_escalate_en_i port randomly to see global escalation locking up the start-stop control FSM in ACC.

`sec_cm_start_stop_ctrl_fsm_local_esc`

Tests:

acc_imem_err
acc_dmem_err
acc_zero_state_err_urnd
acc_illegal_mem_acc
acc_sec_cm

Verify the countermeasure(s) START_STOP_CTRL.FSM.LOCAL_ESC. The start stop FSM moves to a terminal error state upon local escalation.

IMEM/DMEM error tests to see local escalation related with integrity Checking
Zero state URND test to see local escalation regarding a URND value of all zeros
Illegal memory access test to see local escalation while having illegal read and write accesses to the IMEM when the ACC is busy.
Bad internal state errors that are triggered by acc_sec_cm test will also cause local escalation to the locked state.

`sec_cm_ctrl_flow_sca`

Test: acc_single

Verify the countermeasure(s) CTRL_FLOW.SCA. Since this is related with unused parts of the control path not changing throughout an ACC run this security countermeasure is verified with assertions.

`sec_cm_data_mem_sw_noaccess`

Test: acc_sw_no_acc

Verify the countermeasure(s) DATA.MEM.SW_NOACCESS. Read write access using tl_access task is tested with the first Kib of address in DMEM. Expected result is a error response from the TLUL bus.

`sec_cm_key_sideload`

Test: acc_single

Verify the countermeasure(s) KEY.SIDELOAD. DV environment cannot verify the architectural choice of having sideloaded keys. ACC on top using this architecture, also raises an error in the case of invalid sideload keys.

Invalid sideload keys are allowed in the sideload key sequence fifty percent of the time by default. In that scenario ACC would generate a KEY_INVALID recoverable software error. This happens test agnostic so acc_single is mapped to represent an ACC run in general.

`sec_cm_tlul_fifo_ctr_redun`

Test: acc_sec_cm

Verify the countermeasure(s) TLUL_FIFO.CTR.REDUN.

Stage V3 Testpoints

`stress_all_with_rand_reset`

Test: acc_stress_all_with_rand_reset

This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.

Covergroups

regwen_val_when_new_value_written_cg

Cover each lockable reg field with these 2 cases:

When regwen = 1, a different value is written to the lockable CSR field, and a read occurs after that.
When regwen = 0, a different value is written to the lockable CSR field, and a read occurs after that.

This is only applicable if the block contains regwen and locakable CSRs.

tl_errors_cg

Cover the following error cases on TL-UL bus:

TL-UL protocol error cases.
OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

tl_intg_err_cg

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.

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