ACCSim - ACC Simulation Software

ACCSim class represents a simulator that models the whole ACC block. Therefore it includes abstract models for the state of the core, its memory modules, and also the register modules. It has methods for starting the execution, cycle-accurate simulation tracing, and for injecting errors and reacting to those errors with a secure wipe. Additionally, there is a KMAC model included into the simulator for exercising the sideload interface. As explained in the overall ACC DV documentation, this simulator is driven essentially from the SystemVerilog model of the ACC module.

The simulator works in a step-by-step fashion and it has multiple methods to apply external stimuli to ACC. In a typical run without errors, the ISS does the following:

1. Decode the program on the path given by iss_wrapper.cc by the decode_file method in decode.py.
2. Load the decoded program to a local list in sim.py.
3. With each step command from the SystemVerilog side, update the simulated state of the core (state.py), registers (wsr.py, csr.py and gpr.py) and data memory (dmem.py).
4. Once the step is done, pass the generated trace to iss_wrapper.cc, which to then passes it on to ACCTraceChecker.

Co-Simulation with RTL

For co-simulation of RTL and ISS, the acc_tracer module logs state changes of the RTL, and the ISS logs state changes of the Python model. Trace entries from the simulated core (aka. from RTL) appear as a result of DPI callbacks while ISS trace entries appear in the trace checker through ISSWrapper using OnIssTrace method after sending a step command to ACCSim. To check correct behavior, the two separate logs generated by the model and the RTL are compared. For more information about how ACC RTL produces traces see the Tracer README. To see the C++ program that compares both traces, check the method acc_trace_checker.cc in ../model/acc_trace_entry.

PQC Parameterization

ACCSim has been parameterized in accordance with the RTL by using the --pqc flag. This flag controls whether the vectorized instructions in isa.py are valid to execute given the current hardware configuration. It also controls the creation of PQC specific registers in wsr.py and csr.py. Finally, depending on the flag value, the KMAC model used in PQC simulation will be created or removed from state.py. For Co-Simulation with RTL, the acc_sim_cfg.hjson and acc_pqc_sim_cfg.hjson control the --pqc flag value to match the DV environment.