Coordinate activity between CSRNG’s AES and Entropy Source’s SHA3. When CSRNG gets a request and its AES is not active, it acknowledges and until the request has dropped neither runs its AES nor drops the acknowledge.
This alert is triggered when a recoverable alert occurs. Check the RECOV_ALERT_STS register to get more information.
fatal_alert
This alert triggers (i) if an illegal state machine state is reached, or (ii) if an AES fatal alert condition occurs, or (iii) if a fatal integrity failure is detected on the TL-UL bus.
OTP signal used to enable software access to registers.
CSRNG.MAIN_SM.FSM.SPARSE
The CSRNG main state machine uses a sparse state encoding.
CSRNG.UPDRSP.FSM.SPARSE
The CSRNG update response state machine uses a sparse state encoding.
CSRNG.UPDATE.FSM.SPARSE
The CSRNG update state machine uses a sparse state encoding.
CSRNG.BLK_ENC.FSM.SPARSE
The CSRNG block encrypt state machine uses a sparse state encoding.
CSRNG.OUTBLK.FSM.SPARSE
The CSRNG block output state machine uses a sparse state encoding.
CSRNG.GEN_CMD.CTR.REDUN
The generate command uses a counter that is protected by a second counter that counts in the opposite direction.
CSRNG.DRBG_UPD.CTR.REDUN
The ctr_drbg update algorithm uses a counter that is protected by a second counter that counts in the opposite direction.
CSRNG.DRBG_GEN.CTR.REDUN
The ctr_drbg generate algorithm uses a counter that is protected by a second counter that counts in the opposite direction.
CSRNG.CTRL.MUBI
Multi-bit field used for selection control.
CSRNG.MAIN_SM.CTR.LOCAL_ESC
A mismatch detected inside any CSRNG counter moves the main state machine into a terminal error state.
CSRNG.CONSTANTS.LC_GATED
Seed diversification based on the lifecycle state.
CSRNG.SW_GENBITS.BUS.CONSISTENCY
Comparison on successive bus values for genbits returned on the software channel.
CSRNG.TILE_LINK.BUS.INTEGRITY
Tilelink end-to-end bus integrity scheme.
CSRNG.AES_CIPHER.FSM.SPARSE
The AES cipher core FSM uses a sparse state encoding. See the AES module documentation for AES-specific countermeasures.
CSRNG.AES_CIPHER.FSM.REDUN
The AES cipher core FSM uses multiple, independent logic rails. See the AES module documentation for AES-specific countermeasures.
CSRNG.AES_CIPHER.CTRL.SPARSE
Critical control signals for the AES cipher core such as handshake and MUX control signals use sparse encodings. See the AES module documentation for AES-specific countermeasures.
CSRNG.AES_CIPHER.FSM.LOCAL_ESC
The AES cipher core FSM moves to a terminal error state upon local escalation. Can be triggered by AES_CIPHER.FSM.SPARSE, AES_CIPHER.FSM.REDUN, AES_CIPHER.CTR.REDUN and AES_CIPHER.CTRL.SPARSE. See the AES module documentation for AES-specific countermeasures.
CSRNG.AES_CIPHER.CTR.REDUN
The AES round counter inside the AES cipher core FSM is protected with multiple, independent logic rails. See the AES module documentation for AES-specific countermeasures.
CSRNG.AES_CIPHER.DATA_REG.LOCAL_ESC
Upon local escalation, the AES cipher core doesn’t output intermediate state. See the AES module documentation for AES-specific countermeasures.
