Pavona ROM
The ROM is the first software that executes after a device reset, and also serves as the first boot stage in the Pavona Secure Boot implementation. The ROM contents are included in the wafer mask and programmed into the chip’s metal ROM during wafer manufacturing. As a result, the contents are fixed across an entire chip SKU and cannot be updated in-field.
Top-level designs may be configured using either a single- or a dual-stage ROM. The Egret discrete reference design uses a single-stage ROM, and the Dragonfly integrated reference design uses a dual-stage ROM. In a dual-stage ROM, the second stage ROM (ROM1) supports optional patches loaded to OTP that are signed by the Silicon Creator and verified by the first-stage (ROM0).
The purpose of the ROM is to initialize a set of critical hardware blocks and verify that the loaded silicon creator firmware is allowed to be executed on the chip.
