Topgen Tool: Describes topgen.py and its Hjson format source.
Used to generate RTL and validation files for top specific modules such as PLIC, pinmux, and crossbar.
Register Tool: Describes regtool.py and its Hjson format source.
Used to generate documentation, RTL, header files, and validation files for IP registers and top level.
Ipgen Tool: Describes ipgen.py and its Hjson control file.
Used to generate IP blocks from IP templates.
Crossbar Tool: Describes tlgen.py and its Hjson format source.
Used to generate RTL files of the crossbars at the top level.
DVSim: Describes dvsim/dvsim.py.
Used to build and run design verification (DV) tests.
Fpvgen Tool: Describes fpvgen.py.
Used to generate initial code for formal property verification (FPV) testbenches.
Uvmdvgen Tool: Describes uvmdvgen.py.
Used to generate initial UVM-based code for DV testbenches.
Device Table Tool: Describes dttool.py.
Used to generate software device tables based on a top configuration.
Vendor-In Tool: Describes vendor.py and its Hjson control file.
Used to pull a local copy of code maintained in other upstream repositories and apply local patch sets.
Design-related tooling: Describes miscellaneous design-related scripts under design/.
This includes a variety of generator tools and useful scripts.
I2C to SVG Tool: Describes i2csvg.py.
Used to generate svg images from text files of I2C transactions.
