Pavona Software APIs
otp_ctrl.c
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7/**
8 * @file
9 * @brief Device Tables (DT) for IP otp_ctrl and top dragonfly.
10 */
11
12#include "hw/top/dt/otp_ctrl.h"
13
14
15#include "hw/top/otp_ctrl_regs.h"
16
17
18/**
19 * Description of instances.
20 */
21typedef struct dt_desc_otp_ctrl {
22 dt_instance_id_t inst_id; /**< Instance ID */
23 uint32_t reg_addr[kDtOtpCtrlRegBlockCount]; /**< Base address of each register block */
24 /**
25 * PLIC ID of the first IRQ of this instance
26 *
27 * This can be `kDtPlicIrqIdNone` if the block is not connected to the PLIC.
28 */
29 top_dragonfly_plic_irq_id_t first_irq;
30 /**
31 * Alert ID of the first Alert of this instance.
32 *
33 * This value is undefined if the block is not connected to the Alert Handler.
34 */
35 top_dragonfly_alert_id_t first_alert;
36 dt_clock_t clock[kDtOtpCtrlClockCount]; /**< Clock signal connected to each clock port */
37 dt_reset_t reset[kDtOtpCtrlResetCount]; /**< Reset signal connected to each reset port */
38 struct {
39 dt_otp_partition_info_t info[26]; /**< List of OTP partitions */
40 } partitions; /**< Extension */
41} dt_desc_otp_ctrl_t;
42
43
44
45
46static const dt_desc_otp_ctrl_t otp_ctrl_desc[kDtOtpCtrlCount] = {
47 [kDtOtpCtrl] = {
48 .inst_id = kDtInstanceIdOtpCtrl,
49 .reg_addr = {
50 [kDtOtpCtrlRegBlockCore] = 0x30130000,
51 },
52 .first_irq = kTopDragonflyPlicIrqIdOtpCtrlOtpOperationDone,
53 .first_alert = kTopDragonflyAlertIdOtpCtrlFatalMacroError,
54 .clock = {
55 [kDtOtpCtrlClockClk] = kDtClockIo,
56 [kDtOtpCtrlClockEdn] = kDtClockMain,
57 },
58 .reset = {
59 [kDtOtpCtrlResetRst] = kDtResetLcIo,
60 [kDtOtpCtrlResetEdn] = kDtResetLc,
61 },
62 .partitions = {
63 .info = {
64 [kOtpPartitionVendorTest] = {
65 .start_addr = OTP_CTRL_PARAM_VENDOR_TEST_OFFSET,
66 .size = OTP_CTRL_PARAM_VENDOR_TEST_SIZE - OTP_CTRL_PARAM_VENDOR_TEST_DIGEST_SIZE - OTP_CTRL_PARAM_VENDOR_TEST_ZER_SIZE,
67 .sw_readable = 1,
68 .sw_digest = 1,
69 .hw_digest = 0,
70 .digest_reg_offset = OTP_CTRL_VENDOR_TEST_DIGEST_0_REG_OFFSET,
71 .read_lockable = 1,
72 .lock_reg_offset = OTP_CTRL_VENDOR_TEST_READ_LOCK_REG_OFFSET,
73 .read_lock_bit = OTP_CTRL_VENDOR_TEST_READ_LOCK_VENDOR_TEST_READ_LOCK_BIT,
74 .zeroizable = 1,
75 .is_lifecycle = 0,
76 .align_mask = 0x3,
77 },
78 [kOtpPartitionCreatorSwCfg] = {
79 .start_addr = OTP_CTRL_PARAM_CREATOR_SW_CFG_OFFSET,
80 .size = OTP_CTRL_PARAM_CREATOR_SW_CFG_SIZE - OTP_CTRL_PARAM_CREATOR_SW_CFG_DIGEST_SIZE - OTP_CTRL_PARAM_CREATOR_SW_CFG_ZER_SIZE,
81 .sw_readable = 1,
82 .sw_digest = 1,
83 .hw_digest = 0,
84 .digest_reg_offset = OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_REG_OFFSET,
85 .read_lockable = 1,
86 .lock_reg_offset = OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_REG_OFFSET,
87 .read_lock_bit = OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_CREATOR_SW_CFG_READ_LOCK_BIT,
88 .zeroizable = 1,
89 .is_lifecycle = 0,
90 .align_mask = 0x3,
91 },
92 [kOtpPartitionOwnerSwCfg] = {
93 .start_addr = OTP_CTRL_PARAM_OWNER_SW_CFG_OFFSET,
94 .size = OTP_CTRL_PARAM_OWNER_SW_CFG_SIZE - OTP_CTRL_PARAM_OWNER_SW_CFG_DIGEST_SIZE - OTP_CTRL_PARAM_OWNER_SW_CFG_ZER_SIZE,
95 .sw_readable = 1,
96 .sw_digest = 1,
97 .hw_digest = 0,
98 .digest_reg_offset = OTP_CTRL_OWNER_SW_CFG_DIGEST_0_REG_OFFSET,
99 .read_lockable = 1,
100 .lock_reg_offset = OTP_CTRL_OWNER_SW_CFG_READ_LOCK_REG_OFFSET,
101 .read_lock_bit = OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OWNER_SW_CFG_READ_LOCK_BIT,
102 .zeroizable = 1,
103 .is_lifecycle = 0,
104 .align_mask = 0x3,
105 },
106 [kOtpPartitionOwnershipSlotState] = {
107 .start_addr = OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_OFFSET,
108 .size = OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_SIZE - OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_ZER_SIZE,
109 .sw_readable = 0,
110 .sw_digest = 0,
111 .hw_digest = 0,
112 .digest_reg_offset = 0xdeadbeef,
113 .read_lockable = 1,
114 .lock_reg_offset = OTP_CTRL_OWNERSHIP_SLOT_STATE_READ_LOCK_REG_OFFSET,
115 .read_lock_bit = OTP_CTRL_OWNERSHIP_SLOT_STATE_READ_LOCK_OWNERSHIP_SLOT_STATE_READ_LOCK_BIT,
116 .zeroizable = 1,
117 .is_lifecycle = 0,
118 .align_mask = 0x3,
119 },
120 [kOtpPartitionRotCreatorIdentity] = {
121 .start_addr = OTP_CTRL_PARAM_ROT_CREATOR_IDENTITY_OFFSET,
122 .size = OTP_CTRL_PARAM_ROT_CREATOR_IDENTITY_SIZE - OTP_CTRL_PARAM_ROT_CREATOR_IDENTITY_DIGEST_SIZE - OTP_CTRL_PARAM_ROT_CREATOR_IDENTITY_ZER_SIZE,
123 .sw_readable = 1,
124 .sw_digest = 1,
125 .hw_digest = 0,
126 .digest_reg_offset = OTP_CTRL_ROT_CREATOR_IDENTITY_DIGEST_0_REG_OFFSET,
127 .read_lockable = 1,
128 .lock_reg_offset = OTP_CTRL_ROT_CREATOR_IDENTITY_READ_LOCK_REG_OFFSET,
129 .read_lock_bit = OTP_CTRL_ROT_CREATOR_IDENTITY_READ_LOCK_ROT_CREATOR_IDENTITY_READ_LOCK_BIT,
130 .zeroizable = 1,
131 .is_lifecycle = 0,
132 .align_mask = 0x3,
133 },
134 [kOtpPartitionRotOwnerAuthSlot0] = {
135 .start_addr = OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_OFFSET,
136 .size = OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_SIZE - OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_DIGEST_SIZE - OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_ZER_SIZE,
137 .sw_readable = 1,
138 .sw_digest = 1,
139 .hw_digest = 0,
140 .digest_reg_offset = OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_0_REG_OFFSET,
141 .read_lockable = 1,
142 .lock_reg_offset = OTP_CTRL_ROT_OWNER_AUTH_SLOT0_READ_LOCK_REG_OFFSET,
143 .read_lock_bit = OTP_CTRL_ROT_OWNER_AUTH_SLOT0_READ_LOCK_ROT_OWNER_AUTH_SLOT0_READ_LOCK_BIT,
144 .zeroizable = 1,
145 .is_lifecycle = 0,
146 .align_mask = 0x3,
147 },
148 [kOtpPartitionRotOwnerAuthSlot1] = {
149 .start_addr = OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_OFFSET,
150 .size = OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_SIZE - OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_DIGEST_SIZE - OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_ZER_SIZE,
151 .sw_readable = 1,
152 .sw_digest = 1,
153 .hw_digest = 0,
154 .digest_reg_offset = OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_0_REG_OFFSET,
155 .read_lockable = 1,
156 .lock_reg_offset = OTP_CTRL_ROT_OWNER_AUTH_SLOT1_READ_LOCK_REG_OFFSET,
157 .read_lock_bit = OTP_CTRL_ROT_OWNER_AUTH_SLOT1_READ_LOCK_ROT_OWNER_AUTH_SLOT1_READ_LOCK_BIT,
158 .zeroizable = 1,
159 .is_lifecycle = 0,
160 .align_mask = 0x3,
161 },
162 [kOtpPartitionPlatIntegAuthSlot0] = {
163 .start_addr = OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_OFFSET,
164 .size = OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_SIZE - OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_DIGEST_SIZE - OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_ZER_SIZE,
165 .sw_readable = 1,
166 .sw_digest = 1,
167 .hw_digest = 0,
168 .digest_reg_offset = OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_0_REG_OFFSET,
169 .read_lockable = 1,
170 .lock_reg_offset = OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_READ_LOCK_REG_OFFSET,
171 .read_lock_bit = OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_READ_LOCK_PLAT_INTEG_AUTH_SLOT0_READ_LOCK_BIT,
172 .zeroizable = 1,
173 .is_lifecycle = 0,
174 .align_mask = 0x3,
175 },
176 [kOtpPartitionPlatIntegAuthSlot1] = {
177 .start_addr = OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_OFFSET,
178 .size = OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_SIZE - OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_DIGEST_SIZE - OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_ZER_SIZE,
179 .sw_readable = 1,
180 .sw_digest = 1,
181 .hw_digest = 0,
182 .digest_reg_offset = OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_0_REG_OFFSET,
183 .read_lockable = 1,
184 .lock_reg_offset = OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_READ_LOCK_REG_OFFSET,
185 .read_lock_bit = OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_READ_LOCK_PLAT_INTEG_AUTH_SLOT1_READ_LOCK_BIT,
186 .zeroizable = 1,
187 .is_lifecycle = 0,
188 .align_mask = 0x3,
189 },
190 [kOtpPartitionPlatOwnerAuthSlot0] = {
191 .start_addr = OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_OFFSET,
192 .size = OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_SIZE - OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_DIGEST_SIZE - OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_ZER_SIZE,
193 .sw_readable = 1,
194 .sw_digest = 1,
195 .hw_digest = 0,
196 .digest_reg_offset = OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_0_REG_OFFSET,
197 .read_lockable = 1,
198 .lock_reg_offset = OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_READ_LOCK_REG_OFFSET,
199 .read_lock_bit = OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_READ_LOCK_PLAT_OWNER_AUTH_SLOT0_READ_LOCK_BIT,
200 .zeroizable = 1,
201 .is_lifecycle = 0,
202 .align_mask = 0x3,
203 },
204 [kOtpPartitionPlatOwnerAuthSlot1] = {
205 .start_addr = OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_OFFSET,
206 .size = OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_SIZE - OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_DIGEST_SIZE - OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_ZER_SIZE,
207 .sw_readable = 1,
208 .sw_digest = 1,
209 .hw_digest = 0,
210 .digest_reg_offset = OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_0_REG_OFFSET,
211 .read_lockable = 1,
212 .lock_reg_offset = OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_READ_LOCK_REG_OFFSET,
213 .read_lock_bit = OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_READ_LOCK_PLAT_OWNER_AUTH_SLOT1_READ_LOCK_BIT,
214 .zeroizable = 1,
215 .is_lifecycle = 0,
216 .align_mask = 0x3,
217 },
218 [kOtpPartitionPlatOwnerAuthSlot2] = {
219 .start_addr = OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_OFFSET,
220 .size = OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_SIZE - OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_DIGEST_SIZE - OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_ZER_SIZE,
221 .sw_readable = 1,
222 .sw_digest = 1,
223 .hw_digest = 0,
224 .digest_reg_offset = OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_0_REG_OFFSET,
225 .read_lockable = 1,
226 .lock_reg_offset = OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_READ_LOCK_REG_OFFSET,
227 .read_lock_bit = OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_READ_LOCK_PLAT_OWNER_AUTH_SLOT2_READ_LOCK_BIT,
228 .zeroizable = 1,
229 .is_lifecycle = 0,
230 .align_mask = 0x3,
231 },
232 [kOtpPartitionPlatOwnerAuthSlot3] = {
233 .start_addr = OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_OFFSET,
234 .size = OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_SIZE - OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_DIGEST_SIZE - OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_ZER_SIZE,
235 .sw_readable = 1,
236 .sw_digest = 1,
237 .hw_digest = 0,
238 .digest_reg_offset = OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_0_REG_OFFSET,
239 .read_lockable = 1,
240 .lock_reg_offset = OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_READ_LOCK_REG_OFFSET,
241 .read_lock_bit = OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_READ_LOCK_PLAT_OWNER_AUTH_SLOT3_READ_LOCK_BIT,
242 .zeroizable = 1,
243 .is_lifecycle = 0,
244 .align_mask = 0x3,
245 },
246 [kOtpPartitionExtNvm] = {
247 .start_addr = OTP_CTRL_PARAM_EXT_NVM_OFFSET,
248 .size = OTP_CTRL_PARAM_EXT_NVM_SIZE - OTP_CTRL_PARAM_EXT_NVM_ZER_SIZE,
249 .sw_readable = 0,
250 .sw_digest = 0,
251 .hw_digest = 0,
252 .digest_reg_offset = 0xdeadbeef,
253 .read_lockable = 1,
254 .lock_reg_offset = OTP_CTRL_EXT_NVM_READ_LOCK_REG_OFFSET,
255 .read_lock_bit = OTP_CTRL_EXT_NVM_READ_LOCK_EXT_NVM_READ_LOCK_BIT,
256 .zeroizable = 1,
257 .is_lifecycle = 0,
258 .align_mask = 0x3,
259 },
260 [kOtpPartitionRomPatch] = {
261 .start_addr = OTP_CTRL_PARAM_ROM_PATCH_OFFSET,
262 .size = OTP_CTRL_PARAM_ROM_PATCH_SIZE - OTP_CTRL_PARAM_ROM_PATCH_DIGEST_SIZE - OTP_CTRL_PARAM_ROM_PATCH_ZER_SIZE,
263 .sw_readable = 1,
264 .sw_digest = 1,
265 .hw_digest = 0,
266 .digest_reg_offset = OTP_CTRL_ROM_PATCH_DIGEST_0_REG_OFFSET,
267 .read_lockable = 1,
268 .lock_reg_offset = OTP_CTRL_ROM_PATCH_READ_LOCK_REG_OFFSET,
269 .read_lock_bit = OTP_CTRL_ROM_PATCH_READ_LOCK_ROM_PATCH_READ_LOCK_BIT,
270 .zeroizable = 1,
271 .is_lifecycle = 0,
272 .align_mask = 0x3,
273 },
274 [kOtpPartitionSocFusesCp] = {
275 .start_addr = OTP_CTRL_PARAM_SOC_FUSES_CP_OFFSET,
276 .size = OTP_CTRL_PARAM_SOC_FUSES_CP_SIZE - OTP_CTRL_PARAM_SOC_FUSES_CP_DIGEST_SIZE,
277 .sw_readable = 1,
278 .sw_digest = 1,
279 .hw_digest = 0,
280 .digest_reg_offset = OTP_CTRL_SOC_FUSES_CP_DIGEST_0_REG_OFFSET,
281 .read_lockable = 1,
282 .lock_reg_offset = OTP_CTRL_SOC_FUSES_CP_READ_LOCK_REG_OFFSET,
283 .read_lock_bit = OTP_CTRL_SOC_FUSES_CP_READ_LOCK_SOC_FUSES_CP_READ_LOCK_BIT,
284 .zeroizable = 0,
285 .is_lifecycle = 0,
286 .align_mask = 0x3,
287 },
288 [kOtpPartitionSocFusesFt] = {
289 .start_addr = OTP_CTRL_PARAM_SOC_FUSES_FT_OFFSET,
290 .size = OTP_CTRL_PARAM_SOC_FUSES_FT_SIZE - OTP_CTRL_PARAM_SOC_FUSES_FT_DIGEST_SIZE,
291 .sw_readable = 1,
292 .sw_digest = 1,
293 .hw_digest = 0,
294 .digest_reg_offset = OTP_CTRL_SOC_FUSES_FT_DIGEST_0_REG_OFFSET,
295 .read_lockable = 1,
296 .lock_reg_offset = OTP_CTRL_SOC_FUSES_FT_READ_LOCK_REG_OFFSET,
297 .read_lock_bit = OTP_CTRL_SOC_FUSES_FT_READ_LOCK_SOC_FUSES_FT_READ_LOCK_BIT,
298 .zeroizable = 0,
299 .is_lifecycle = 0,
300 .align_mask = 0x3,
301 },
302 [kOtpPartitionScratchFuses] = {
303 .start_addr = OTP_CTRL_PARAM_SCRATCH_FUSES_OFFSET,
304 .size = OTP_CTRL_PARAM_SCRATCH_FUSES_SIZE - OTP_CTRL_PARAM_SCRATCH_FUSES_ZER_SIZE,
305 .sw_readable = 0,
306 .sw_digest = 0,
307 .hw_digest = 0,
308 .digest_reg_offset = 0xdeadbeef,
309 .read_lockable = 1,
310 .lock_reg_offset = OTP_CTRL_SCRATCH_FUSES_READ_LOCK_REG_OFFSET,
311 .read_lock_bit = OTP_CTRL_SCRATCH_FUSES_READ_LOCK_SCRATCH_FUSES_READ_LOCK_BIT,
312 .zeroizable = 1,
313 .is_lifecycle = 0,
314 .align_mask = 0x3,
315 },
316 [kOtpPartitionHwCfg0] = {
317 .start_addr = OTP_CTRL_PARAM_HW_CFG0_OFFSET,
318 .size = OTP_CTRL_PARAM_HW_CFG0_SIZE - OTP_CTRL_PARAM_HW_CFG0_DIGEST_SIZE - OTP_CTRL_PARAM_HW_CFG0_ZER_SIZE,
319 .sw_readable = 1,
320 .sw_digest = 0,
321 .hw_digest = 1,
322 .digest_reg_offset = OTP_CTRL_HW_CFG0_DIGEST_0_REG_OFFSET,
323 .read_lockable = 0,
324 .lock_reg_offset = 0xdeadbeef,
325 .read_lock_bit = 0xdeadbeef,
326 .zeroizable = 1,
327 .is_lifecycle = 0,
328 .align_mask = 0x3,
329 },
330 [kOtpPartitionHwCfg1] = {
331 .start_addr = OTP_CTRL_PARAM_HW_CFG1_OFFSET,
332 .size = OTP_CTRL_PARAM_HW_CFG1_SIZE - OTP_CTRL_PARAM_HW_CFG1_DIGEST_SIZE - OTP_CTRL_PARAM_HW_CFG1_ZER_SIZE,
333 .sw_readable = 1,
334 .sw_digest = 0,
335 .hw_digest = 1,
336 .digest_reg_offset = OTP_CTRL_HW_CFG1_DIGEST_0_REG_OFFSET,
337 .read_lockable = 0,
338 .lock_reg_offset = 0xdeadbeef,
339 .read_lock_bit = 0xdeadbeef,
340 .zeroizable = 1,
341 .is_lifecycle = 0,
342 .align_mask = 0x3,
343 },
344 [kOtpPartitionHwCfg2] = {
345 .start_addr = OTP_CTRL_PARAM_HW_CFG2_OFFSET,
346 .size = OTP_CTRL_PARAM_HW_CFG2_SIZE - OTP_CTRL_PARAM_HW_CFG2_DIGEST_SIZE - OTP_CTRL_PARAM_HW_CFG2_ZER_SIZE,
347 .sw_readable = 1,
348 .sw_digest = 0,
349 .hw_digest = 1,
350 .digest_reg_offset = OTP_CTRL_HW_CFG2_DIGEST_0_REG_OFFSET,
351 .read_lockable = 0,
352 .lock_reg_offset = 0xdeadbeef,
353 .read_lock_bit = 0xdeadbeef,
354 .zeroizable = 1,
355 .is_lifecycle = 0,
356 .align_mask = 0x3,
357 },
358 [kOtpPartitionSecret0] = {
359 .start_addr = OTP_CTRL_PARAM_SECRET0_OFFSET,
360 .size = OTP_CTRL_PARAM_SECRET0_SIZE - OTP_CTRL_PARAM_SECRET0_DIGEST_SIZE - OTP_CTRL_PARAM_SECRET0_ZER_SIZE,
361 .sw_readable = 0,
362 .sw_digest = 0,
363 .hw_digest = 1,
364 .digest_reg_offset = OTP_CTRL_SECRET0_DIGEST_0_REG_OFFSET,
365 .read_lockable = 0,
366 .lock_reg_offset = 0xdeadbeef,
367 .read_lock_bit = 0xdeadbeef,
368 .zeroizable = 1,
369 .is_lifecycle = 0,
370 .align_mask = 0x7,
371 },
372 [kOtpPartitionSecret1] = {
373 .start_addr = OTP_CTRL_PARAM_SECRET1_OFFSET,
374 .size = OTP_CTRL_PARAM_SECRET1_SIZE - OTP_CTRL_PARAM_SECRET1_DIGEST_SIZE - OTP_CTRL_PARAM_SECRET1_ZER_SIZE,
375 .sw_readable = 0,
376 .sw_digest = 0,
377 .hw_digest = 1,
378 .digest_reg_offset = OTP_CTRL_SECRET1_DIGEST_0_REG_OFFSET,
379 .read_lockable = 0,
380 .lock_reg_offset = 0xdeadbeef,
381 .read_lock_bit = 0xdeadbeef,
382 .zeroizable = 1,
383 .is_lifecycle = 0,
384 .align_mask = 0x7,
385 },
386 [kOtpPartitionSecret2] = {
387 .start_addr = OTP_CTRL_PARAM_SECRET2_OFFSET,
388 .size = OTP_CTRL_PARAM_SECRET2_SIZE - OTP_CTRL_PARAM_SECRET2_DIGEST_SIZE - OTP_CTRL_PARAM_SECRET2_ZER_SIZE,
389 .sw_readable = 0,
390 .sw_digest = 0,
391 .hw_digest = 1,
392 .digest_reg_offset = OTP_CTRL_SECRET2_DIGEST_0_REG_OFFSET,
393 .read_lockable = 0,
394 .lock_reg_offset = 0xdeadbeef,
395 .read_lock_bit = 0xdeadbeef,
396 .zeroizable = 1,
397 .is_lifecycle = 0,
398 .align_mask = 0x7,
399 },
400 [kOtpPartitionSecret3] = {
401 .start_addr = OTP_CTRL_PARAM_SECRET3_OFFSET,
402 .size = OTP_CTRL_PARAM_SECRET3_SIZE - OTP_CTRL_PARAM_SECRET3_DIGEST_SIZE - OTP_CTRL_PARAM_SECRET3_ZER_SIZE,
403 .sw_readable = 0,
404 .sw_digest = 0,
405 .hw_digest = 1,
406 .digest_reg_offset = OTP_CTRL_SECRET3_DIGEST_0_REG_OFFSET,
407 .read_lockable = 0,
408 .lock_reg_offset = 0xdeadbeef,
409 .read_lock_bit = 0xdeadbeef,
410 .zeroizable = 1,
411 .is_lifecycle = 0,
412 .align_mask = 0x7,
413 },
414 [kOtpPartitionLifeCycle] = {
415 .start_addr = OTP_CTRL_PARAM_LIFE_CYCLE_OFFSET,
416 .size = OTP_CTRL_PARAM_LIFE_CYCLE_SIZE,
417 .sw_readable = 0,
418 .sw_digest = 0,
419 .hw_digest = 0,
420 .digest_reg_offset = 0xdeadbeef,
421 .read_lockable = 0,
422 .lock_reg_offset = 0xdeadbeef,
423 .read_lock_bit = 0xdeadbeef,
424 .zeroizable = 0,
425 .is_lifecycle = 1,
426 .align_mask = 0x3,
427 },
428 },
429 },
430 },
431};
432
433/**
434 * Return a pointer to the `dt_otp_ctrl_desc_t` structure of the requested
435 * `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
436 * the function) with the provided default value.
437 */
438#define TRY_GET_DT(dt, default) ({ if ((dt) < (dt_otp_ctrl_t)0 || (int)(dt) >= kDtOtpCtrlCount) return (default); &otp_ctrl_desc[dt]; })
439
440dt_otp_ctrl_t dt_otp_ctrl_from_instance_id(dt_instance_id_t inst_id) {
441 if (inst_id >= kDtInstanceIdOtpCtrl && inst_id <= kDtInstanceIdOtpCtrl) {
442 return (dt_otp_ctrl_t)(inst_id - kDtInstanceIdOtpCtrl);
443 }
444 return (dt_otp_ctrl_t)0;
445}
446
451
452uint32_t dt_otp_ctrl_reg_block(
453 dt_otp_ctrl_t dt,
454 dt_otp_ctrl_reg_block_t reg_block) {
455 // Return a recognizable address in case of wrong argument.
456 return TRY_GET_DT(dt, 0xdeadbeef)->reg_addr[reg_block];
457}
458
459dt_plic_irq_id_t dt_otp_ctrl_irq_to_plic_id(
460 dt_otp_ctrl_t dt,
461 dt_otp_ctrl_irq_t irq) {
462 dt_plic_irq_id_t first_irq = TRY_GET_DT(dt, kDtPlicIrqIdNone)->first_irq;
463 if (first_irq == kDtPlicIrqIdNone) {
464 return kDtPlicIrqIdNone;
465 }
466 return (dt_plic_irq_id_t)((uint32_t)first_irq + (uint32_t)irq);
467}
468
469dt_otp_ctrl_irq_t dt_otp_ctrl_irq_from_plic_id(
470 dt_otp_ctrl_t dt,
471 dt_plic_irq_id_t irq) {
472 dt_otp_ctrl_irq_t count = kDtOtpCtrlIrqCount;
473 dt_plic_irq_id_t first_irq = TRY_GET_DT(dt, count)->first_irq;
474 if (first_irq == kDtPlicIrqIdNone) {
475 return count;
476 }
477 if (irq < first_irq || irq >= first_irq + (dt_plic_irq_id_t)count) {
478 return count;
479 }
480 return (dt_otp_ctrl_irq_t)(irq - first_irq);
481}
482
483
484dt_alert_id_t dt_otp_ctrl_alert_to_alert_id(
485 dt_otp_ctrl_t dt,
486 dt_otp_ctrl_alert_t alert) {
487 return (dt_alert_id_t)((uint32_t)otp_ctrl_desc[dt].first_alert + (uint32_t)alert);
488}
489
490dt_otp_ctrl_alert_t dt_otp_ctrl_alert_from_alert_id(
491 dt_otp_ctrl_t dt,
492 dt_alert_id_t alert) {
493 dt_otp_ctrl_alert_t count = kDtOtpCtrlAlertCount;
494 if (alert < otp_ctrl_desc[dt].first_alert || alert >= otp_ctrl_desc[dt].first_alert + (dt_alert_id_t)count) {
495 return count;
496 }
497 return (dt_otp_ctrl_alert_t)(alert - otp_ctrl_desc[dt].first_alert);
498}
499
500
501
502dt_clock_t dt_otp_ctrl_clock(
503 dt_otp_ctrl_t dt,
504 dt_otp_ctrl_clock_t clk) {
505 // Return the first clock in case of invalid argument.
506 return TRY_GET_DT(dt, (dt_clock_t)0)->clock[clk];
507}
508
509dt_reset_t dt_otp_ctrl_reset(
510 dt_otp_ctrl_t dt,
511 dt_otp_ctrl_reset_t rst) {
512 const dt_otp_ctrl_reset_t count = kDtOtpCtrlResetCount;
513 if (rst >= count) {
514 return kDtResetUnknown;
515 }
516 return TRY_GET_DT(dt, kDtResetUnknown)->reset[rst];
517}
518
519
520
521
522dt_otp_partition_info_t
523dt_otp_ctrl_partition(dt_otp_ctrl_t dt, otp_partition_t partition) {
524 dt_otp_partition_info_t invalid_part = {
525 .start_addr = 0xdeadbeef,
526 .size = 0x0,
527 .sw_readable = 0,
528 .sw_digest = 0,
529 .hw_digest = 0,
530 .digest_reg_offset = 0xdeadbeef,
531 .read_lockable = 0,
532 .lock_reg_offset = 0xdeadbeef,
533 .read_lock_bit = 0xdeadbeef,
534 .zeroizable = 0,
535 .is_lifecycle = 0,
536 .align_mask = 0x0,
537 };
538 return TRY_GET_DT(dt, invalid_part)->partitions.info[partition];
539}
540
541
542