top_dragonfly.h File Reference

Top-specific Definitions. More...

Go to the source code of this file.

Macros
#define	TOP_DRAGONFLY_UART0_BASE_ADDR   0x30010000u
	Peripheral base address for uart0 in top dragonfly.
#define	TOP_DRAGONFLY_UART0_SIZE_BYTES   0x40u
	Peripheral size for uart0 in top dragonfly.
#define	TOP_DRAGONFLY_GPIO_BASE_ADDR   0x30000000u
	Peripheral base address for gpio in top dragonfly.
#define	TOP_DRAGONFLY_GPIO_SIZE_BYTES   0x100u
	Peripheral size for gpio in top dragonfly.
#define	TOP_DRAGONFLY_SPI_DEVICE_BASE_ADDR   0x30310000u
	Peripheral base address for spi_device in top dragonfly.
#define	TOP_DRAGONFLY_SPI_DEVICE_SIZE_BYTES   0x2000u
	Peripheral size for spi_device in top dragonfly.
#define	TOP_DRAGONFLY_I2C0_BASE_ADDR   0x30080000u
	Peripheral base address for i2c0 in top dragonfly.
#define	TOP_DRAGONFLY_I2C0_SIZE_BYTES   0x80u
	Peripheral size for i2c0 in top dragonfly.
#define	TOP_DRAGONFLY_RV_TIMER_BASE_ADDR   0x30100000u
	Peripheral base address for rv_timer in top dragonfly.
#define	TOP_DRAGONFLY_RV_TIMER_SIZE_BYTES   0x200u
	Peripheral size for rv_timer in top dragonfly.
#define	TOP_DRAGONFLY_OTP_CTRL_CORE_BASE_ADDR   0x30130000u
	Peripheral base address for core device on otp_ctrl in top dragonfly.
#define	TOP_DRAGONFLY_OTP_CTRL_CORE_SIZE_BYTES   0x10000u
	Peripheral size for core device on otp_ctrl in top dragonfly.
#define	TOP_DRAGONFLY_OTP_MACRO_PRIM_BASE_ADDR   0x30140000u
	Peripheral base address for prim device on otp_macro in top dragonfly.
#define	TOP_DRAGONFLY_OTP_MACRO_PRIM_SIZE_BYTES   0x20u
	Peripheral size for prim device on otp_macro in top dragonfly.
#define	TOP_DRAGONFLY_LC_CTRL_REGS_BASE_ADDR   0x30150000u
	Peripheral base address for regs device on lc_ctrl in top dragonfly.
#define	TOP_DRAGONFLY_LC_CTRL_REGS_SIZE_BYTES   0x100u
	Peripheral size for regs device on lc_ctrl in top dragonfly.
#define	TOP_DRAGONFLY_ALERT_HANDLER_BASE_ADDR   0x30160000u
	Peripheral base address for alert_handler in top dragonfly.
#define	TOP_DRAGONFLY_ALERT_HANDLER_SIZE_BYTES   0x800u
	Peripheral size for alert_handler in top dragonfly.
#define	TOP_DRAGONFLY_SPI_HOST0_BASE_ADDR   0x30300000u
	Peripheral base address for spi_host0 in top dragonfly.
#define	TOP_DRAGONFLY_SPI_HOST0_SIZE_BYTES   0x40u
	Peripheral size for spi_host0 in top dragonfly.
#define	TOP_DRAGONFLY_PWRMGR_AON_BASE_ADDR   0x30400000u
	Peripheral base address for pwrmgr_aon in top dragonfly.
#define	TOP_DRAGONFLY_PWRMGR_AON_SIZE_BYTES   0x80u
	Peripheral size for pwrmgr_aon in top dragonfly.
#define	TOP_DRAGONFLY_RSTMGR_AON_BASE_ADDR   0x30410000u
	Peripheral base address for rstmgr_aon in top dragonfly.
#define	TOP_DRAGONFLY_RSTMGR_AON_SIZE_BYTES   0x80u
	Peripheral size for rstmgr_aon in top dragonfly.
#define	TOP_DRAGONFLY_CLKMGR_AON_BASE_ADDR   0x30420000u
	Peripheral base address for clkmgr_aon in top dragonfly.
#define	TOP_DRAGONFLY_CLKMGR_AON_SIZE_BYTES   0x40u
	Peripheral size for clkmgr_aon in top dragonfly.
#define	TOP_DRAGONFLY_PINMUX_AON_BASE_ADDR   0x30460000u
	Peripheral base address for pinmux_aon in top dragonfly.
#define	TOP_DRAGONFLY_PINMUX_AON_SIZE_BYTES   0x800u
	Peripheral size for pinmux_aon in top dragonfly.
#define	TOP_DRAGONFLY_AON_TIMER_AON_BASE_ADDR   0x30470000u
	Peripheral base address for aon_timer_aon in top dragonfly.
#define	TOP_DRAGONFLY_AON_TIMER_AON_SIZE_BYTES   0x40u
	Peripheral size for aon_timer_aon in top dragonfly.
#define	TOP_DRAGONFLY_AST_BASE_ADDR   0x30480000u
	Peripheral base address for ast in top dragonfly.
#define	TOP_DRAGONFLY_AST_SIZE_BYTES   0x400u
	Peripheral size for ast in top dragonfly.
#define	TOP_DRAGONFLY_SOC_PROXY_CORE_BASE_ADDR   0x22030000u
	Peripheral base address for core device on soc_proxy in top dragonfly.
#define	TOP_DRAGONFLY_SOC_PROXY_CORE_SIZE_BYTES   0x8u
	Peripheral size for core device on soc_proxy in top dragonfly.
#define	TOP_DRAGONFLY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR   0x30500000u
	Peripheral base address for regs device on sram_ctrl_ret_aon in top dragonfly.
#define	TOP_DRAGONFLY_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES   0x40u
	Peripheral size for regs device on sram_ctrl_ret_aon in top dragonfly.
#define	TOP_DRAGONFLY_RV_DM_REGS_BASE_ADDR   0x21200000u
	Peripheral base address for regs device on rv_dm in top dragonfly.
#define	TOP_DRAGONFLY_RV_DM_REGS_SIZE_BYTES   0x10u
	Peripheral size for regs device on rv_dm in top dragonfly.
#define	TOP_DRAGONFLY_RV_DM_MEM_BASE_ADDR   0x40000u
	Peripheral base address for mem device on rv_dm in top dragonfly.
#define	TOP_DRAGONFLY_RV_DM_MEM_SIZE_BYTES   0x1000u
	Peripheral size for mem device on rv_dm in top dragonfly.
#define	TOP_DRAGONFLY_RV_PLIC_BASE_ADDR   0x28000000u
	Peripheral base address for rv_plic in top dragonfly.
#define	TOP_DRAGONFLY_RV_PLIC_SIZE_BYTES   0x8000000u
	Peripheral size for rv_plic in top dragonfly.
#define	TOP_DRAGONFLY_ACC_BASE_ADDR   0x22100000u
	Peripheral base address for acc in top dragonfly.
#define	TOP_DRAGONFLY_ACC_SIZE_BYTES   0x20000u
	Peripheral size for acc in top dragonfly.
#define	TOP_DRAGONFLY_AES_BASE_ADDR   0x21100000u
	Peripheral base address for aes in top dragonfly.
#define	TOP_DRAGONFLY_AES_SIZE_BYTES   0x100u
	Peripheral size for aes in top dragonfly.
#define	TOP_DRAGONFLY_HMAC_BASE_ADDR   0x21110000u
	Peripheral base address for hmac in top dragonfly.
#define	TOP_DRAGONFLY_HMAC_SIZE_BYTES   0x2000u
	Peripheral size for hmac in top dragonfly.
#define	TOP_DRAGONFLY_KMAC_BASE_ADDR   0x21120000u
	Peripheral base address for kmac in top dragonfly.
#define	TOP_DRAGONFLY_KMAC_SIZE_BYTES   0x1000u
	Peripheral size for kmac in top dragonfly.
#define	TOP_DRAGONFLY_KEYMGR_DPE_BASE_ADDR   0x21140000u
	Peripheral base address for keymgr_dpe in top dragonfly.
#define	TOP_DRAGONFLY_KEYMGR_DPE_SIZE_BYTES   0x100u
	Peripheral size for keymgr_dpe in top dragonfly.
#define	TOP_DRAGONFLY_CSRNG_BASE_ADDR   0x21150000u
	Peripheral base address for csrng in top dragonfly.
#define	TOP_DRAGONFLY_CSRNG_SIZE_BYTES   0x80u
	Peripheral size for csrng in top dragonfly.
#define	TOP_DRAGONFLY_ENTROPY_SRC_BASE_ADDR   0x21160000u
	Peripheral base address for entropy_src in top dragonfly.
#define	TOP_DRAGONFLY_ENTROPY_SRC_SIZE_BYTES   0x100u
	Peripheral size for entropy_src in top dragonfly.
#define	TOP_DRAGONFLY_EDN0_BASE_ADDR   0x21170000u
	Peripheral base address for edn0 in top dragonfly.
#define	TOP_DRAGONFLY_EDN0_SIZE_BYTES   0x80u
	Peripheral size for edn0 in top dragonfly.
#define	TOP_DRAGONFLY_EDN1_BASE_ADDR   0x21180000u
	Peripheral base address for edn1 in top dragonfly.
#define	TOP_DRAGONFLY_EDN1_SIZE_BYTES   0x80u
	Peripheral size for edn1 in top dragonfly.
#define	TOP_DRAGONFLY_SRAM_CTRL_MAIN_REGS_BASE_ADDR   0x211C0000u
	Peripheral base address for regs device on sram_ctrl_main in top dragonfly.
#define	TOP_DRAGONFLY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES   0x40u
	Peripheral size for regs device on sram_ctrl_main in top dragonfly.
#define	TOP_DRAGONFLY_SRAM_CTRL_MBOX_REGS_BASE_ADDR   0x211D0000u
	Peripheral base address for regs device on sram_ctrl_mbox in top dragonfly.
#define	TOP_DRAGONFLY_SRAM_CTRL_MBOX_REGS_SIZE_BYTES   0x40u
	Peripheral size for regs device on sram_ctrl_mbox in top dragonfly.
#define	TOP_DRAGONFLY_ROM_CTRL0_REGS_BASE_ADDR   0x211E0000u
	Peripheral base address for regs device on rom_ctrl0 in top dragonfly.
#define	TOP_DRAGONFLY_ROM_CTRL0_REGS_SIZE_BYTES   0x80u
	Peripheral size for regs device on rom_ctrl0 in top dragonfly.
#define	TOP_DRAGONFLY_ROM_CTRL1_REGS_BASE_ADDR   0x211E1000u
	Peripheral base address for regs device on rom_ctrl1 in top dragonfly.
#define	TOP_DRAGONFLY_ROM_CTRL1_REGS_SIZE_BYTES   0x80u
	Peripheral size for regs device on rom_ctrl1 in top dragonfly.
#define	TOP_DRAGONFLY_DMA_BASE_ADDR   0x22010000u
	Peripheral base address for dma in top dragonfly.
#define	TOP_DRAGONFLY_DMA_SIZE_BYTES   0x200u
	Peripheral size for dma in top dragonfly.
#define	TOP_DRAGONFLY_MBX0_CORE_BASE_ADDR   0x22000000u
	Peripheral base address for core device on mbx0 in top dragonfly.
#define	TOP_DRAGONFLY_MBX0_CORE_SIZE_BYTES   0x80u
	Peripheral size for core device on mbx0 in top dragonfly.
#define	TOP_DRAGONFLY_MBX1_CORE_BASE_ADDR   0x22000100u
	Peripheral base address for core device on mbx1 in top dragonfly.
#define	TOP_DRAGONFLY_MBX1_CORE_SIZE_BYTES   0x80u
	Peripheral size for core device on mbx1 in top dragonfly.
#define	TOP_DRAGONFLY_MBX2_CORE_BASE_ADDR   0x22000200u
	Peripheral base address for core device on mbx2 in top dragonfly.
#define	TOP_DRAGONFLY_MBX2_CORE_SIZE_BYTES   0x80u
	Peripheral size for core device on mbx2 in top dragonfly.
#define	TOP_DRAGONFLY_MBX3_CORE_BASE_ADDR   0x22000300u
	Peripheral base address for core device on mbx3 in top dragonfly.
#define	TOP_DRAGONFLY_MBX3_CORE_SIZE_BYTES   0x80u
	Peripheral size for core device on mbx3 in top dragonfly.
#define	TOP_DRAGONFLY_MBX4_CORE_BASE_ADDR   0x22000400u
	Peripheral base address for core device on mbx4 in top dragonfly.
#define	TOP_DRAGONFLY_MBX4_CORE_SIZE_BYTES   0x80u
	Peripheral size for core device on mbx4 in top dragonfly.
#define	TOP_DRAGONFLY_MBX5_CORE_BASE_ADDR   0x22000500u
	Peripheral base address for core device on mbx5 in top dragonfly.
#define	TOP_DRAGONFLY_MBX5_CORE_SIZE_BYTES   0x80u
	Peripheral size for core device on mbx5 in top dragonfly.
#define	TOP_DRAGONFLY_MBX6_CORE_BASE_ADDR   0x22000600u
	Peripheral base address for core device on mbx6 in top dragonfly.
#define	TOP_DRAGONFLY_MBX6_CORE_SIZE_BYTES   0x80u
	Peripheral size for core device on mbx6 in top dragonfly.
#define	TOP_DRAGONFLY_MBX_JTAG_CORE_BASE_ADDR   0x22000800u
	Peripheral base address for core device on mbx_jtag in top dragonfly.
#define	TOP_DRAGONFLY_MBX_JTAG_CORE_SIZE_BYTES   0x80u
	Peripheral size for core device on mbx_jtag in top dragonfly.
#define	TOP_DRAGONFLY_MBX_PCIE0_CORE_BASE_ADDR   0x22040000u
	Peripheral base address for core device on mbx_pcie0 in top dragonfly.
#define	TOP_DRAGONFLY_MBX_PCIE0_CORE_SIZE_BYTES   0x80u
	Peripheral size for core device on mbx_pcie0 in top dragonfly.
#define	TOP_DRAGONFLY_MBX_PCIE1_CORE_BASE_ADDR   0x22040100u
	Peripheral base address for core device on mbx_pcie1 in top dragonfly.
#define	TOP_DRAGONFLY_MBX_PCIE1_CORE_SIZE_BYTES   0x80u
	Peripheral size for core device on mbx_pcie1 in top dragonfly.
#define	TOP_DRAGONFLY_SOC_DBG_CTRL_CORE_BASE_ADDR   0x30170000u
	Peripheral base address for core device on soc_dbg_ctrl in top dragonfly.
#define	TOP_DRAGONFLY_SOC_DBG_CTRL_CORE_SIZE_BYTES   0x20u
	Peripheral size for core device on soc_dbg_ctrl in top dragonfly.
#define	TOP_DRAGONFLY_RV_CORE_IBEX_CFG_BASE_ADDR   0x211F0000u
	Peripheral base address for cfg device on rv_core_ibex in top dragonfly.
#define	TOP_DRAGONFLY_RV_CORE_IBEX_CFG_SIZE_BYTES   0x800u
	Peripheral size for cfg device on rv_core_ibex in top dragonfly.
#define	TOP_DRAGONFLY_SOC_PROXY_CTN_BASE_ADDR   0x40000000u
	Memory base address for ctn memory on soc_proxy in top dragonfly.
#define	TOP_DRAGONFLY_SOC_PROXY_CTN_SIZE_BYTES   0x80000000u
	Memory size for ctn memory on soc_proxy in top dragonfly.
#define	TOP_DRAGONFLY_SOC_PROXY_RAM_CTN_BASE_ADDR   0x41000000u
	Memory base address for ram_ctn in top dragonfly.
#define	TOP_DRAGONFLY_SOC_PROXY_RAM_CTN_SIZE_BYTES   0x100000u
	Memory size for ram_ctn in top dragonfly.
#define	TOP_DRAGONFLY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR   0x30600000u
	Memory base address for ram memory on sram_ctrl_ret_aon in top dragonfly.
#define	TOP_DRAGONFLY_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES   0x1000u
	Memory size for ram memory on sram_ctrl_ret_aon in top dragonfly.
#define	TOP_DRAGONFLY_SRAM_CTRL_MAIN_RAM_BASE_ADDR   0x10000000u
	Memory base address for ram memory on sram_ctrl_main in top dragonfly.
#define	TOP_DRAGONFLY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES   0x10000u
	Memory size for ram memory on sram_ctrl_main in top dragonfly.
#define	TOP_DRAGONFLY_SRAM_CTRL_MBOX_RAM_BASE_ADDR   0x11000000u
	Memory base address for ram memory on sram_ctrl_mbox in top dragonfly.
#define	TOP_DRAGONFLY_SRAM_CTRL_MBOX_RAM_SIZE_BYTES   0x1000u
	Memory size for ram memory on sram_ctrl_mbox in top dragonfly.
#define	TOP_DRAGONFLY_ROM_CTRL0_ROM_BASE_ADDR   0x8000u
	Memory base address for rom memory on rom_ctrl0 in top dragonfly.
#define	TOP_DRAGONFLY_ROM_CTRL0_ROM_SIZE_BYTES   0x8000u
	Memory size for rom memory on rom_ctrl0 in top dragonfly.
#define	TOP_DRAGONFLY_ROM_CTRL1_ROM_BASE_ADDR   0x20000u
	Memory base address for rom memory on rom_ctrl1 in top dragonfly.
#define	TOP_DRAGONFLY_ROM_CTRL1_ROM_SIZE_BYTES   0x10000u
	Memory size for rom memory on rom_ctrl1 in top dragonfly.
#define	PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET   2
#define	NUM_MIO_PADS   12
#define	NUM_DIO_PADS   73
#define	PINMUX_PERIPH_OUTSEL_IDX_OFFSET   3
#define	TOP_DRAGONFLY_MMIO_BASE_ADDR   0x21100000u
	MMIO Region.
#define	TOP_DRAGONFLY_MMIO_SIZE_BYTES   0xF501000u

Typedefs
typedef enum top_dragonfly_plic_peripheral	top_dragonfly_plic_peripheral_t
	PLIC Interrupt Source Peripheral.
typedef enum top_dragonfly_plic_irq_id	top_dragonfly_plic_irq_id_t
	PLIC Interrupt Source.
typedef enum top_dragonfly_plic_target	top_dragonfly_plic_target_t
	PLIC Interrupt Target.
typedef enum top_dragonfly_alert_peripheral	top_dragonfly_alert_peripheral_t
	Alert Handler Source Peripheral.
typedef enum top_dragonfly_alert_id	top_dragonfly_alert_id_t
	Alert Handler Alert Source.
typedef enum top_dragonfly_pinmux_peripheral_in	top_dragonfly_pinmux_peripheral_in_t
	Pinmux Peripheral Input.
typedef enum top_dragonfly_pinmux_insel	top_dragonfly_pinmux_insel_t
	Pinmux MIO Input Selector.
typedef enum top_dragonfly_pinmux_mio_out	top_dragonfly_pinmux_mio_out_t
	Pinmux MIO Output.
typedef enum top_dragonfly_pinmux_outsel	top_dragonfly_pinmux_outsel_t
	Pinmux Peripheral Output Selector.
typedef enum top_dragonfly_direct_pads	top_dragonfly_direct_pads_t
	Dedicated Pad Selects.
typedef enum top_dragonfly_muxed_pads	top_dragonfly_muxed_pads_t
	Muxed Pad Selects.
typedef enum top_dragonfly_power_manager_wake_ups	top_dragonfly_power_manager_wake_ups_t
	Power Manager Wakeup Signals.
typedef enum top_dragonfly_reset_manager_sw_resets	top_dragonfly_reset_manager_sw_resets_t
	Reset Manager Software Controlled Resets.
typedef enum top_dragonfly_power_manager_reset_requests	top_dragonfly_power_manager_reset_requests_t
	Power Manager Reset Request Signals.
typedef enum top_dragonfly_gateable_clocks	top_dragonfly_gateable_clocks_t
	Clock Manager Software-Controlled ("Gated") Clocks.
typedef enum top_dragonfly_hintable_clocks	top_dragonfly_hintable_clocks_t
	Clock Manager Software-Hinted Clocks.

Enumerations
enum	top_dragonfly_plic_peripheral {   kTopDragonflyPlicPeripheralUnknown = 0 ,   kTopDragonflyPlicPeripheralUart0 = 1 ,   kTopDragonflyPlicPeripheralGpio = 2 ,   kTopDragonflyPlicPeripheralSpiDevice = 3 ,   kTopDragonflyPlicPeripheralI2c0 = 4 ,   kTopDragonflyPlicPeripheralRvTimer = 5 ,   kTopDragonflyPlicPeripheralOtpCtrl = 6 ,   kTopDragonflyPlicPeripheralAlertHandler = 7 ,   kTopDragonflyPlicPeripheralSpiHost0 = 8 ,   kTopDragonflyPlicPeripheralPwrmgrAon = 9 ,   kTopDragonflyPlicPeripheralAonTimerAon = 10 ,   kTopDragonflyPlicPeripheralAcc = 11 ,   kTopDragonflyPlicPeripheralHmac = 12 ,   kTopDragonflyPlicPeripheralKmac = 13 ,   kTopDragonflyPlicPeripheralKeymgrDpe = 14 ,   kTopDragonflyPlicPeripheralCsrng = 15 ,   kTopDragonflyPlicPeripheralEntropySrc = 16 ,   kTopDragonflyPlicPeripheralEdn0 = 17 ,   kTopDragonflyPlicPeripheralEdn1 = 18 ,   kTopDragonflyPlicPeripheralDma = 19 ,   kTopDragonflyPlicPeripheralMbx0 = 20 ,   kTopDragonflyPlicPeripheralMbx1 = 21 ,   kTopDragonflyPlicPeripheralMbx2 = 22 ,   kTopDragonflyPlicPeripheralMbx3 = 23 ,   kTopDragonflyPlicPeripheralMbx4 = 24 ,   kTopDragonflyPlicPeripheralMbx5 = 25 ,   kTopDragonflyPlicPeripheralMbx6 = 26 ,   kTopDragonflyPlicPeripheralMbxJtag = 27 ,   kTopDragonflyPlicPeripheralMbxPcie0 = 28 ,   kTopDragonflyPlicPeripheralMbxPcie1 = 29 ,   kTopDragonflyPlicPeripheralRaclCtrl = 30 ,   kTopDragonflyPlicPeripheralAcRangeCheck = 31 ,   kTopDragonflyPlicPeripheralLast = 31 }
	PLIC Interrupt Source Peripheral. More...
enum	top_dragonfly_plic_irq_id {   kTopDragonflyPlicIrqIdNone = 0 ,   kTopDragonflyPlicIrqIdUart0TxWatermark = 1 ,   kTopDragonflyPlicIrqIdUart0RxWatermark = 2 ,   kTopDragonflyPlicIrqIdUart0TxDone = 3 ,   kTopDragonflyPlicIrqIdUart0RxOverflow = 4 ,   kTopDragonflyPlicIrqIdUart0RxFrameErr = 5 ,   kTopDragonflyPlicIrqIdUart0RxBreakErr = 6 ,   kTopDragonflyPlicIrqIdUart0RxTimeout = 7 ,   kTopDragonflyPlicIrqIdUart0RxParityErr = 8 ,   kTopDragonflyPlicIrqIdUart0TxEmpty = 9 ,   kTopDragonflyPlicIrqIdGpioGpio0 = 10 ,   kTopDragonflyPlicIrqIdGpioGpio1 = 11 ,   kTopDragonflyPlicIrqIdGpioGpio2 = 12 ,   kTopDragonflyPlicIrqIdGpioGpio3 = 13 ,   kTopDragonflyPlicIrqIdGpioGpio4 = 14 ,   kTopDragonflyPlicIrqIdGpioGpio5 = 15 ,   kTopDragonflyPlicIrqIdGpioGpio6 = 16 ,   kTopDragonflyPlicIrqIdGpioGpio7 = 17 ,   kTopDragonflyPlicIrqIdGpioGpio8 = 18 ,   kTopDragonflyPlicIrqIdGpioGpio9 = 19 ,   kTopDragonflyPlicIrqIdGpioGpio10 = 20 ,   kTopDragonflyPlicIrqIdGpioGpio11 = 21 ,   kTopDragonflyPlicIrqIdGpioGpio12 = 22 ,   kTopDragonflyPlicIrqIdGpioGpio13 = 23 ,   kTopDragonflyPlicIrqIdGpioGpio14 = 24 ,   kTopDragonflyPlicIrqIdGpioGpio15 = 25 ,   kTopDragonflyPlicIrqIdGpioGpio16 = 26 ,   kTopDragonflyPlicIrqIdGpioGpio17 = 27 ,   kTopDragonflyPlicIrqIdGpioGpio18 = 28 ,   kTopDragonflyPlicIrqIdGpioGpio19 = 29 ,   kTopDragonflyPlicIrqIdGpioGpio20 = 30 ,   kTopDragonflyPlicIrqIdGpioGpio21 = 31 ,   kTopDragonflyPlicIrqIdGpioGpio22 = 32 ,   kTopDragonflyPlicIrqIdGpioGpio23 = 33 ,   kTopDragonflyPlicIrqIdGpioGpio24 = 34 ,   kTopDragonflyPlicIrqIdGpioGpio25 = 35 ,   kTopDragonflyPlicIrqIdGpioGpio26 = 36 ,   kTopDragonflyPlicIrqIdGpioGpio27 = 37 ,   kTopDragonflyPlicIrqIdGpioGpio28 = 38 ,   kTopDragonflyPlicIrqIdGpioGpio29 = 39 ,   kTopDragonflyPlicIrqIdGpioGpio30 = 40 ,   kTopDragonflyPlicIrqIdGpioGpio31 = 41 ,   kTopDragonflyPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty = 42 ,   kTopDragonflyPlicIrqIdSpiDeviceUploadPayloadNotEmpty = 43 ,   kTopDragonflyPlicIrqIdSpiDeviceUploadPayloadOverflow = 44 ,   kTopDragonflyPlicIrqIdSpiDeviceReadbufWatermark = 45 ,   kTopDragonflyPlicIrqIdSpiDeviceReadbufFlip = 46 ,   kTopDragonflyPlicIrqIdSpiDeviceTpmHeaderNotEmpty = 47 ,   kTopDragonflyPlicIrqIdSpiDeviceTpmRdfifoCmdEnd = 48 ,   kTopDragonflyPlicIrqIdSpiDeviceTpmRdfifoDrop = 49 ,   kTopDragonflyPlicIrqIdI2c0FmtThreshold = 50 ,   kTopDragonflyPlicIrqIdI2c0RxThreshold = 51 ,   kTopDragonflyPlicIrqIdI2c0AcqThreshold = 52 ,   kTopDragonflyPlicIrqIdI2c0RxOverflow = 53 ,   kTopDragonflyPlicIrqIdI2c0ControllerHalt = 54 ,   kTopDragonflyPlicIrqIdI2c0SclInterference = 55 ,   kTopDragonflyPlicIrqIdI2c0SdaInterference = 56 ,   kTopDragonflyPlicIrqIdI2c0StretchTimeout = 57 ,   kTopDragonflyPlicIrqIdI2c0SdaUnstable = 58 ,   kTopDragonflyPlicIrqIdI2c0CmdComplete = 59 ,   kTopDragonflyPlicIrqIdI2c0TxStretch = 60 ,   kTopDragonflyPlicIrqIdI2c0TxThreshold = 61 ,   kTopDragonflyPlicIrqIdI2c0AcqStretch = 62 ,   kTopDragonflyPlicIrqIdI2c0UnexpStop = 63 ,   kTopDragonflyPlicIrqIdI2c0HostTimeout = 64 ,   kTopDragonflyPlicIrqIdRvTimerTimerExpiredHart0Timer0 = 65 ,   kTopDragonflyPlicIrqIdOtpCtrlOtpOperationDone = 66 ,   kTopDragonflyPlicIrqIdOtpCtrlOtpError = 67 ,   kTopDragonflyPlicIrqIdAlertHandlerClassa = 68 ,   kTopDragonflyPlicIrqIdAlertHandlerClassb = 69 ,   kTopDragonflyPlicIrqIdAlertHandlerClassc = 70 ,   kTopDragonflyPlicIrqIdAlertHandlerClassd = 71 ,   kTopDragonflyPlicIrqIdSpiHost0Error = 72 ,   kTopDragonflyPlicIrqIdSpiHost0SpiEvent = 73 ,   kTopDragonflyPlicIrqIdPwrmgrAonWakeup = 74 ,   kTopDragonflyPlicIrqIdAonTimerAonWkupTimerExpired = 75 ,   kTopDragonflyPlicIrqIdAonTimerAonWdogTimerBark = 76 ,   kTopDragonflyPlicIrqIdAccDone = 77 ,   kTopDragonflyPlicIrqIdHmacHmacDone = 78 ,   kTopDragonflyPlicIrqIdHmacFifoEmpty = 79 ,   kTopDragonflyPlicIrqIdHmacHmacErr = 80 ,   kTopDragonflyPlicIrqIdKmacKmacDone = 81 ,   kTopDragonflyPlicIrqIdKmacFifoEmpty = 82 ,   kTopDragonflyPlicIrqIdKmacKmacErr = 83 ,   kTopDragonflyPlicIrqIdKeymgrDpeOpDone = 84 ,   kTopDragonflyPlicIrqIdCsrngCsCmdReqDone = 85 ,   kTopDragonflyPlicIrqIdCsrngCsEntropyReq = 86 ,   kTopDragonflyPlicIrqIdCsrngCsHwInstExc = 87 ,   kTopDragonflyPlicIrqIdCsrngCsFatalErr = 88 ,   kTopDragonflyPlicIrqIdEntropySrcEsEntropyValid = 89 ,   kTopDragonflyPlicIrqIdEntropySrcEsHealthTestFailed = 90 ,   kTopDragonflyPlicIrqIdEntropySrcEsObserveFifoReady = 91 ,   kTopDragonflyPlicIrqIdEntropySrcEsFatalErr = 92 ,   kTopDragonflyPlicIrqIdEdn0EdnCmdReqDone = 93 ,   kTopDragonflyPlicIrqIdEdn0EdnFatalErr = 94 ,   kTopDragonflyPlicIrqIdEdn1EdnCmdReqDone = 95 ,   kTopDragonflyPlicIrqIdEdn1EdnFatalErr = 96 ,   kTopDragonflyPlicIrqIdDmaDmaDone = 97 ,   kTopDragonflyPlicIrqIdDmaDmaChunkDone = 98 ,   kTopDragonflyPlicIrqIdDmaDmaError = 99 ,   kTopDragonflyPlicIrqIdMbx0MbxReady = 100 ,   kTopDragonflyPlicIrqIdMbx0MbxAbort = 101 ,   kTopDragonflyPlicIrqIdMbx0MbxError = 102 ,   kTopDragonflyPlicIrqIdMbx1MbxReady = 103 ,   kTopDragonflyPlicIrqIdMbx1MbxAbort = 104 ,   kTopDragonflyPlicIrqIdMbx1MbxError = 105 ,   kTopDragonflyPlicIrqIdMbx2MbxReady = 106 ,   kTopDragonflyPlicIrqIdMbx2MbxAbort = 107 ,   kTopDragonflyPlicIrqIdMbx2MbxError = 108 ,   kTopDragonflyPlicIrqIdMbx3MbxReady = 109 ,   kTopDragonflyPlicIrqIdMbx3MbxAbort = 110 ,   kTopDragonflyPlicIrqIdMbx3MbxError = 111 ,   kTopDragonflyPlicIrqIdMbx4MbxReady = 112 ,   kTopDragonflyPlicIrqIdMbx4MbxAbort = 113 ,   kTopDragonflyPlicIrqIdMbx4MbxError = 114 ,   kTopDragonflyPlicIrqIdMbx5MbxReady = 115 ,   kTopDragonflyPlicIrqIdMbx5MbxAbort = 116 ,   kTopDragonflyPlicIrqIdMbx5MbxError = 117 ,   kTopDragonflyPlicIrqIdMbx6MbxReady = 118 ,   kTopDragonflyPlicIrqIdMbx6MbxAbort = 119 ,   kTopDragonflyPlicIrqIdMbx6MbxError = 120 ,   kTopDragonflyPlicIrqIdMbxJtagMbxReady = 121 ,   kTopDragonflyPlicIrqIdMbxJtagMbxAbort = 122 ,   kTopDragonflyPlicIrqIdMbxJtagMbxError = 123 ,   kTopDragonflyPlicIrqIdMbxPcie0MbxReady = 124 ,   kTopDragonflyPlicIrqIdMbxPcie0MbxAbort = 125 ,   kTopDragonflyPlicIrqIdMbxPcie0MbxError = 126 ,   kTopDragonflyPlicIrqIdMbxPcie1MbxReady = 127 ,   kTopDragonflyPlicIrqIdMbxPcie1MbxAbort = 128 ,   kTopDragonflyPlicIrqIdMbxPcie1MbxError = 129 ,   kTopDragonflyPlicIrqIdRaclCtrlRaclError = 130 ,   kTopDragonflyPlicIrqIdAcRangeCheckDenyCntReached = 131 ,   kTopDragonflyPlicIrqIdLast = 131 }
	PLIC Interrupt Source. More...
enum	top_dragonfly_plic_target {   kTopDragonflyPlicTargetIbex0 = 0 ,   kTopDragonflyPlicTargetLast = 0 }
	PLIC Interrupt Target. More...
enum	top_dragonfly_alert_peripheral {   kTopDragonflyAlertPeripheralExternal = 0 ,   kTopDragonflyAlertPeripheralUart0 = 1 ,   kTopDragonflyAlertPeripheralGpio = 2 ,   kTopDragonflyAlertPeripheralSpiDevice = 3 ,   kTopDragonflyAlertPeripheralI2c0 = 4 ,   kTopDragonflyAlertPeripheralRvTimer = 5 ,   kTopDragonflyAlertPeripheralOtpCtrl = 6 ,   kTopDragonflyAlertPeripheralLcCtrl = 7 ,   kTopDragonflyAlertPeripheralSpiHost0 = 8 ,   kTopDragonflyAlertPeripheralPwrmgrAon = 9 ,   kTopDragonflyAlertPeripheralRstmgrAon = 10 ,   kTopDragonflyAlertPeripheralClkmgrAon = 11 ,   kTopDragonflyAlertPeripheralPinmuxAon = 12 ,   kTopDragonflyAlertPeripheralAonTimerAon = 13 ,   kTopDragonflyAlertPeripheralSocProxy = 14 ,   kTopDragonflyAlertPeripheralSramCtrlRetAon = 15 ,   kTopDragonflyAlertPeripheralRvDm = 16 ,   kTopDragonflyAlertPeripheralRvPlic = 17 ,   kTopDragonflyAlertPeripheralAcc = 18 ,   kTopDragonflyAlertPeripheralAes = 19 ,   kTopDragonflyAlertPeripheralHmac = 20 ,   kTopDragonflyAlertPeripheralKmac = 21 ,   kTopDragonflyAlertPeripheralKeymgrDpe = 22 ,   kTopDragonflyAlertPeripheralCsrng = 23 ,   kTopDragonflyAlertPeripheralEntropySrc = 24 ,   kTopDragonflyAlertPeripheralEdn0 = 25 ,   kTopDragonflyAlertPeripheralEdn1 = 26 ,   kTopDragonflyAlertPeripheralSramCtrlMain = 27 ,   kTopDragonflyAlertPeripheralSramCtrlMbox = 28 ,   kTopDragonflyAlertPeripheralRomCtrl0 = 29 ,   kTopDragonflyAlertPeripheralRomCtrl1 = 30 ,   kTopDragonflyAlertPeripheralDma = 31 ,   kTopDragonflyAlertPeripheralMbx0 = 32 ,   kTopDragonflyAlertPeripheralMbx1 = 33 ,   kTopDragonflyAlertPeripheralMbx2 = 34 ,   kTopDragonflyAlertPeripheralMbx3 = 35 ,   kTopDragonflyAlertPeripheralMbx4 = 36 ,   kTopDragonflyAlertPeripheralMbx5 = 37 ,   kTopDragonflyAlertPeripheralMbx6 = 38 ,   kTopDragonflyAlertPeripheralMbxJtag = 39 ,   kTopDragonflyAlertPeripheralMbxPcie0 = 40 ,   kTopDragonflyAlertPeripheralMbxPcie1 = 41 ,   kTopDragonflyAlertPeripheralSocDbgCtrl = 42 ,   kTopDragonflyAlertPeripheralRaclCtrl = 43 ,   kTopDragonflyAlertPeripheralAcRangeCheck = 44 ,   kTopDragonflyAlertPeripheralRvCoreIbex = 45 ,   kTopDragonflyAlertPeripheralLast = 45 }
	Alert Handler Source Peripheral. More...
enum	top_dragonfly_alert_id {   kTopDragonflyAlertIdUart0FatalFault = 0 ,   kTopDragonflyAlertIdGpioFatalFault = 1 ,   kTopDragonflyAlertIdSpiDeviceFatalFault = 2 ,   kTopDragonflyAlertIdI2c0FatalFault = 3 ,   kTopDragonflyAlertIdRvTimerFatalFault = 4 ,   kTopDragonflyAlertIdOtpCtrlFatalMacroError = 5 ,   kTopDragonflyAlertIdOtpCtrlFatalCheckError = 6 ,   kTopDragonflyAlertIdOtpCtrlFatalBusIntegError = 7 ,   kTopDragonflyAlertIdOtpCtrlFatalPrimOtpAlert = 8 ,   kTopDragonflyAlertIdOtpCtrlRecovPrimOtpAlert = 9 ,   kTopDragonflyAlertIdLcCtrlFatalProgError = 10 ,   kTopDragonflyAlertIdLcCtrlFatalStateError = 11 ,   kTopDragonflyAlertIdLcCtrlFatalBusIntegError = 12 ,   kTopDragonflyAlertIdSpiHost0FatalFault = 13 ,   kTopDragonflyAlertIdPwrmgrAonFatalFault = 14 ,   kTopDragonflyAlertIdRstmgrAonFatalFault = 15 ,   kTopDragonflyAlertIdRstmgrAonFatalCnstyFault = 16 ,   kTopDragonflyAlertIdClkmgrAonRecovFault = 17 ,   kTopDragonflyAlertIdClkmgrAonFatalFault = 18 ,   kTopDragonflyAlertIdPinmuxAonFatalFault = 19 ,   kTopDragonflyAlertIdAonTimerAonFatalFault = 20 ,   kTopDragonflyAlertIdSocProxyFatalAlertIntg = 21 ,   kTopDragonflyAlertIdSramCtrlRetAonFatalError = 22 ,   kTopDragonflyAlertIdRvDmFatalFault = 23 ,   kTopDragonflyAlertIdRvPlicFatalFault = 24 ,   kTopDragonflyAlertIdAccFatal = 25 ,   kTopDragonflyAlertIdAccRecov = 26 ,   kTopDragonflyAlertIdAesRecovCtrlUpdateErr = 27 ,   kTopDragonflyAlertIdAesFatalFault = 28 ,   kTopDragonflyAlertIdHmacFatalFault = 29 ,   kTopDragonflyAlertIdKmacRecovOperationErr = 30 ,   kTopDragonflyAlertIdKmacFatalFaultErr = 31 ,   kTopDragonflyAlertIdKeymgrDpeRecovOperationErr = 32 ,   kTopDragonflyAlertIdKeymgrDpeFatalFaultErr = 33 ,   kTopDragonflyAlertIdCsrngRecovAlert = 34 ,   kTopDragonflyAlertIdCsrngFatalAlert = 35 ,   kTopDragonflyAlertIdEntropySrcRecovAlert = 36 ,   kTopDragonflyAlertIdEntropySrcFatalAlert = 37 ,   kTopDragonflyAlertIdEdn0RecovAlert = 38 ,   kTopDragonflyAlertIdEdn0FatalAlert = 39 ,   kTopDragonflyAlertIdEdn1RecovAlert = 40 ,   kTopDragonflyAlertIdEdn1FatalAlert = 41 ,   kTopDragonflyAlertIdSramCtrlMainFatalError = 42 ,   kTopDragonflyAlertIdSramCtrlMboxFatalError = 43 ,   kTopDragonflyAlertIdRomCtrl0Fatal = 44 ,   kTopDragonflyAlertIdRomCtrl1Fatal = 45 ,   kTopDragonflyAlertIdDmaFatalFault = 46 ,   kTopDragonflyAlertIdMbx0FatalFault = 47 ,   kTopDragonflyAlertIdMbx0RecovFault = 48 ,   kTopDragonflyAlertIdMbx1FatalFault = 49 ,   kTopDragonflyAlertIdMbx1RecovFault = 50 ,   kTopDragonflyAlertIdMbx2FatalFault = 51 ,   kTopDragonflyAlertIdMbx2RecovFault = 52 ,   kTopDragonflyAlertIdMbx3FatalFault = 53 ,   kTopDragonflyAlertIdMbx3RecovFault = 54 ,   kTopDragonflyAlertIdMbx4FatalFault = 55 ,   kTopDragonflyAlertIdMbx4RecovFault = 56 ,   kTopDragonflyAlertIdMbx5FatalFault = 57 ,   kTopDragonflyAlertIdMbx5RecovFault = 58 ,   kTopDragonflyAlertIdMbx6FatalFault = 59 ,   kTopDragonflyAlertIdMbx6RecovFault = 60 ,   kTopDragonflyAlertIdMbxJtagFatalFault = 61 ,   kTopDragonflyAlertIdMbxJtagRecovFault = 62 ,   kTopDragonflyAlertIdMbxPcie0FatalFault = 63 ,   kTopDragonflyAlertIdMbxPcie0RecovFault = 64 ,   kTopDragonflyAlertIdMbxPcie1FatalFault = 65 ,   kTopDragonflyAlertIdMbxPcie1RecovFault = 66 ,   kTopDragonflyAlertIdSocDbgCtrlFatalFault = 67 ,   kTopDragonflyAlertIdSocDbgCtrlRecovCtrlUpdateErr = 68 ,   kTopDragonflyAlertIdRaclCtrlFatalFault = 69 ,   kTopDragonflyAlertIdRaclCtrlRecovCtrlUpdateErr = 70 ,   kTopDragonflyAlertIdAcRangeCheckRecovCtrlUpdateErr = 71 ,   kTopDragonflyAlertIdAcRangeCheckFatalFault = 72 ,   kTopDragonflyAlertIdRvCoreIbexFatalSwErr = 73 ,   kTopDragonflyAlertIdRvCoreIbexRecovSwErr = 74 ,   kTopDragonflyAlertIdRvCoreIbexFatalHwErr = 75 ,   kTopDragonflyAlertIdRvCoreIbexRecovHwErr = 76 ,   kTopDragonflyAlertIdLast = 76 }
	Alert Handler Alert Source. More...
enum	top_dragonfly_pinmux_peripheral_in {   kTopDragonflyPinmuxPeripheralInSocProxySocGpi12 = 0 ,   kTopDragonflyPinmuxPeripheralInSocProxySocGpi13 = 1 ,   kTopDragonflyPinmuxPeripheralInSocProxySocGpi14 = 2 ,   kTopDragonflyPinmuxPeripheralInSocProxySocGpi15 = 3 ,   kTopDragonflyPinmuxPeripheralInLast = 3 }
	Pinmux Peripheral Input. More...
enum	top_dragonfly_pinmux_insel {   kTopDragonflyPinmuxInselConstantZero = 0 ,   kTopDragonflyPinmuxInselConstantOne = 1 ,   kTopDragonflyPinmuxInselMio0 = 2 ,   kTopDragonflyPinmuxInselMio1 = 3 ,   kTopDragonflyPinmuxInselMio2 = 4 ,   kTopDragonflyPinmuxInselMio3 = 5 ,   kTopDragonflyPinmuxInselMio4 = 6 ,   kTopDragonflyPinmuxInselMio5 = 7 ,   kTopDragonflyPinmuxInselMio6 = 8 ,   kTopDragonflyPinmuxInselMio7 = 9 ,   kTopDragonflyPinmuxInselMio8 = 10 ,   kTopDragonflyPinmuxInselMio9 = 11 ,   kTopDragonflyPinmuxInselMio10 = 12 ,   kTopDragonflyPinmuxInselMio11 = 13 ,   kTopDragonflyPinmuxInselLast = 13 }
	Pinmux MIO Input Selector. More...
enum	top_dragonfly_pinmux_mio_out {   kTopDragonflyPinmuxMioOutMio0 = 0 ,   kTopDragonflyPinmuxMioOutMio1 = 1 ,   kTopDragonflyPinmuxMioOutMio2 = 2 ,   kTopDragonflyPinmuxMioOutMio3 = 3 ,   kTopDragonflyPinmuxMioOutMio4 = 4 ,   kTopDragonflyPinmuxMioOutMio5 = 5 ,   kTopDragonflyPinmuxMioOutMio6 = 6 ,   kTopDragonflyPinmuxMioOutMio7 = 7 ,   kTopDragonflyPinmuxMioOutMio8 = 8 ,   kTopDragonflyPinmuxMioOutMio9 = 9 ,   kTopDragonflyPinmuxMioOutMio10 = 10 ,   kTopDragonflyPinmuxMioOutMio11 = 11 ,   kTopDragonflyPinmuxMioOutLast = 11 }
	Pinmux MIO Output. More...
enum	top_dragonfly_pinmux_outsel {   kTopDragonflyPinmuxOutselConstantZero = 0 ,   kTopDragonflyPinmuxOutselConstantOne = 1 ,   kTopDragonflyPinmuxOutselConstantHighZ = 2 ,   kTopDragonflyPinmuxOutselSocProxySocGpo12 = 3 ,   kTopDragonflyPinmuxOutselSocProxySocGpo13 = 4 ,   kTopDragonflyPinmuxOutselSocProxySocGpo14 = 5 ,   kTopDragonflyPinmuxOutselSocProxySocGpo15 = 6 ,   kTopDragonflyPinmuxOutselOtpMacroTest0 = 7 ,   kTopDragonflyPinmuxOutselLast = 7 }
	Pinmux Peripheral Output Selector. More...
enum	top_dragonfly_direct_pads {   kTopDragonflyDirectPadsSpiHost0Sd0 = 0 ,   kTopDragonflyDirectPadsSpiHost0Sd1 = 1 ,   kTopDragonflyDirectPadsSpiHost0Sd2 = 2 ,   kTopDragonflyDirectPadsSpiHost0Sd3 = 3 ,   kTopDragonflyDirectPadsSpiDeviceSd0 = 4 ,   kTopDragonflyDirectPadsSpiDeviceSd1 = 5 ,   kTopDragonflyDirectPadsSpiDeviceSd2 = 6 ,   kTopDragonflyDirectPadsSpiDeviceSd3 = 7 ,   kTopDragonflyDirectPadsI2c0Scl = 8 ,   kTopDragonflyDirectPadsI2c0Sda = 9 ,   kTopDragonflyDirectPadsGpioGpio0 = 10 ,   kTopDragonflyDirectPadsGpioGpio1 = 11 ,   kTopDragonflyDirectPadsGpioGpio2 = 12 ,   kTopDragonflyDirectPadsGpioGpio3 = 13 ,   kTopDragonflyDirectPadsGpioGpio4 = 14 ,   kTopDragonflyDirectPadsGpioGpio5 = 15 ,   kTopDragonflyDirectPadsGpioGpio6 = 16 ,   kTopDragonflyDirectPadsGpioGpio7 = 17 ,   kTopDragonflyDirectPadsGpioGpio8 = 18 ,   kTopDragonflyDirectPadsGpioGpio9 = 19 ,   kTopDragonflyDirectPadsGpioGpio10 = 20 ,   kTopDragonflyDirectPadsGpioGpio11 = 21 ,   kTopDragonflyDirectPadsGpioGpio12 = 22 ,   kTopDragonflyDirectPadsGpioGpio13 = 23 ,   kTopDragonflyDirectPadsGpioGpio14 = 24 ,   kTopDragonflyDirectPadsGpioGpio15 = 25 ,   kTopDragonflyDirectPadsGpioGpio16 = 26 ,   kTopDragonflyDirectPadsGpioGpio17 = 27 ,   kTopDragonflyDirectPadsGpioGpio18 = 28 ,   kTopDragonflyDirectPadsGpioGpio19 = 29 ,   kTopDragonflyDirectPadsGpioGpio20 = 30 ,   kTopDragonflyDirectPadsGpioGpio21 = 31 ,   kTopDragonflyDirectPadsGpioGpio22 = 32 ,   kTopDragonflyDirectPadsGpioGpio23 = 33 ,   kTopDragonflyDirectPadsGpioGpio24 = 34 ,   kTopDragonflyDirectPadsGpioGpio25 = 35 ,   kTopDragonflyDirectPadsGpioGpio26 = 36 ,   kTopDragonflyDirectPadsGpioGpio27 = 37 ,   kTopDragonflyDirectPadsGpioGpio28 = 38 ,   kTopDragonflyDirectPadsGpioGpio29 = 39 ,   kTopDragonflyDirectPadsGpioGpio30 = 40 ,   kTopDragonflyDirectPadsGpioGpio31 = 41 ,   kTopDragonflyDirectPadsSpiDeviceSck = 42 ,   kTopDragonflyDirectPadsSpiDeviceCsb = 43 ,   kTopDragonflyDirectPadsSpiDeviceTpmCsb = 44 ,   kTopDragonflyDirectPadsUart0Rx = 45 ,   kTopDragonflyDirectPadsSocProxySocGpi0 = 46 ,   kTopDragonflyDirectPadsSocProxySocGpi1 = 47 ,   kTopDragonflyDirectPadsSocProxySocGpi2 = 48 ,   kTopDragonflyDirectPadsSocProxySocGpi3 = 49 ,   kTopDragonflyDirectPadsSocProxySocGpi4 = 50 ,   kTopDragonflyDirectPadsSocProxySocGpi5 = 51 ,   kTopDragonflyDirectPadsSocProxySocGpi6 = 52 ,   kTopDragonflyDirectPadsSocProxySocGpi7 = 53 ,   kTopDragonflyDirectPadsSocProxySocGpi8 = 54 ,   kTopDragonflyDirectPadsSocProxySocGpi9 = 55 ,   kTopDragonflyDirectPadsSocProxySocGpi10 = 56 ,   kTopDragonflyDirectPadsSocProxySocGpi11 = 57 ,   kTopDragonflyDirectPadsSpiHost0Sck = 58 ,   kTopDragonflyDirectPadsSpiHost0Csb = 59 ,   kTopDragonflyDirectPadsUart0Tx = 60 ,   kTopDragonflyDirectPadsSocProxySocGpo0 = 61 ,   kTopDragonflyDirectPadsSocProxySocGpo1 = 62 ,   kTopDragonflyDirectPadsSocProxySocGpo2 = 63 ,   kTopDragonflyDirectPadsSocProxySocGpo3 = 64 ,   kTopDragonflyDirectPadsSocProxySocGpo4 = 65 ,   kTopDragonflyDirectPadsSocProxySocGpo5 = 66 ,   kTopDragonflyDirectPadsSocProxySocGpo6 = 67 ,   kTopDragonflyDirectPadsSocProxySocGpo7 = 68 ,   kTopDragonflyDirectPadsSocProxySocGpo8 = 69 ,   kTopDragonflyDirectPadsSocProxySocGpo9 = 70 ,   kTopDragonflyDirectPadsSocProxySocGpo10 = 71 ,   kTopDragonflyDirectPadsSocProxySocGpo11 = 72 ,   kTopDragonflyDirectPadsLast = 72 }
	Dedicated Pad Selects. More...
enum	top_dragonfly_muxed_pads {   kTopDragonflyMuxedPadsMio0 = 0 ,   kTopDragonflyMuxedPadsMio1 = 1 ,   kTopDragonflyMuxedPadsMio2 = 2 ,   kTopDragonflyMuxedPadsMio3 = 3 ,   kTopDragonflyMuxedPadsMio4 = 4 ,   kTopDragonflyMuxedPadsMio5 = 5 ,   kTopDragonflyMuxedPadsMio6 = 6 ,   kTopDragonflyMuxedPadsMio7 = 7 ,   kTopDragonflyMuxedPadsMio8 = 8 ,   kTopDragonflyMuxedPadsMio9 = 9 ,   kTopDragonflyMuxedPadsMio10 = 10 ,   kTopDragonflyMuxedPadsMio11 = 11 ,   kTopDragonflyMuxedPadsLast = 11 }
	Muxed Pad Selects. More...
enum	top_dragonfly_power_manager_wake_ups {   kTopDragonflyPowerManagerWakeUpsPinmuxAonPinWkupReq = 0 ,   kTopDragonflyPowerManagerWakeUpsAonTimerAonWkupReq = 1 ,   kTopDragonflyPowerManagerWakeUpsSocProxyWkupExternalReq = 2 ,   kTopDragonflyPowerManagerWakeUpsLast = 2 }
	Power Manager Wakeup Signals. More...
enum	top_dragonfly_reset_manager_sw_resets {   kTopDragonflyResetManagerSwResetsSpiDevice = 0 ,   kTopDragonflyResetManagerSwResetsSpiHost0 = 1 ,   kTopDragonflyResetManagerSwResetsI2c0 = 2 ,   kTopDragonflyResetManagerSwResetsLast = 2 }
	Reset Manager Software Controlled Resets. More...
enum	top_dragonfly_power_manager_reset_requests {   kTopDragonflyPowerManagerResetRequestsAonTimerAonAonTimerRstReq = 0 ,   kTopDragonflyPowerManagerResetRequestsSocProxyRstReqExternal = 1 ,   kTopDragonflyPowerManagerResetRequestsLast = 1 }
	Power Manager Reset Request Signals. More...
enum	top_dragonfly_gateable_clocks {   kTopDragonflyGateableClocksIoPeri = 0 ,   kTopDragonflyGateableClocksLast = 0 }
	Clock Manager Software-Controlled ("Gated") Clocks. More...
enum	top_dragonfly_hintable_clocks {   kTopDragonflyHintableClocksMainAcc = 0 ,   kTopDragonflyHintableClocksMainAes = 1 ,   kTopDragonflyHintableClocksMainHmac = 2 ,   kTopDragonflyHintableClocksMainKmac = 3 ,   kTopDragonflyHintableClocksLast = 3 }
	Clock Manager Software-Hinted Clocks. More...

Variables
const top_dragonfly_plic_peripheral_t	top_dragonfly_plic_interrupt_for_peripheral [132]
	PLIC Interrupt Source to Peripheral Map.
const top_dragonfly_alert_peripheral_t	top_dragonfly_alert_for_peripheral [77]
	Alert Handler Alert Source to Peripheral Map.

Detailed Description

Top-specific Definitions.

This file contains preprocessor and type definitions for use within the device C/C++ codebase.

These definitions are for information that depends on the top-specific chip configuration, which includes:

• Device Memory Information (for Peripherals and Memory)
• PLIC Interrupt ID Names and Source Mappings
• Alert ID Names and Source Mappings
• Pinmux Pin/Select Names
• Power Manager Wakeups

Definition in file top_dragonfly.h.

Macro Definition Documentation

NUM_DIO_PADS

#define NUM_DIO_PADS   73

Definition at line 1312 of file top_dragonfly.h.

NUM_MIO_PADS

#define NUM_MIO_PADS   12

Definition at line 1311 of file top_dragonfly.h.

PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET

#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET   2

Definition at line 1307 of file top_dragonfly.h.

PINMUX_PERIPH_OUTSEL_IDX_OFFSET

#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET   3

Definition at line 1314 of file top_dragonfly.h.

TOP_DRAGONFLY_ACC_BASE_ADDR

#define TOP_DRAGONFLY_ACC_BASE_ADDR   0x22100000u

Peripheral base address for acc in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 416 of file top_dragonfly.h.

TOP_DRAGONFLY_ACC_SIZE_BYTES

#define TOP_DRAGONFLY_ACC_SIZE_BYTES   0x20000u

Peripheral size for acc in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_ACC_BASE_ADDR and TOP_DRAGONFLY_ACC_BASE_ADDR + TOP_DRAGONFLY_ACC_SIZE_BYTES.

Definition at line 426 of file top_dragonfly.h.

TOP_DRAGONFLY_AES_BASE_ADDR

#define TOP_DRAGONFLY_AES_BASE_ADDR   0x21100000u

Peripheral base address for aes in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 434 of file top_dragonfly.h.

TOP_DRAGONFLY_AES_SIZE_BYTES

#define TOP_DRAGONFLY_AES_SIZE_BYTES   0x100u

Peripheral size for aes in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_AES_BASE_ADDR and TOP_DRAGONFLY_AES_BASE_ADDR + TOP_DRAGONFLY_AES_SIZE_BYTES.

Definition at line 444 of file top_dragonfly.h.

TOP_DRAGONFLY_ALERT_HANDLER_BASE_ADDR

#define TOP_DRAGONFLY_ALERT_HANDLER_BASE_ADDR   0x30160000u

Peripheral base address for alert_handler in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 182 of file top_dragonfly.h.

TOP_DRAGONFLY_ALERT_HANDLER_SIZE_BYTES

#define TOP_DRAGONFLY_ALERT_HANDLER_SIZE_BYTES   0x800u

Peripheral size for alert_handler in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_ALERT_HANDLER_BASE_ADDR and TOP_DRAGONFLY_ALERT_HANDLER_BASE_ADDR + TOP_DRAGONFLY_ALERT_HANDLER_SIZE_BYTES.

Definition at line 192 of file top_dragonfly.h.

TOP_DRAGONFLY_AON_TIMER_AON_BASE_ADDR

#define TOP_DRAGONFLY_AON_TIMER_AON_BASE_ADDR   0x30470000u

Peripheral base address for aon_timer_aon in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 290 of file top_dragonfly.h.

TOP_DRAGONFLY_AON_TIMER_AON_SIZE_BYTES

#define TOP_DRAGONFLY_AON_TIMER_AON_SIZE_BYTES   0x40u

Peripheral size for aon_timer_aon in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_AON_TIMER_AON_BASE_ADDR and TOP_DRAGONFLY_AON_TIMER_AON_BASE_ADDR + TOP_DRAGONFLY_AON_TIMER_AON_SIZE_BYTES.

Definition at line 300 of file top_dragonfly.h.

TOP_DRAGONFLY_AST_BASE_ADDR

#define TOP_DRAGONFLY_AST_BASE_ADDR   0x30480000u

Peripheral base address for ast in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 308 of file top_dragonfly.h.

TOP_DRAGONFLY_AST_SIZE_BYTES

#define TOP_DRAGONFLY_AST_SIZE_BYTES   0x400u

Peripheral size for ast in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_AST_BASE_ADDR and TOP_DRAGONFLY_AST_BASE_ADDR + TOP_DRAGONFLY_AST_SIZE_BYTES.

Definition at line 318 of file top_dragonfly.h.

TOP_DRAGONFLY_CLKMGR_AON_BASE_ADDR

#define TOP_DRAGONFLY_CLKMGR_AON_BASE_ADDR   0x30420000u

Peripheral base address for clkmgr_aon in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 254 of file top_dragonfly.h.

TOP_DRAGONFLY_CLKMGR_AON_SIZE_BYTES

#define TOP_DRAGONFLY_CLKMGR_AON_SIZE_BYTES   0x40u

Peripheral size for clkmgr_aon in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_CLKMGR_AON_BASE_ADDR and TOP_DRAGONFLY_CLKMGR_AON_BASE_ADDR + TOP_DRAGONFLY_CLKMGR_AON_SIZE_BYTES.

Definition at line 264 of file top_dragonfly.h.

TOP_DRAGONFLY_CSRNG_BASE_ADDR

#define TOP_DRAGONFLY_CSRNG_BASE_ADDR   0x21150000u

Peripheral base address for csrng in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 506 of file top_dragonfly.h.

TOP_DRAGONFLY_CSRNG_SIZE_BYTES

#define TOP_DRAGONFLY_CSRNG_SIZE_BYTES   0x80u

Peripheral size for csrng in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_CSRNG_BASE_ADDR and TOP_DRAGONFLY_CSRNG_BASE_ADDR + TOP_DRAGONFLY_CSRNG_SIZE_BYTES.

Definition at line 516 of file top_dragonfly.h.

TOP_DRAGONFLY_DMA_BASE_ADDR

#define TOP_DRAGONFLY_DMA_BASE_ADDR   0x22010000u

Peripheral base address for dma in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 650 of file top_dragonfly.h.

TOP_DRAGONFLY_DMA_SIZE_BYTES

#define TOP_DRAGONFLY_DMA_SIZE_BYTES   0x200u

Peripheral size for dma in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_DMA_BASE_ADDR and TOP_DRAGONFLY_DMA_BASE_ADDR + TOP_DRAGONFLY_DMA_SIZE_BYTES.

Definition at line 660 of file top_dragonfly.h.

TOP_DRAGONFLY_EDN0_BASE_ADDR

#define TOP_DRAGONFLY_EDN0_BASE_ADDR   0x21170000u

Peripheral base address for edn0 in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 542 of file top_dragonfly.h.

TOP_DRAGONFLY_EDN0_SIZE_BYTES

#define TOP_DRAGONFLY_EDN0_SIZE_BYTES   0x80u

Peripheral size for edn0 in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_EDN0_BASE_ADDR and TOP_DRAGONFLY_EDN0_BASE_ADDR + TOP_DRAGONFLY_EDN0_SIZE_BYTES.

Definition at line 552 of file top_dragonfly.h.

TOP_DRAGONFLY_EDN1_BASE_ADDR

#define TOP_DRAGONFLY_EDN1_BASE_ADDR   0x21180000u

Peripheral base address for edn1 in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 560 of file top_dragonfly.h.

TOP_DRAGONFLY_EDN1_SIZE_BYTES

#define TOP_DRAGONFLY_EDN1_SIZE_BYTES   0x80u

Peripheral size for edn1 in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_EDN1_BASE_ADDR and TOP_DRAGONFLY_EDN1_BASE_ADDR + TOP_DRAGONFLY_EDN1_SIZE_BYTES.

Definition at line 570 of file top_dragonfly.h.

TOP_DRAGONFLY_ENTROPY_SRC_BASE_ADDR

#define TOP_DRAGONFLY_ENTROPY_SRC_BASE_ADDR   0x21160000u

Peripheral base address for entropy_src in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 524 of file top_dragonfly.h.

TOP_DRAGONFLY_ENTROPY_SRC_SIZE_BYTES

#define TOP_DRAGONFLY_ENTROPY_SRC_SIZE_BYTES   0x100u

Peripheral size for entropy_src in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_ENTROPY_SRC_BASE_ADDR and TOP_DRAGONFLY_ENTROPY_SRC_BASE_ADDR + TOP_DRAGONFLY_ENTROPY_SRC_SIZE_BYTES.

Definition at line 534 of file top_dragonfly.h.

TOP_DRAGONFLY_GPIO_BASE_ADDR

#define TOP_DRAGONFLY_GPIO_BASE_ADDR   0x30000000u

Peripheral base address for gpio in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 56 of file top_dragonfly.h.

TOP_DRAGONFLY_GPIO_SIZE_BYTES

#define TOP_DRAGONFLY_GPIO_SIZE_BYTES   0x100u

Peripheral size for gpio in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_GPIO_BASE_ADDR and TOP_DRAGONFLY_GPIO_BASE_ADDR + TOP_DRAGONFLY_GPIO_SIZE_BYTES.

Definition at line 66 of file top_dragonfly.h.

TOP_DRAGONFLY_HMAC_BASE_ADDR

#define TOP_DRAGONFLY_HMAC_BASE_ADDR   0x21110000u

Peripheral base address for hmac in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 452 of file top_dragonfly.h.

TOP_DRAGONFLY_HMAC_SIZE_BYTES

#define TOP_DRAGONFLY_HMAC_SIZE_BYTES   0x2000u

Peripheral size for hmac in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_HMAC_BASE_ADDR and TOP_DRAGONFLY_HMAC_BASE_ADDR + TOP_DRAGONFLY_HMAC_SIZE_BYTES.

Definition at line 462 of file top_dragonfly.h.

TOP_DRAGONFLY_I2C0_BASE_ADDR

#define TOP_DRAGONFLY_I2C0_BASE_ADDR   0x30080000u

Peripheral base address for i2c0 in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 92 of file top_dragonfly.h.

TOP_DRAGONFLY_I2C0_SIZE_BYTES

#define TOP_DRAGONFLY_I2C0_SIZE_BYTES   0x80u

Peripheral size for i2c0 in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_I2C0_BASE_ADDR and TOP_DRAGONFLY_I2C0_BASE_ADDR + TOP_DRAGONFLY_I2C0_SIZE_BYTES.

Definition at line 102 of file top_dragonfly.h.

TOP_DRAGONFLY_KEYMGR_DPE_BASE_ADDR

#define TOP_DRAGONFLY_KEYMGR_DPE_BASE_ADDR   0x21140000u

Peripheral base address for keymgr_dpe in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 488 of file top_dragonfly.h.

TOP_DRAGONFLY_KEYMGR_DPE_SIZE_BYTES

#define TOP_DRAGONFLY_KEYMGR_DPE_SIZE_BYTES   0x100u

Peripheral size for keymgr_dpe in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_KEYMGR_DPE_BASE_ADDR and TOP_DRAGONFLY_KEYMGR_DPE_BASE_ADDR + TOP_DRAGONFLY_KEYMGR_DPE_SIZE_BYTES.

Definition at line 498 of file top_dragonfly.h.

TOP_DRAGONFLY_KMAC_BASE_ADDR

#define TOP_DRAGONFLY_KMAC_BASE_ADDR   0x21120000u

Peripheral base address for kmac in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 470 of file top_dragonfly.h.

TOP_DRAGONFLY_KMAC_SIZE_BYTES

#define TOP_DRAGONFLY_KMAC_SIZE_BYTES   0x1000u

Peripheral size for kmac in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_KMAC_BASE_ADDR and TOP_DRAGONFLY_KMAC_BASE_ADDR + TOP_DRAGONFLY_KMAC_SIZE_BYTES.

Definition at line 480 of file top_dragonfly.h.

TOP_DRAGONFLY_LC_CTRL_REGS_BASE_ADDR

#define TOP_DRAGONFLY_LC_CTRL_REGS_BASE_ADDR   0x30150000u

Peripheral base address for regs device on lc_ctrl in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 164 of file top_dragonfly.h.

TOP_DRAGONFLY_LC_CTRL_REGS_SIZE_BYTES

#define TOP_DRAGONFLY_LC_CTRL_REGS_SIZE_BYTES   0x100u

Peripheral size for regs device on lc_ctrl in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_LC_CTRL_REGS_BASE_ADDR and TOP_DRAGONFLY_LC_CTRL_REGS_BASE_ADDR + TOP_DRAGONFLY_LC_CTRL_REGS_SIZE_BYTES.

Definition at line 174 of file top_dragonfly.h.

TOP_DRAGONFLY_MBX0_CORE_BASE_ADDR

#define TOP_DRAGONFLY_MBX0_CORE_BASE_ADDR   0x22000000u

Peripheral base address for core device on mbx0 in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 668 of file top_dragonfly.h.

TOP_DRAGONFLY_MBX0_CORE_SIZE_BYTES

#define TOP_DRAGONFLY_MBX0_CORE_SIZE_BYTES   0x80u

Peripheral size for core device on mbx0 in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_MBX0_CORE_BASE_ADDR and TOP_DRAGONFLY_MBX0_CORE_BASE_ADDR + TOP_DRAGONFLY_MBX0_CORE_SIZE_BYTES.

Definition at line 678 of file top_dragonfly.h.

TOP_DRAGONFLY_MBX1_CORE_BASE_ADDR

#define TOP_DRAGONFLY_MBX1_CORE_BASE_ADDR   0x22000100u

Peripheral base address for core device on mbx1 in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 686 of file top_dragonfly.h.

TOP_DRAGONFLY_MBX1_CORE_SIZE_BYTES

#define TOP_DRAGONFLY_MBX1_CORE_SIZE_BYTES   0x80u

Peripheral size for core device on mbx1 in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_MBX1_CORE_BASE_ADDR and TOP_DRAGONFLY_MBX1_CORE_BASE_ADDR + TOP_DRAGONFLY_MBX1_CORE_SIZE_BYTES.

Definition at line 696 of file top_dragonfly.h.

TOP_DRAGONFLY_MBX2_CORE_BASE_ADDR

#define TOP_DRAGONFLY_MBX2_CORE_BASE_ADDR   0x22000200u

Peripheral base address for core device on mbx2 in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 704 of file top_dragonfly.h.

TOP_DRAGONFLY_MBX2_CORE_SIZE_BYTES

#define TOP_DRAGONFLY_MBX2_CORE_SIZE_BYTES   0x80u

Peripheral size for core device on mbx2 in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_MBX2_CORE_BASE_ADDR and TOP_DRAGONFLY_MBX2_CORE_BASE_ADDR + TOP_DRAGONFLY_MBX2_CORE_SIZE_BYTES.

Definition at line 714 of file top_dragonfly.h.

TOP_DRAGONFLY_MBX3_CORE_BASE_ADDR

#define TOP_DRAGONFLY_MBX3_CORE_BASE_ADDR   0x22000300u

Peripheral base address for core device on mbx3 in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 722 of file top_dragonfly.h.

TOP_DRAGONFLY_MBX3_CORE_SIZE_BYTES

#define TOP_DRAGONFLY_MBX3_CORE_SIZE_BYTES   0x80u

Peripheral size for core device on mbx3 in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_MBX3_CORE_BASE_ADDR and TOP_DRAGONFLY_MBX3_CORE_BASE_ADDR + TOP_DRAGONFLY_MBX3_CORE_SIZE_BYTES.

Definition at line 732 of file top_dragonfly.h.

TOP_DRAGONFLY_MBX4_CORE_BASE_ADDR

#define TOP_DRAGONFLY_MBX4_CORE_BASE_ADDR   0x22000400u

Peripheral base address for core device on mbx4 in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 740 of file top_dragonfly.h.

TOP_DRAGONFLY_MBX4_CORE_SIZE_BYTES

#define TOP_DRAGONFLY_MBX4_CORE_SIZE_BYTES   0x80u

Peripheral size for core device on mbx4 in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_MBX4_CORE_BASE_ADDR and TOP_DRAGONFLY_MBX4_CORE_BASE_ADDR + TOP_DRAGONFLY_MBX4_CORE_SIZE_BYTES.

Definition at line 750 of file top_dragonfly.h.

TOP_DRAGONFLY_MBX5_CORE_BASE_ADDR

#define TOP_DRAGONFLY_MBX5_CORE_BASE_ADDR   0x22000500u

Peripheral base address for core device on mbx5 in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 758 of file top_dragonfly.h.

TOP_DRAGONFLY_MBX5_CORE_SIZE_BYTES

#define TOP_DRAGONFLY_MBX5_CORE_SIZE_BYTES   0x80u

Peripheral size for core device on mbx5 in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_MBX5_CORE_BASE_ADDR and TOP_DRAGONFLY_MBX5_CORE_BASE_ADDR + TOP_DRAGONFLY_MBX5_CORE_SIZE_BYTES.

Definition at line 768 of file top_dragonfly.h.

TOP_DRAGONFLY_MBX6_CORE_BASE_ADDR

#define TOP_DRAGONFLY_MBX6_CORE_BASE_ADDR   0x22000600u

Peripheral base address for core device on mbx6 in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 776 of file top_dragonfly.h.

TOP_DRAGONFLY_MBX6_CORE_SIZE_BYTES

#define TOP_DRAGONFLY_MBX6_CORE_SIZE_BYTES   0x80u

Peripheral size for core device on mbx6 in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_MBX6_CORE_BASE_ADDR and TOP_DRAGONFLY_MBX6_CORE_BASE_ADDR + TOP_DRAGONFLY_MBX6_CORE_SIZE_BYTES.

Definition at line 786 of file top_dragonfly.h.

TOP_DRAGONFLY_MBX_JTAG_CORE_BASE_ADDR

#define TOP_DRAGONFLY_MBX_JTAG_CORE_BASE_ADDR   0x22000800u

Peripheral base address for core device on mbx_jtag in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 794 of file top_dragonfly.h.

TOP_DRAGONFLY_MBX_JTAG_CORE_SIZE_BYTES

#define TOP_DRAGONFLY_MBX_JTAG_CORE_SIZE_BYTES   0x80u

Peripheral size for core device on mbx_jtag in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_MBX_JTAG_CORE_BASE_ADDR and TOP_DRAGONFLY_MBX_JTAG_CORE_BASE_ADDR + TOP_DRAGONFLY_MBX_JTAG_CORE_SIZE_BYTES.

Definition at line 804 of file top_dragonfly.h.

TOP_DRAGONFLY_MBX_PCIE0_CORE_BASE_ADDR

#define TOP_DRAGONFLY_MBX_PCIE0_CORE_BASE_ADDR   0x22040000u

Peripheral base address for core device on mbx_pcie0 in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 812 of file top_dragonfly.h.

TOP_DRAGONFLY_MBX_PCIE0_CORE_SIZE_BYTES

#define TOP_DRAGONFLY_MBX_PCIE0_CORE_SIZE_BYTES   0x80u

Peripheral size for core device on mbx_pcie0 in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_MBX_PCIE0_CORE_BASE_ADDR and TOP_DRAGONFLY_MBX_PCIE0_CORE_BASE_ADDR + TOP_DRAGONFLY_MBX_PCIE0_CORE_SIZE_BYTES.

Definition at line 822 of file top_dragonfly.h.

TOP_DRAGONFLY_MBX_PCIE1_CORE_BASE_ADDR

#define TOP_DRAGONFLY_MBX_PCIE1_CORE_BASE_ADDR   0x22040100u

Peripheral base address for core device on mbx_pcie1 in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 830 of file top_dragonfly.h.

TOP_DRAGONFLY_MBX_PCIE1_CORE_SIZE_BYTES

#define TOP_DRAGONFLY_MBX_PCIE1_CORE_SIZE_BYTES   0x80u

Peripheral size for core device on mbx_pcie1 in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_MBX_PCIE1_CORE_BASE_ADDR and TOP_DRAGONFLY_MBX_PCIE1_CORE_BASE_ADDR + TOP_DRAGONFLY_MBX_PCIE1_CORE_SIZE_BYTES.

Definition at line 840 of file top_dragonfly.h.

TOP_DRAGONFLY_MMIO_BASE_ADDR

#define TOP_DRAGONFLY_MMIO_BASE_ADDR   0x21100000u

MMIO Region.

MMIO region excludes any memory that is separate from the module configuration space, i.e. ROM, main SRAM, and mbx SRAM are excluded but retention SRAM or spi_device are included.

Definition at line 1541 of file top_dragonfly.h.

TOP_DRAGONFLY_MMIO_SIZE_BYTES

#define TOP_DRAGONFLY_MMIO_SIZE_BYTES   0xF501000u

Definition at line 1542 of file top_dragonfly.h.

TOP_DRAGONFLY_OTP_CTRL_CORE_BASE_ADDR

#define TOP_DRAGONFLY_OTP_CTRL_CORE_BASE_ADDR   0x30130000u

Peripheral base address for core device on otp_ctrl in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 128 of file top_dragonfly.h.

TOP_DRAGONFLY_OTP_CTRL_CORE_SIZE_BYTES

#define TOP_DRAGONFLY_OTP_CTRL_CORE_SIZE_BYTES   0x10000u

Peripheral size for core device on otp_ctrl in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_OTP_CTRL_CORE_BASE_ADDR and TOP_DRAGONFLY_OTP_CTRL_CORE_BASE_ADDR + TOP_DRAGONFLY_OTP_CTRL_CORE_SIZE_BYTES.

Definition at line 138 of file top_dragonfly.h.

TOP_DRAGONFLY_OTP_MACRO_PRIM_BASE_ADDR

#define TOP_DRAGONFLY_OTP_MACRO_PRIM_BASE_ADDR   0x30140000u

Peripheral base address for prim device on otp_macro in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 146 of file top_dragonfly.h.

TOP_DRAGONFLY_OTP_MACRO_PRIM_SIZE_BYTES

#define TOP_DRAGONFLY_OTP_MACRO_PRIM_SIZE_BYTES   0x20u

Peripheral size for prim device on otp_macro in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_OTP_MACRO_PRIM_BASE_ADDR and TOP_DRAGONFLY_OTP_MACRO_PRIM_BASE_ADDR + TOP_DRAGONFLY_OTP_MACRO_PRIM_SIZE_BYTES.

Definition at line 156 of file top_dragonfly.h.

TOP_DRAGONFLY_PINMUX_AON_BASE_ADDR

#define TOP_DRAGONFLY_PINMUX_AON_BASE_ADDR   0x30460000u

Peripheral base address for pinmux_aon in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 272 of file top_dragonfly.h.

TOP_DRAGONFLY_PINMUX_AON_SIZE_BYTES

#define TOP_DRAGONFLY_PINMUX_AON_SIZE_BYTES   0x800u

Peripheral size for pinmux_aon in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_PINMUX_AON_BASE_ADDR and TOP_DRAGONFLY_PINMUX_AON_BASE_ADDR + TOP_DRAGONFLY_PINMUX_AON_SIZE_BYTES.

Definition at line 282 of file top_dragonfly.h.

TOP_DRAGONFLY_PWRMGR_AON_BASE_ADDR

#define TOP_DRAGONFLY_PWRMGR_AON_BASE_ADDR   0x30400000u

Peripheral base address for pwrmgr_aon in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 218 of file top_dragonfly.h.

TOP_DRAGONFLY_PWRMGR_AON_SIZE_BYTES

#define TOP_DRAGONFLY_PWRMGR_AON_SIZE_BYTES   0x80u

Peripheral size for pwrmgr_aon in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_PWRMGR_AON_BASE_ADDR and TOP_DRAGONFLY_PWRMGR_AON_BASE_ADDR + TOP_DRAGONFLY_PWRMGR_AON_SIZE_BYTES.

Definition at line 228 of file top_dragonfly.h.

TOP_DRAGONFLY_ROM_CTRL0_REGS_BASE_ADDR

#define TOP_DRAGONFLY_ROM_CTRL0_REGS_BASE_ADDR   0x211E0000u

Peripheral base address for regs device on rom_ctrl0 in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 614 of file top_dragonfly.h.

TOP_DRAGONFLY_ROM_CTRL0_REGS_SIZE_BYTES

#define TOP_DRAGONFLY_ROM_CTRL0_REGS_SIZE_BYTES   0x80u

Peripheral size for regs device on rom_ctrl0 in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_ROM_CTRL0_REGS_BASE_ADDR and TOP_DRAGONFLY_ROM_CTRL0_REGS_BASE_ADDR + TOP_DRAGONFLY_ROM_CTRL0_REGS_SIZE_BYTES.

Definition at line 624 of file top_dragonfly.h.

TOP_DRAGONFLY_ROM_CTRL0_ROM_BASE_ADDR

#define TOP_DRAGONFLY_ROM_CTRL0_ROM_BASE_ADDR   0x8000u

Memory base address for rom memory on rom_ctrl0 in top dragonfly.

Definition at line 932 of file top_dragonfly.h.

TOP_DRAGONFLY_ROM_CTRL0_ROM_SIZE_BYTES

#define TOP_DRAGONFLY_ROM_CTRL0_ROM_SIZE_BYTES   0x8000u

Memory size for rom memory on rom_ctrl0 in top dragonfly.

Definition at line 937 of file top_dragonfly.h.

TOP_DRAGONFLY_ROM_CTRL1_REGS_BASE_ADDR

#define TOP_DRAGONFLY_ROM_CTRL1_REGS_BASE_ADDR   0x211E1000u

Peripheral base address for regs device on rom_ctrl1 in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 632 of file top_dragonfly.h.

TOP_DRAGONFLY_ROM_CTRL1_REGS_SIZE_BYTES

#define TOP_DRAGONFLY_ROM_CTRL1_REGS_SIZE_BYTES   0x80u

Peripheral size for regs device on rom_ctrl1 in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_ROM_CTRL1_REGS_BASE_ADDR and TOP_DRAGONFLY_ROM_CTRL1_REGS_BASE_ADDR + TOP_DRAGONFLY_ROM_CTRL1_REGS_SIZE_BYTES.

Definition at line 642 of file top_dragonfly.h.

TOP_DRAGONFLY_ROM_CTRL1_ROM_BASE_ADDR

#define TOP_DRAGONFLY_ROM_CTRL1_ROM_BASE_ADDR   0x20000u

Memory base address for rom memory on rom_ctrl1 in top dragonfly.

Definition at line 942 of file top_dragonfly.h.

TOP_DRAGONFLY_ROM_CTRL1_ROM_SIZE_BYTES

#define TOP_DRAGONFLY_ROM_CTRL1_ROM_SIZE_BYTES   0x10000u

Memory size for rom memory on rom_ctrl1 in top dragonfly.

Definition at line 947 of file top_dragonfly.h.

TOP_DRAGONFLY_RSTMGR_AON_BASE_ADDR

#define TOP_DRAGONFLY_RSTMGR_AON_BASE_ADDR   0x30410000u

Peripheral base address for rstmgr_aon in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 236 of file top_dragonfly.h.

TOP_DRAGONFLY_RSTMGR_AON_SIZE_BYTES

#define TOP_DRAGONFLY_RSTMGR_AON_SIZE_BYTES   0x80u

Peripheral size for rstmgr_aon in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_RSTMGR_AON_BASE_ADDR and TOP_DRAGONFLY_RSTMGR_AON_BASE_ADDR + TOP_DRAGONFLY_RSTMGR_AON_SIZE_BYTES.

Definition at line 246 of file top_dragonfly.h.

TOP_DRAGONFLY_RV_CORE_IBEX_CFG_BASE_ADDR

#define TOP_DRAGONFLY_RV_CORE_IBEX_CFG_BASE_ADDR   0x211F0000u

Peripheral base address for cfg device on rv_core_ibex in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 866 of file top_dragonfly.h.

TOP_DRAGONFLY_RV_CORE_IBEX_CFG_SIZE_BYTES

#define TOP_DRAGONFLY_RV_CORE_IBEX_CFG_SIZE_BYTES   0x800u

Peripheral size for cfg device on rv_core_ibex in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_RV_CORE_IBEX_CFG_BASE_ADDR and TOP_DRAGONFLY_RV_CORE_IBEX_CFG_BASE_ADDR + TOP_DRAGONFLY_RV_CORE_IBEX_CFG_SIZE_BYTES.

Definition at line 876 of file top_dragonfly.h.

TOP_DRAGONFLY_RV_DM_MEM_BASE_ADDR

#define TOP_DRAGONFLY_RV_DM_MEM_BASE_ADDR   0x40000u

Peripheral base address for mem device on rv_dm in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 380 of file top_dragonfly.h.

TOP_DRAGONFLY_RV_DM_MEM_SIZE_BYTES

#define TOP_DRAGONFLY_RV_DM_MEM_SIZE_BYTES   0x1000u

Peripheral size for mem device on rv_dm in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_RV_DM_MEM_BASE_ADDR and TOP_DRAGONFLY_RV_DM_MEM_BASE_ADDR + TOP_DRAGONFLY_RV_DM_MEM_SIZE_BYTES.

Definition at line 390 of file top_dragonfly.h.

TOP_DRAGONFLY_RV_DM_REGS_BASE_ADDR

#define TOP_DRAGONFLY_RV_DM_REGS_BASE_ADDR   0x21200000u

Peripheral base address for regs device on rv_dm in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 362 of file top_dragonfly.h.

TOP_DRAGONFLY_RV_DM_REGS_SIZE_BYTES

#define TOP_DRAGONFLY_RV_DM_REGS_SIZE_BYTES   0x10u

Peripheral size for regs device on rv_dm in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_RV_DM_REGS_BASE_ADDR and TOP_DRAGONFLY_RV_DM_REGS_BASE_ADDR + TOP_DRAGONFLY_RV_DM_REGS_SIZE_BYTES.

Definition at line 372 of file top_dragonfly.h.

TOP_DRAGONFLY_RV_PLIC_BASE_ADDR

#define TOP_DRAGONFLY_RV_PLIC_BASE_ADDR   0x28000000u

Peripheral base address for rv_plic in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 398 of file top_dragonfly.h.

TOP_DRAGONFLY_RV_PLIC_SIZE_BYTES

#define TOP_DRAGONFLY_RV_PLIC_SIZE_BYTES   0x8000000u

Peripheral size for rv_plic in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_RV_PLIC_BASE_ADDR and TOP_DRAGONFLY_RV_PLIC_BASE_ADDR + TOP_DRAGONFLY_RV_PLIC_SIZE_BYTES.

Definition at line 408 of file top_dragonfly.h.

TOP_DRAGONFLY_RV_TIMER_BASE_ADDR

#define TOP_DRAGONFLY_RV_TIMER_BASE_ADDR   0x30100000u

Peripheral base address for rv_timer in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 110 of file top_dragonfly.h.

TOP_DRAGONFLY_RV_TIMER_SIZE_BYTES

#define TOP_DRAGONFLY_RV_TIMER_SIZE_BYTES   0x200u

Peripheral size for rv_timer in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_RV_TIMER_BASE_ADDR and TOP_DRAGONFLY_RV_TIMER_BASE_ADDR + TOP_DRAGONFLY_RV_TIMER_SIZE_BYTES.

Definition at line 120 of file top_dragonfly.h.

TOP_DRAGONFLY_SOC_DBG_CTRL_CORE_BASE_ADDR

#define TOP_DRAGONFLY_SOC_DBG_CTRL_CORE_BASE_ADDR   0x30170000u

Peripheral base address for core device on soc_dbg_ctrl in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 848 of file top_dragonfly.h.

TOP_DRAGONFLY_SOC_DBG_CTRL_CORE_SIZE_BYTES

#define TOP_DRAGONFLY_SOC_DBG_CTRL_CORE_SIZE_BYTES   0x20u

Peripheral size for core device on soc_dbg_ctrl in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_SOC_DBG_CTRL_CORE_BASE_ADDR and TOP_DRAGONFLY_SOC_DBG_CTRL_CORE_BASE_ADDR + TOP_DRAGONFLY_SOC_DBG_CTRL_CORE_SIZE_BYTES.

Definition at line 858 of file top_dragonfly.h.

TOP_DRAGONFLY_SOC_PROXY_CORE_BASE_ADDR

#define TOP_DRAGONFLY_SOC_PROXY_CORE_BASE_ADDR   0x22030000u

Peripheral base address for core device on soc_proxy in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 326 of file top_dragonfly.h.

TOP_DRAGONFLY_SOC_PROXY_CORE_SIZE_BYTES

#define TOP_DRAGONFLY_SOC_PROXY_CORE_SIZE_BYTES   0x8u

Peripheral size for core device on soc_proxy in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_SOC_PROXY_CORE_BASE_ADDR and TOP_DRAGONFLY_SOC_PROXY_CORE_BASE_ADDR + TOP_DRAGONFLY_SOC_PROXY_CORE_SIZE_BYTES.

Definition at line 336 of file top_dragonfly.h.

TOP_DRAGONFLY_SOC_PROXY_CTN_BASE_ADDR

#define TOP_DRAGONFLY_SOC_PROXY_CTN_BASE_ADDR   0x40000000u

Memory base address for ctn memory on soc_proxy in top dragonfly.

Definition at line 882 of file top_dragonfly.h.

TOP_DRAGONFLY_SOC_PROXY_CTN_SIZE_BYTES

#define TOP_DRAGONFLY_SOC_PROXY_CTN_SIZE_BYTES   0x80000000u

Memory size for ctn memory on soc_proxy in top dragonfly.

Definition at line 887 of file top_dragonfly.h.

TOP_DRAGONFLY_SOC_PROXY_RAM_CTN_BASE_ADDR

#define TOP_DRAGONFLY_SOC_PROXY_RAM_CTN_BASE_ADDR   0x41000000u

Memory base address for ram_ctn in top dragonfly.

Definition at line 892 of file top_dragonfly.h.

TOP_DRAGONFLY_SOC_PROXY_RAM_CTN_SIZE_BYTES

#define TOP_DRAGONFLY_SOC_PROXY_RAM_CTN_SIZE_BYTES   0x100000u

Memory size for ram_ctn in top dragonfly.

Definition at line 897 of file top_dragonfly.h.

TOP_DRAGONFLY_SPI_DEVICE_BASE_ADDR

#define TOP_DRAGONFLY_SPI_DEVICE_BASE_ADDR   0x30310000u

Peripheral base address for spi_device in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 74 of file top_dragonfly.h.

TOP_DRAGONFLY_SPI_DEVICE_SIZE_BYTES

#define TOP_DRAGONFLY_SPI_DEVICE_SIZE_BYTES   0x2000u

Peripheral size for spi_device in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_SPI_DEVICE_BASE_ADDR and TOP_DRAGONFLY_SPI_DEVICE_BASE_ADDR + TOP_DRAGONFLY_SPI_DEVICE_SIZE_BYTES.

Definition at line 84 of file top_dragonfly.h.

TOP_DRAGONFLY_SPI_HOST0_BASE_ADDR

#define TOP_DRAGONFLY_SPI_HOST0_BASE_ADDR   0x30300000u

Peripheral base address for spi_host0 in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 200 of file top_dragonfly.h.

TOP_DRAGONFLY_SPI_HOST0_SIZE_BYTES

#define TOP_DRAGONFLY_SPI_HOST0_SIZE_BYTES   0x40u

Peripheral size for spi_host0 in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_SPI_HOST0_BASE_ADDR and TOP_DRAGONFLY_SPI_HOST0_BASE_ADDR + TOP_DRAGONFLY_SPI_HOST0_SIZE_BYTES.

Definition at line 210 of file top_dragonfly.h.

TOP_DRAGONFLY_SRAM_CTRL_MAIN_RAM_BASE_ADDR

#define TOP_DRAGONFLY_SRAM_CTRL_MAIN_RAM_BASE_ADDR   0x10000000u

Memory base address for ram memory on sram_ctrl_main in top dragonfly.

Definition at line 912 of file top_dragonfly.h.

TOP_DRAGONFLY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES

#define TOP_DRAGONFLY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES   0x10000u

Memory size for ram memory on sram_ctrl_main in top dragonfly.

Definition at line 917 of file top_dragonfly.h.

TOP_DRAGONFLY_SRAM_CTRL_MAIN_REGS_BASE_ADDR

#define TOP_DRAGONFLY_SRAM_CTRL_MAIN_REGS_BASE_ADDR   0x211C0000u

Peripheral base address for regs device on sram_ctrl_main in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 578 of file top_dragonfly.h.

TOP_DRAGONFLY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES

#define TOP_DRAGONFLY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES   0x40u

Peripheral size for regs device on sram_ctrl_main in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_SRAM_CTRL_MAIN_REGS_BASE_ADDR and TOP_DRAGONFLY_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_DRAGONFLY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES.

Definition at line 588 of file top_dragonfly.h.

TOP_DRAGONFLY_SRAM_CTRL_MBOX_RAM_BASE_ADDR

#define TOP_DRAGONFLY_SRAM_CTRL_MBOX_RAM_BASE_ADDR   0x11000000u

Memory base address for ram memory on sram_ctrl_mbox in top dragonfly.

Definition at line 922 of file top_dragonfly.h.

TOP_DRAGONFLY_SRAM_CTRL_MBOX_RAM_SIZE_BYTES

#define TOP_DRAGONFLY_SRAM_CTRL_MBOX_RAM_SIZE_BYTES   0x1000u

Memory size for ram memory on sram_ctrl_mbox in top dragonfly.

Definition at line 927 of file top_dragonfly.h.

TOP_DRAGONFLY_SRAM_CTRL_MBOX_REGS_BASE_ADDR

#define TOP_DRAGONFLY_SRAM_CTRL_MBOX_REGS_BASE_ADDR   0x211D0000u

Peripheral base address for regs device on sram_ctrl_mbox in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 596 of file top_dragonfly.h.

TOP_DRAGONFLY_SRAM_CTRL_MBOX_REGS_SIZE_BYTES

#define TOP_DRAGONFLY_SRAM_CTRL_MBOX_REGS_SIZE_BYTES   0x40u

Peripheral size for regs device on sram_ctrl_mbox in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_SRAM_CTRL_MBOX_REGS_BASE_ADDR and TOP_DRAGONFLY_SRAM_CTRL_MBOX_REGS_BASE_ADDR + TOP_DRAGONFLY_SRAM_CTRL_MBOX_REGS_SIZE_BYTES.

Definition at line 606 of file top_dragonfly.h.

TOP_DRAGONFLY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR

#define TOP_DRAGONFLY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR   0x30600000u

Memory base address for ram memory on sram_ctrl_ret_aon in top dragonfly.

Definition at line 902 of file top_dragonfly.h.

TOP_DRAGONFLY_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES

#define TOP_DRAGONFLY_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES   0x1000u

Memory size for ram memory on sram_ctrl_ret_aon in top dragonfly.

Definition at line 907 of file top_dragonfly.h.

TOP_DRAGONFLY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR

#define TOP_DRAGONFLY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR   0x30500000u

Peripheral base address for regs device on sram_ctrl_ret_aon in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 344 of file top_dragonfly.h.

TOP_DRAGONFLY_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES

#define TOP_DRAGONFLY_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES   0x40u

Peripheral size for regs device on sram_ctrl_ret_aon in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR and TOP_DRAGONFLY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR + TOP_DRAGONFLY_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES.

Definition at line 354 of file top_dragonfly.h.

TOP_DRAGONFLY_UART0_BASE_ADDR

#define TOP_DRAGONFLY_UART0_BASE_ADDR   0x30010000u

Peripheral base address for uart0 in top dragonfly.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 38 of file top_dragonfly.h.

TOP_DRAGONFLY_UART0_SIZE_BYTES

#define TOP_DRAGONFLY_UART0_SIZE_BYTES   0x40u

Peripheral size for uart0 in top dragonfly.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DRAGONFLY_UART0_BASE_ADDR and TOP_DRAGONFLY_UART0_BASE_ADDR + TOP_DRAGONFLY_UART0_SIZE_BYTES.

Definition at line 48 of file top_dragonfly.h.

Typedef Documentation

top_dragonfly_alert_id_t

typedef enum top_dragonfly_alert_id top_dragonfly_alert_id_t

Alert Handler Alert Source.

Enumeration of all Alert Handler Alert Sources. The alert sources belonging to the same peripheral are guaranteed to be consecutive.

top_dragonfly_alert_peripheral_t

typedef enum top_dragonfly_alert_peripheral top_dragonfly_alert_peripheral_t

Alert Handler Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding alert.

top_dragonfly_gateable_clocks_t

typedef enum top_dragonfly_gateable_clocks top_dragonfly_gateable_clocks_t

Clock Manager Software-Controlled ("Gated") Clocks.

The Software has full control over these clocks.

top_dragonfly_hintable_clocks_t

typedef enum top_dragonfly_hintable_clocks top_dragonfly_hintable_clocks_t

Clock Manager Software-Hinted Clocks.

The Software has partial control over these clocks. It can ask them to stop, but the clock manager is in control of whether the clock actually is stopped.

top_dragonfly_plic_irq_id_t

typedef enum top_dragonfly_plic_irq_id top_dragonfly_plic_irq_id_t

PLIC Interrupt Source.

Enumeration of all PLIC interrupt sources. The interrupt sources belonging to the same peripheral are guaranteed to be consecutive.

top_dragonfly_plic_peripheral_t

typedef enum top_dragonfly_plic_peripheral top_dragonfly_plic_peripheral_t

PLIC Interrupt Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding interrupt.

top_dragonfly_plic_target_t

typedef enum top_dragonfly_plic_target top_dragonfly_plic_target_t

PLIC Interrupt Target.

Enumeration used to determine which set of IE, CC, threshold registers to access for a given interrupt target.

Enumeration Type Documentation

top_dragonfly_alert_id

enum top_dragonfly_alert_id

Alert Handler Alert Source.

Enumeration of all Alert Handler Alert Sources. The alert sources belonging to the same peripheral are guaranteed to be consecutive.

Enumerator
kTopDragonflyAlertIdUart0FatalFault	uart0_fatal_fault
kTopDragonflyAlertIdGpioFatalFault	gpio_fatal_fault
kTopDragonflyAlertIdSpiDeviceFatalFault	spi_device_fatal_fault
kTopDragonflyAlertIdI2c0FatalFault	i2c0_fatal_fault
kTopDragonflyAlertIdRvTimerFatalFault	rv_timer_fatal_fault
kTopDragonflyAlertIdOtpCtrlFatalMacroError	otp_ctrl_fatal_macro_error
kTopDragonflyAlertIdOtpCtrlFatalCheckError	otp_ctrl_fatal_check_error
kTopDragonflyAlertIdOtpCtrlFatalBusIntegError	otp_ctrl_fatal_bus_integ_error
kTopDragonflyAlertIdOtpCtrlFatalPrimOtpAlert	otp_ctrl_fatal_prim_otp_alert
kTopDragonflyAlertIdOtpCtrlRecovPrimOtpAlert	otp_ctrl_recov_prim_otp_alert
kTopDragonflyAlertIdLcCtrlFatalProgError	lc_ctrl_fatal_prog_error
kTopDragonflyAlertIdLcCtrlFatalStateError	lc_ctrl_fatal_state_error
kTopDragonflyAlertIdLcCtrlFatalBusIntegError	lc_ctrl_fatal_bus_integ_error
kTopDragonflyAlertIdSpiHost0FatalFault	spi_host0_fatal_fault
kTopDragonflyAlertIdPwrmgrAonFatalFault	pwrmgr_aon_fatal_fault
kTopDragonflyAlertIdRstmgrAonFatalFault	rstmgr_aon_fatal_fault
kTopDragonflyAlertIdRstmgrAonFatalCnstyFault	rstmgr_aon_fatal_cnsty_fault
kTopDragonflyAlertIdClkmgrAonRecovFault	clkmgr_aon_recov_fault
kTopDragonflyAlertIdClkmgrAonFatalFault	clkmgr_aon_fatal_fault
kTopDragonflyAlertIdPinmuxAonFatalFault	pinmux_aon_fatal_fault
kTopDragonflyAlertIdAonTimerAonFatalFault	aon_timer_aon_fatal_fault
kTopDragonflyAlertIdSocProxyFatalAlertIntg	soc_proxy_fatal_alert_intg
kTopDragonflyAlertIdSramCtrlRetAonFatalError	sram_ctrl_ret_aon_fatal_error
kTopDragonflyAlertIdRvDmFatalFault	rv_dm_fatal_fault
kTopDragonflyAlertIdRvPlicFatalFault	rv_plic_fatal_fault
kTopDragonflyAlertIdAccFatal	acc_fatal
kTopDragonflyAlertIdAccRecov	acc_recov
kTopDragonflyAlertIdAesRecovCtrlUpdateErr	aes_recov_ctrl_update_err
kTopDragonflyAlertIdAesFatalFault	aes_fatal_fault
kTopDragonflyAlertIdHmacFatalFault	hmac_fatal_fault
kTopDragonflyAlertIdKmacRecovOperationErr	kmac_recov_operation_err
kTopDragonflyAlertIdKmacFatalFaultErr	kmac_fatal_fault_err
kTopDragonflyAlertIdKeymgrDpeRecovOperationErr	keymgr_dpe_recov_operation_err
kTopDragonflyAlertIdKeymgrDpeFatalFaultErr	keymgr_dpe_fatal_fault_err
kTopDragonflyAlertIdCsrngRecovAlert	csrng_recov_alert
kTopDragonflyAlertIdCsrngFatalAlert	csrng_fatal_alert
kTopDragonflyAlertIdEntropySrcRecovAlert	entropy_src_recov_alert
kTopDragonflyAlertIdEntropySrcFatalAlert	entropy_src_fatal_alert
kTopDragonflyAlertIdEdn0RecovAlert	edn0_recov_alert
kTopDragonflyAlertIdEdn0FatalAlert	edn0_fatal_alert
kTopDragonflyAlertIdEdn1RecovAlert	edn1_recov_alert
kTopDragonflyAlertIdEdn1FatalAlert	edn1_fatal_alert
kTopDragonflyAlertIdSramCtrlMainFatalError	sram_ctrl_main_fatal_error
kTopDragonflyAlertIdSramCtrlMboxFatalError	sram_ctrl_mbox_fatal_error
kTopDragonflyAlertIdRomCtrl0Fatal	rom_ctrl0_fatal
kTopDragonflyAlertIdRomCtrl1Fatal	rom_ctrl1_fatal
kTopDragonflyAlertIdDmaFatalFault	dma_fatal_fault
kTopDragonflyAlertIdMbx0FatalFault	mbx0_fatal_fault
kTopDragonflyAlertIdMbx0RecovFault	mbx0_recov_fault
kTopDragonflyAlertIdMbx1FatalFault	mbx1_fatal_fault
kTopDragonflyAlertIdMbx1RecovFault	mbx1_recov_fault
kTopDragonflyAlertIdMbx2FatalFault	mbx2_fatal_fault
kTopDragonflyAlertIdMbx2RecovFault	mbx2_recov_fault
kTopDragonflyAlertIdMbx3FatalFault	mbx3_fatal_fault
kTopDragonflyAlertIdMbx3RecovFault	mbx3_recov_fault
kTopDragonflyAlertIdMbx4FatalFault	mbx4_fatal_fault
kTopDragonflyAlertIdMbx4RecovFault	mbx4_recov_fault
kTopDragonflyAlertIdMbx5FatalFault	mbx5_fatal_fault
kTopDragonflyAlertIdMbx5RecovFault	mbx5_recov_fault
kTopDragonflyAlertIdMbx6FatalFault	mbx6_fatal_fault
kTopDragonflyAlertIdMbx6RecovFault	mbx6_recov_fault
kTopDragonflyAlertIdMbxJtagFatalFault	mbx_jtag_fatal_fault
kTopDragonflyAlertIdMbxJtagRecovFault	mbx_jtag_recov_fault
kTopDragonflyAlertIdMbxPcie0FatalFault	mbx_pcie0_fatal_fault
kTopDragonflyAlertIdMbxPcie0RecovFault	mbx_pcie0_recov_fault
kTopDragonflyAlertIdMbxPcie1FatalFault	mbx_pcie1_fatal_fault
kTopDragonflyAlertIdMbxPcie1RecovFault	mbx_pcie1_recov_fault
kTopDragonflyAlertIdSocDbgCtrlFatalFault	soc_dbg_ctrl_fatal_fault
kTopDragonflyAlertIdSocDbgCtrlRecovCtrlUpdateErr	soc_dbg_ctrl_recov_ctrl_update_err
kTopDragonflyAlertIdRaclCtrlFatalFault	racl_ctrl_fatal_fault
kTopDragonflyAlertIdRaclCtrlRecovCtrlUpdateErr	racl_ctrl_recov_ctrl_update_err
kTopDragonflyAlertIdAcRangeCheckRecovCtrlUpdateErr	ac_range_check_recov_ctrl_update_err
kTopDragonflyAlertIdAcRangeCheckFatalFault	ac_range_check_fatal_fault
kTopDragonflyAlertIdRvCoreIbexFatalSwErr	rv_core_ibex_fatal_sw_err
kTopDragonflyAlertIdRvCoreIbexRecovSwErr	rv_core_ibex_recov_sw_err
kTopDragonflyAlertIdRvCoreIbexFatalHwErr	rv_core_ibex_fatal_hw_err
kTopDragonflyAlertIdRvCoreIbexRecovHwErr	rv_core_ibex_recov_hw_err

Definition at line 1217 of file top_dragonfly.h.

top_dragonfly_alert_peripheral

enum top_dragonfly_alert_peripheral

Alert Handler Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding alert.

Enumerator
kTopDragonflyAlertPeripheralExternal	External Peripheral.
kTopDragonflyAlertPeripheralUart0	uart0
kTopDragonflyAlertPeripheralGpio	gpio
kTopDragonflyAlertPeripheralSpiDevice	spi_device
kTopDragonflyAlertPeripheralI2c0	i2c0
kTopDragonflyAlertPeripheralRvTimer	rv_timer
kTopDragonflyAlertPeripheralOtpCtrl	otp_ctrl
kTopDragonflyAlertPeripheralLcCtrl	lc_ctrl
kTopDragonflyAlertPeripheralSpiHost0	spi_host0
kTopDragonflyAlertPeripheralPwrmgrAon	pwrmgr_aon
kTopDragonflyAlertPeripheralRstmgrAon	rstmgr_aon
kTopDragonflyAlertPeripheralClkmgrAon	clkmgr_aon
kTopDragonflyAlertPeripheralPinmuxAon	pinmux_aon
kTopDragonflyAlertPeripheralAonTimerAon	aon_timer_aon
kTopDragonflyAlertPeripheralSocProxy	soc_proxy
kTopDragonflyAlertPeripheralSramCtrlRetAon	sram_ctrl_ret_aon
kTopDragonflyAlertPeripheralRvDm	rv_dm
kTopDragonflyAlertPeripheralRvPlic	rv_plic
kTopDragonflyAlertPeripheralAcc	acc
kTopDragonflyAlertPeripheralAes	aes
kTopDragonflyAlertPeripheralHmac	hmac
kTopDragonflyAlertPeripheralKmac	kmac
kTopDragonflyAlertPeripheralKeymgrDpe	keymgr_dpe
kTopDragonflyAlertPeripheralCsrng	csrng
kTopDragonflyAlertPeripheralEntropySrc	entropy_src
kTopDragonflyAlertPeripheralEdn0	edn0
kTopDragonflyAlertPeripheralEdn1	edn1
kTopDragonflyAlertPeripheralSramCtrlMain	sram_ctrl_main
kTopDragonflyAlertPeripheralSramCtrlMbox	sram_ctrl_mbox
kTopDragonflyAlertPeripheralRomCtrl0	rom_ctrl0
kTopDragonflyAlertPeripheralRomCtrl1	rom_ctrl1
kTopDragonflyAlertPeripheralDma	dma
kTopDragonflyAlertPeripheralMbx0	mbx0
kTopDragonflyAlertPeripheralMbx1	mbx1
kTopDragonflyAlertPeripheralMbx2	mbx2
kTopDragonflyAlertPeripheralMbx3	mbx3
kTopDragonflyAlertPeripheralMbx4	mbx4
kTopDragonflyAlertPeripheralMbx5	mbx5
kTopDragonflyAlertPeripheralMbx6	mbx6
kTopDragonflyAlertPeripheralMbxJtag	mbx_jtag
kTopDragonflyAlertPeripheralMbxPcie0	mbx_pcie0
kTopDragonflyAlertPeripheralMbxPcie1	mbx_pcie1
kTopDragonflyAlertPeripheralSocDbgCtrl	soc_dbg_ctrl
kTopDragonflyAlertPeripheralRaclCtrl	racl_ctrl
kTopDragonflyAlertPeripheralAcRangeCheck	ac_range_check
kTopDragonflyAlertPeripheralRvCoreIbex	rv_core_ibex

Definition at line 1161 of file top_dragonfly.h.

top_dragonfly_direct_pads

enum top_dragonfly_direct_pads

Dedicated Pad Selects.

Definition at line 1385 of file top_dragonfly.h.

top_dragonfly_gateable_clocks

enum top_dragonfly_gateable_clocks

Clock Manager Software-Controlled ("Gated") Clocks.

The Software has full control over these clocks.

Enumerator
kTopDragonflyGateableClocksIoPeri	Clock clk_io_peri in group peri.

Definition at line 1515 of file top_dragonfly.h.

top_dragonfly_hintable_clocks

enum top_dragonfly_hintable_clocks

Clock Manager Software-Hinted Clocks.

The Software has partial control over these clocks. It can ask them to stop, but the clock manager is in control of whether the clock actually is stopped.

Enumerator
kTopDragonflyHintableClocksMainAcc	Clock clk_main_acc in group trans.
kTopDragonflyHintableClocksMainAes	Clock clk_main_aes in group trans.
kTopDragonflyHintableClocksMainHmac	Clock clk_main_hmac in group trans.
kTopDragonflyHintableClocksMainKmac	Clock clk_main_kmac in group trans.

Definition at line 1526 of file top_dragonfly.h.

top_dragonfly_muxed_pads

enum top_dragonfly_muxed_pads

Muxed Pad Selects.

Definition at line 1465 of file top_dragonfly.h.

top_dragonfly_pinmux_insel

enum top_dragonfly_pinmux_insel

Pinmux MIO Input Selector.

Enumerator
kTopDragonflyPinmuxInselConstantZero	Tie constantly to zero.
kTopDragonflyPinmuxInselConstantOne	Tie constantly to one.
kTopDragonflyPinmuxInselMio0	MIO Pad 0.
kTopDragonflyPinmuxInselMio1	MIO Pad 1.
kTopDragonflyPinmuxInselMio2	MIO Pad 2.
kTopDragonflyPinmuxInselMio3	MIO Pad 3.
kTopDragonflyPinmuxInselMio4	MIO Pad 4.
kTopDragonflyPinmuxInselMio5	MIO Pad 5.
kTopDragonflyPinmuxInselMio6	MIO Pad 6.
kTopDragonflyPinmuxInselMio7	MIO Pad 7.
kTopDragonflyPinmuxInselMio8	MIO Pad 8.
kTopDragonflyPinmuxInselMio9	MIO Pad 9.
kTopDragonflyPinmuxInselMio10	MIO Pad 10.
kTopDragonflyPinmuxInselMio11	MIO Pad 11.

Definition at line 1330 of file top_dragonfly.h.

top_dragonfly_pinmux_mio_out

enum top_dragonfly_pinmux_mio_out

Pinmux MIO Output.

Enumerator
kTopDragonflyPinmuxMioOutMio0	MIO Pad 0.
kTopDragonflyPinmuxMioOutMio1	MIO Pad 1.
kTopDragonflyPinmuxMioOutMio2	MIO Pad 2.
kTopDragonflyPinmuxMioOutMio3	MIO Pad 3.
kTopDragonflyPinmuxMioOutMio4	MIO Pad 4.
kTopDragonflyPinmuxMioOutMio5	MIO Pad 5.
kTopDragonflyPinmuxMioOutMio6	MIO Pad 6.
kTopDragonflyPinmuxMioOutMio7	MIO Pad 7.
kTopDragonflyPinmuxMioOutMio8	MIO Pad 8.
kTopDragonflyPinmuxMioOutMio9	MIO Pad 9.
kTopDragonflyPinmuxMioOutMio10	MIO Pad 10.
kTopDragonflyPinmuxMioOutMio11	MIO Pad 11.

Definition at line 1351 of file top_dragonfly.h.

top_dragonfly_pinmux_outsel

enum top_dragonfly_pinmux_outsel

Pinmux Peripheral Output Selector.

Enumerator
kTopDragonflyPinmuxOutselConstantZero	Tie constantly to zero.
kTopDragonflyPinmuxOutselConstantOne	Tie constantly to one.
kTopDragonflyPinmuxOutselConstantHighZ	Tie constantly to high-Z.
kTopDragonflyPinmuxOutselSocProxySocGpo12	Peripheral Output 0.
kTopDragonflyPinmuxOutselSocProxySocGpo13	Peripheral Output 1.
kTopDragonflyPinmuxOutselSocProxySocGpo14	Peripheral Output 2.
kTopDragonflyPinmuxOutselSocProxySocGpo15	Peripheral Output 3.
kTopDragonflyPinmuxOutselOtpMacroTest0	Peripheral Output 4.

Definition at line 1370 of file top_dragonfly.h.

top_dragonfly_pinmux_peripheral_in

enum top_dragonfly_pinmux_peripheral_in

Pinmux Peripheral Input.

Enumerator
kTopDragonflyPinmuxPeripheralInSocProxySocGpi12	Peripheral Input 0.
kTopDragonflyPinmuxPeripheralInSocProxySocGpi13	Peripheral Input 1.
kTopDragonflyPinmuxPeripheralInSocProxySocGpi14	Peripheral Input 2.
kTopDragonflyPinmuxPeripheralInSocProxySocGpi15	Peripheral Input 3.

Definition at line 1319 of file top_dragonfly.h.

top_dragonfly_plic_irq_id

enum top_dragonfly_plic_irq_id

PLIC Interrupt Source.

Enumeration of all PLIC interrupt sources. The interrupt sources belonging to the same peripheral are guaranteed to be consecutive.

Enumerator
kTopDragonflyPlicIrqIdNone	No Interrupt.
kTopDragonflyPlicIrqIdUart0TxWatermark	uart0_tx_watermark
kTopDragonflyPlicIrqIdUart0RxWatermark	uart0_rx_watermark
kTopDragonflyPlicIrqIdUart0TxDone	uart0_tx_done
kTopDragonflyPlicIrqIdUart0RxOverflow	uart0_rx_overflow
kTopDragonflyPlicIrqIdUart0RxFrameErr	uart0_rx_frame_err
kTopDragonflyPlicIrqIdUart0RxBreakErr	uart0_rx_break_err
kTopDragonflyPlicIrqIdUart0RxTimeout	uart0_rx_timeout
kTopDragonflyPlicIrqIdUart0RxParityErr	uart0_rx_parity_err
kTopDragonflyPlicIrqIdUart0TxEmpty	uart0_tx_empty
kTopDragonflyPlicIrqIdGpioGpio0	gpio_gpio 0
kTopDragonflyPlicIrqIdGpioGpio1	gpio_gpio 1
kTopDragonflyPlicIrqIdGpioGpio2	gpio_gpio 2
kTopDragonflyPlicIrqIdGpioGpio3	gpio_gpio 3
kTopDragonflyPlicIrqIdGpioGpio4	gpio_gpio 4
kTopDragonflyPlicIrqIdGpioGpio5	gpio_gpio 5
kTopDragonflyPlicIrqIdGpioGpio6	gpio_gpio 6
kTopDragonflyPlicIrqIdGpioGpio7	gpio_gpio 7
kTopDragonflyPlicIrqIdGpioGpio8	gpio_gpio 8
kTopDragonflyPlicIrqIdGpioGpio9	gpio_gpio 9
kTopDragonflyPlicIrqIdGpioGpio10	gpio_gpio 10
kTopDragonflyPlicIrqIdGpioGpio11	gpio_gpio 11
kTopDragonflyPlicIrqIdGpioGpio12	gpio_gpio 12
kTopDragonflyPlicIrqIdGpioGpio13	gpio_gpio 13
kTopDragonflyPlicIrqIdGpioGpio14	gpio_gpio 14
kTopDragonflyPlicIrqIdGpioGpio15	gpio_gpio 15
kTopDragonflyPlicIrqIdGpioGpio16	gpio_gpio 16
kTopDragonflyPlicIrqIdGpioGpio17	gpio_gpio 17
kTopDragonflyPlicIrqIdGpioGpio18	gpio_gpio 18
kTopDragonflyPlicIrqIdGpioGpio19	gpio_gpio 19
kTopDragonflyPlicIrqIdGpioGpio20	gpio_gpio 20
kTopDragonflyPlicIrqIdGpioGpio21	gpio_gpio 21
kTopDragonflyPlicIrqIdGpioGpio22	gpio_gpio 22
kTopDragonflyPlicIrqIdGpioGpio23	gpio_gpio 23
kTopDragonflyPlicIrqIdGpioGpio24	gpio_gpio 24
kTopDragonflyPlicIrqIdGpioGpio25	gpio_gpio 25
kTopDragonflyPlicIrqIdGpioGpio26	gpio_gpio 26
kTopDragonflyPlicIrqIdGpioGpio27	gpio_gpio 27
kTopDragonflyPlicIrqIdGpioGpio28	gpio_gpio 28
kTopDragonflyPlicIrqIdGpioGpio29	gpio_gpio 29
kTopDragonflyPlicIrqIdGpioGpio30	gpio_gpio 30
kTopDragonflyPlicIrqIdGpioGpio31	gpio_gpio 31
kTopDragonflyPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty	spi_device_upload_cmdfifo_not_empty
kTopDragonflyPlicIrqIdSpiDeviceUploadPayloadNotEmpty	spi_device_upload_payload_not_empty
kTopDragonflyPlicIrqIdSpiDeviceUploadPayloadOverflow	spi_device_upload_payload_overflow
kTopDragonflyPlicIrqIdSpiDeviceReadbufWatermark	spi_device_readbuf_watermark
kTopDragonflyPlicIrqIdSpiDeviceReadbufFlip	spi_device_readbuf_flip
kTopDragonflyPlicIrqIdSpiDeviceTpmHeaderNotEmpty	spi_device_tpm_header_not_empty
kTopDragonflyPlicIrqIdSpiDeviceTpmRdfifoCmdEnd	spi_device_tpm_rdfifo_cmd_end
kTopDragonflyPlicIrqIdSpiDeviceTpmRdfifoDrop	spi_device_tpm_rdfifo_drop
kTopDragonflyPlicIrqIdI2c0FmtThreshold	i2c0_fmt_threshold
kTopDragonflyPlicIrqIdI2c0RxThreshold	i2c0_rx_threshold
kTopDragonflyPlicIrqIdI2c0AcqThreshold	i2c0_acq_threshold
kTopDragonflyPlicIrqIdI2c0RxOverflow	i2c0_rx_overflow
kTopDragonflyPlicIrqIdI2c0ControllerHalt	i2c0_controller_halt
kTopDragonflyPlicIrqIdI2c0SclInterference	i2c0_scl_interference
kTopDragonflyPlicIrqIdI2c0SdaInterference	i2c0_sda_interference
kTopDragonflyPlicIrqIdI2c0StretchTimeout	i2c0_stretch_timeout
kTopDragonflyPlicIrqIdI2c0SdaUnstable	i2c0_sda_unstable
kTopDragonflyPlicIrqIdI2c0CmdComplete	i2c0_cmd_complete
kTopDragonflyPlicIrqIdI2c0TxStretch	i2c0_tx_stretch
kTopDragonflyPlicIrqIdI2c0TxThreshold	i2c0_tx_threshold
kTopDragonflyPlicIrqIdI2c0AcqStretch	i2c0_acq_stretch
kTopDragonflyPlicIrqIdI2c0UnexpStop	i2c0_unexp_stop
kTopDragonflyPlicIrqIdI2c0HostTimeout	i2c0_host_timeout
kTopDragonflyPlicIrqIdRvTimerTimerExpiredHart0Timer0	rv_timer_timer_expired_hart0_timer0
kTopDragonflyPlicIrqIdOtpCtrlOtpOperationDone	otp_ctrl_otp_operation_done
kTopDragonflyPlicIrqIdOtpCtrlOtpError	otp_ctrl_otp_error
kTopDragonflyPlicIrqIdAlertHandlerClassa	alert_handler_classa
kTopDragonflyPlicIrqIdAlertHandlerClassb	alert_handler_classb
kTopDragonflyPlicIrqIdAlertHandlerClassc	alert_handler_classc
kTopDragonflyPlicIrqIdAlertHandlerClassd	alert_handler_classd
kTopDragonflyPlicIrqIdSpiHost0Error	spi_host0_error
kTopDragonflyPlicIrqIdSpiHost0SpiEvent	spi_host0_spi_event
kTopDragonflyPlicIrqIdPwrmgrAonWakeup	pwrmgr_aon_wakeup
kTopDragonflyPlicIrqIdAonTimerAonWkupTimerExpired	aon_timer_aon_wkup_timer_expired
kTopDragonflyPlicIrqIdAonTimerAonWdogTimerBark	aon_timer_aon_wdog_timer_bark
kTopDragonflyPlicIrqIdAccDone	acc_done
kTopDragonflyPlicIrqIdHmacHmacDone	hmac_hmac_done
kTopDragonflyPlicIrqIdHmacFifoEmpty	hmac_fifo_empty
kTopDragonflyPlicIrqIdHmacHmacErr	hmac_hmac_err
kTopDragonflyPlicIrqIdKmacKmacDone	kmac_kmac_done
kTopDragonflyPlicIrqIdKmacFifoEmpty	kmac_fifo_empty
kTopDragonflyPlicIrqIdKmacKmacErr	kmac_kmac_err
kTopDragonflyPlicIrqIdKeymgrDpeOpDone	keymgr_dpe_op_done
kTopDragonflyPlicIrqIdCsrngCsCmdReqDone	csrng_cs_cmd_req_done
kTopDragonflyPlicIrqIdCsrngCsEntropyReq	csrng_cs_entropy_req
kTopDragonflyPlicIrqIdCsrngCsHwInstExc	csrng_cs_hw_inst_exc
kTopDragonflyPlicIrqIdCsrngCsFatalErr	csrng_cs_fatal_err
kTopDragonflyPlicIrqIdEntropySrcEsEntropyValid	entropy_src_es_entropy_valid
kTopDragonflyPlicIrqIdEntropySrcEsHealthTestFailed	entropy_src_es_health_test_failed
kTopDragonflyPlicIrqIdEntropySrcEsObserveFifoReady	entropy_src_es_observe_fifo_ready
kTopDragonflyPlicIrqIdEntropySrcEsFatalErr	entropy_src_es_fatal_err
kTopDragonflyPlicIrqIdEdn0EdnCmdReqDone	edn0_edn_cmd_req_done
kTopDragonflyPlicIrqIdEdn0EdnFatalErr	edn0_edn_fatal_err
kTopDragonflyPlicIrqIdEdn1EdnCmdReqDone	edn1_edn_cmd_req_done
kTopDragonflyPlicIrqIdEdn1EdnFatalErr	edn1_edn_fatal_err
kTopDragonflyPlicIrqIdDmaDmaDone	dma_dma_done
kTopDragonflyPlicIrqIdDmaDmaChunkDone	dma_dma_chunk_done
kTopDragonflyPlicIrqIdDmaDmaError	dma_dma_error
kTopDragonflyPlicIrqIdMbx0MbxReady	mbx0_mbx_ready
kTopDragonflyPlicIrqIdMbx0MbxAbort	mbx0_mbx_abort
kTopDragonflyPlicIrqIdMbx0MbxError	mbx0_mbx_error
kTopDragonflyPlicIrqIdMbx1MbxReady	mbx1_mbx_ready
kTopDragonflyPlicIrqIdMbx1MbxAbort	mbx1_mbx_abort
kTopDragonflyPlicIrqIdMbx1MbxError	mbx1_mbx_error
kTopDragonflyPlicIrqIdMbx2MbxReady	mbx2_mbx_ready
kTopDragonflyPlicIrqIdMbx2MbxAbort	mbx2_mbx_abort
kTopDragonflyPlicIrqIdMbx2MbxError	mbx2_mbx_error
kTopDragonflyPlicIrqIdMbx3MbxReady	mbx3_mbx_ready
kTopDragonflyPlicIrqIdMbx3MbxAbort	mbx3_mbx_abort
kTopDragonflyPlicIrqIdMbx3MbxError	mbx3_mbx_error
kTopDragonflyPlicIrqIdMbx4MbxReady	mbx4_mbx_ready
kTopDragonflyPlicIrqIdMbx4MbxAbort	mbx4_mbx_abort
kTopDragonflyPlicIrqIdMbx4MbxError	mbx4_mbx_error
kTopDragonflyPlicIrqIdMbx5MbxReady	mbx5_mbx_ready
kTopDragonflyPlicIrqIdMbx5MbxAbort	mbx5_mbx_abort
kTopDragonflyPlicIrqIdMbx5MbxError	mbx5_mbx_error
kTopDragonflyPlicIrqIdMbx6MbxReady	mbx6_mbx_ready
kTopDragonflyPlicIrqIdMbx6MbxAbort	mbx6_mbx_abort
kTopDragonflyPlicIrqIdMbx6MbxError	mbx6_mbx_error
kTopDragonflyPlicIrqIdMbxJtagMbxReady	mbx_jtag_mbx_ready
kTopDragonflyPlicIrqIdMbxJtagMbxAbort	mbx_jtag_mbx_abort
kTopDragonflyPlicIrqIdMbxJtagMbxError	mbx_jtag_mbx_error
kTopDragonflyPlicIrqIdMbxPcie0MbxReady	mbx_pcie0_mbx_ready
kTopDragonflyPlicIrqIdMbxPcie0MbxAbort	mbx_pcie0_mbx_abort
kTopDragonflyPlicIrqIdMbxPcie0MbxError	mbx_pcie0_mbx_error
kTopDragonflyPlicIrqIdMbxPcie1MbxReady	mbx_pcie1_mbx_ready
kTopDragonflyPlicIrqIdMbxPcie1MbxAbort	mbx_pcie1_mbx_abort
kTopDragonflyPlicIrqIdMbxPcie1MbxError	mbx_pcie1_mbx_error
kTopDragonflyPlicIrqIdRaclCtrlRaclError	racl_ctrl_racl_error
kTopDragonflyPlicIrqIdAcRangeCheckDenyCntReached	ac_range_check_deny_cnt_reached

Definition at line 998 of file top_dragonfly.h.

top_dragonfly_plic_peripheral

enum top_dragonfly_plic_peripheral

PLIC Interrupt Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding interrupt.

Enumerator
kTopDragonflyPlicPeripheralUnknown	Unknown Peripheral.
kTopDragonflyPlicPeripheralUart0	uart0
kTopDragonflyPlicPeripheralGpio	gpio
kTopDragonflyPlicPeripheralSpiDevice	spi_device
kTopDragonflyPlicPeripheralI2c0	i2c0
kTopDragonflyPlicPeripheralRvTimer	rv_timer
kTopDragonflyPlicPeripheralOtpCtrl	otp_ctrl
kTopDragonflyPlicPeripheralAlertHandler	alert_handler
kTopDragonflyPlicPeripheralSpiHost0	spi_host0
kTopDragonflyPlicPeripheralPwrmgrAon	pwrmgr_aon
kTopDragonflyPlicPeripheralAonTimerAon	aon_timer_aon
kTopDragonflyPlicPeripheralAcc	acc
kTopDragonflyPlicPeripheralHmac	hmac
kTopDragonflyPlicPeripheralKmac	kmac
kTopDragonflyPlicPeripheralKeymgrDpe	keymgr_dpe
kTopDragonflyPlicPeripheralCsrng	csrng
kTopDragonflyPlicPeripheralEntropySrc	entropy_src
kTopDragonflyPlicPeripheralEdn0	edn0
kTopDragonflyPlicPeripheralEdn1	edn1
kTopDragonflyPlicPeripheralDma	dma
kTopDragonflyPlicPeripheralMbx0	mbx0
kTopDragonflyPlicPeripheralMbx1	mbx1
kTopDragonflyPlicPeripheralMbx2	mbx2
kTopDragonflyPlicPeripheralMbx3	mbx3
kTopDragonflyPlicPeripheralMbx4	mbx4
kTopDragonflyPlicPeripheralMbx5	mbx5
kTopDragonflyPlicPeripheralMbx6	mbx6
kTopDragonflyPlicPeripheralMbxJtag	mbx_jtag
kTopDragonflyPlicPeripheralMbxPcie0	mbx_pcie0
kTopDragonflyPlicPeripheralMbxPcie1	mbx_pcie1
kTopDragonflyPlicPeripheralRaclCtrl	racl_ctrl
kTopDragonflyPlicPeripheralAcRangeCheck	ac_range_check

Definition at line 956 of file top_dragonfly.h.

top_dragonfly_plic_target

enum top_dragonfly_plic_target

PLIC Interrupt Target.

Enumeration used to determine which set of IE, CC, threshold registers to access for a given interrupt target.

Enumerator
kTopDragonflyPlicTargetIbex0	Ibex Core 0.

Definition at line 1149 of file top_dragonfly.h.

top_dragonfly_power_manager_reset_requests

enum top_dragonfly_power_manager_reset_requests

Power Manager Reset Request Signals.

Definition at line 1504 of file top_dragonfly.h.

top_dragonfly_power_manager_wake_ups

enum top_dragonfly_power_manager_wake_ups

Power Manager Wakeup Signals.

Definition at line 1484 of file top_dragonfly.h.

top_dragonfly_reset_manager_sw_resets

enum top_dragonfly_reset_manager_sw_resets

Reset Manager Software Controlled Resets.

Definition at line 1494 of file top_dragonfly.h.

Variable Documentation

top_dragonfly_alert_for_peripheral

const top_dragonfly_alert_peripheral_t top_dragonfly_alert_for_peripheral[77]

extern

Alert Handler Alert Source to Peripheral Map.

This array is a mapping from top_dragonfly_alert_id_t to top_dragonfly_alert_peripheral_t.

Definition at line 18 of file top_dragonfly.c.

top_dragonfly_plic_interrupt_for_peripheral

const top_dragonfly_plic_peripheral_t top_dragonfly_plic_interrupt_for_peripheral[132]

extern

PLIC Interrupt Source to Peripheral Map.

This array is a mapping from top_dragonfly_plic_irq_id_t to top_dragonfly_plic_peripheral_t.

Definition at line 105 of file top_dragonfly.c.