14void isr_testutils_ac_range_check_isr(
17 dif_ac_range_check_irq_t *irq_serviced) {
22 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
26 top_dragonfly_plic_interrupt_for_peripheral[plic_irq_id];
29 dif_ac_range_check_irq_t irq =
30 (dif_ac_range_check_irq_t)(plic_irq_id -
32 .plic_ac_range_check_start_irq_id);
38 CHECK_DIF_OK(dif_ac_range_check_irq_get_state(
41 "Only ac_range_check IRQ %d expected to fire. Actual IRQ state = %x",
47 CHECK_DIF_OK(dif_ac_range_check_irq_get_type(
50 CHECK_DIF_OK(dif_ac_range_check_irq_acknowledge(
52 }
else if (mute_status_irq) {
53 CHECK_DIF_OK(dif_ac_range_check_irq_set_enabled(
58 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
64 dif_acc_irq_t *irq_serviced) {
69 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
73 top_dragonfly_plic_interrupt_for_peripheral[plic_irq_id];
83 CHECK_DIF_OK(dif_acc_irq_get_state(acc_ctx.
acc, &snapshot));
85 "Only acc IRQ %d expected to fire. Actual IRQ state = %x", irq,
91 CHECK_DIF_OK(dif_acc_irq_get_type(acc_ctx.
acc, irq, &type));
93 CHECK_DIF_OK(dif_acc_irq_acknowledge(acc_ctx.
acc, irq));
97 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
101void isr_testutils_alert_handler_isr(
104 dif_alert_handler_irq_t *irq_serviced) {
109 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
113 top_dragonfly_plic_interrupt_for_peripheral[plic_irq_id];
116 dif_alert_handler_irq_t irq =
117 (dif_alert_handler_irq_t)(plic_irq_id -
119 .plic_alert_handler_start_irq_id);
125 CHECK_DIF_OK(dif_alert_handler_irq_get_state(
128 "Only alert_handler IRQ %d expected to fire. Actual IRQ state = %x",
134 CHECK_DIF_OK(dif_alert_handler_irq_get_type(alert_handler_ctx.
alert_handler,
137 CHECK_DIF_OK(dif_alert_handler_irq_acknowledge(
142 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
146void isr_testutils_aon_timer_isr(
149 dif_aon_timer_irq_t *irq_serviced) {
154 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
158 top_dragonfly_plic_interrupt_for_peripheral[plic_irq_id];
161 dif_aon_timer_irq_t irq =
162 (dif_aon_timer_irq_t)(plic_irq_id -
170 dif_aon_timer_irq_get_state(aon_timer_ctx.
aon_timer, &snapshot));
172 "Only aon_timer IRQ %d expected to fire. Actual IRQ state = %x", irq,
178 CHECK_DIF_OK(dif_aon_timer_irq_get_type(aon_timer_ctx.
aon_timer, irq, &type));
180 CHECK_DIF_OK(dif_aon_timer_irq_acknowledge(aon_timer_ctx.
aon_timer, irq));
184 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
188void isr_testutils_csrng_isr(
191 dif_csrng_irq_t *irq_serviced) {
196 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
200 top_dragonfly_plic_interrupt_for_peripheral[plic_irq_id];
203 dif_csrng_irq_t irq =
210 CHECK_DIF_OK(dif_csrng_irq_get_state(csrng_ctx.
csrng, &snapshot));
212 "Only csrng IRQ %d expected to fire. Actual IRQ state = %x", irq,
218 CHECK_DIF_OK(dif_csrng_irq_get_type(csrng_ctx.
csrng, irq, &type));
220 CHECK_DIF_OK(dif_csrng_irq_acknowledge(csrng_ctx.
csrng, irq));
224 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
229 bool mute_status_irq,
231 dif_dma_irq_t *irq_serviced) {
236 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
240 top_dragonfly_plic_interrupt_for_peripheral[plic_irq_id];
250 CHECK_DIF_OK(dif_dma_irq_get_state(dma_ctx.
dma, &snapshot));
252 "Only dma IRQ %d expected to fire. Actual IRQ state = %x", irq,
258 CHECK_DIF_OK(dif_dma_irq_get_type(dma_ctx.
dma, irq, &type));
260 CHECK_DIF_OK(dif_dma_irq_acknowledge(dma_ctx.
dma, irq));
261 }
else if (mute_status_irq) {
266 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
272 dif_edn_irq_t *irq_serviced) {
277 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
281 top_dragonfly_plic_interrupt_for_peripheral[plic_irq_id];
291 CHECK_DIF_OK(dif_edn_irq_get_state(edn_ctx.
edn, &snapshot));
293 "Only edn IRQ %d expected to fire. Actual IRQ state = %x", irq,
299 CHECK_DIF_OK(dif_edn_irq_get_type(edn_ctx.
edn, irq, &type));
301 CHECK_DIF_OK(dif_edn_irq_acknowledge(edn_ctx.
edn, irq));
305 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
309void isr_testutils_entropy_src_isr(
312 dif_entropy_src_irq_t *irq_serviced) {
317 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
321 top_dragonfly_plic_interrupt_for_peripheral[plic_irq_id];
324 dif_entropy_src_irq_t irq =
325 (dif_entropy_src_irq_t)(plic_irq_id -
333 dif_entropy_src_irq_get_state(entropy_src_ctx.
entropy_src, &snapshot));
335 "Only entropy_src IRQ %d expected to fire. Actual IRQ state = %x",
342 dif_entropy_src_irq_get_type(entropy_src_ctx.
entropy_src, irq, &type));
345 dif_entropy_src_irq_acknowledge(entropy_src_ctx.
entropy_src, irq));
349 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
353void isr_testutils_gpio_isr(
356 dif_gpio_irq_t *irq_serviced) {
361 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
365 top_dragonfly_plic_interrupt_for_peripheral[plic_irq_id];
375 CHECK_DIF_OK(dif_gpio_irq_get_state(gpio_ctx.
gpio, &snapshot));
377 "Only gpio IRQ %d expected to fire. Actual IRQ state = %x", irq,
383 CHECK_DIF_OK(dif_gpio_irq_get_type(gpio_ctx.
gpio, irq, &type));
385 CHECK_DIF_OK(dif_gpio_irq_acknowledge(gpio_ctx.
gpio, irq));
389 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
393void isr_testutils_hmac_isr(
396 dif_hmac_irq_t *irq_serviced) {
401 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
405 top_dragonfly_plic_interrupt_for_peripheral[plic_irq_id];
415 CHECK_DIF_OK(dif_hmac_irq_get_state(hmac_ctx.
hmac, &snapshot));
417 "Only hmac IRQ %d expected to fire. Actual IRQ state = %x", irq,
423 CHECK_DIF_OK(dif_hmac_irq_get_type(hmac_ctx.
hmac, irq, &type));
425 CHECK_DIF_OK(dif_hmac_irq_acknowledge(hmac_ctx.
hmac, irq));
426 }
else if (mute_status_irq) {
432 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
437 bool mute_status_irq,
439 dif_i2c_irq_t *irq_serviced) {
444 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
448 top_dragonfly_plic_interrupt_for_peripheral[plic_irq_id];
458 CHECK_DIF_OK(dif_i2c_irq_get_state(i2c_ctx.
i2c, &snapshot));
460 "Only i2c IRQ %d expected to fire. Actual IRQ state = %x", irq,
466 CHECK_DIF_OK(dif_i2c_irq_get_type(i2c_ctx.
i2c, irq, &type));
468 CHECK_DIF_OK(dif_i2c_irq_acknowledge(i2c_ctx.
i2c, irq));
469 }
else if (mute_status_irq) {
474 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
478void isr_testutils_keymgr_dpe_isr(
481 dif_keymgr_dpe_irq_t *irq_serviced) {
486 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
490 top_dragonfly_plic_interrupt_for_peripheral[plic_irq_id];
493 dif_keymgr_dpe_irq_t irq =
494 (dif_keymgr_dpe_irq_t)(plic_irq_id -
502 dif_keymgr_dpe_irq_get_state(keymgr_dpe_ctx.
keymgr_dpe, &snapshot));
504 "Only keymgr_dpe IRQ %d expected to fire. Actual IRQ state = %x", irq,
511 dif_keymgr_dpe_irq_get_type(keymgr_dpe_ctx.
keymgr_dpe, irq, &type));
514 dif_keymgr_dpe_irq_acknowledge(keymgr_dpe_ctx.
keymgr_dpe, irq));
518 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
522void isr_testutils_kmac_isr(
525 dif_kmac_irq_t *irq_serviced) {
530 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
534 top_dragonfly_plic_interrupt_for_peripheral[plic_irq_id];
544 CHECK_DIF_OK(dif_kmac_irq_get_state(kmac_ctx.
kmac, &snapshot));
546 "Only kmac IRQ %d expected to fire. Actual IRQ state = %x", irq,
552 CHECK_DIF_OK(dif_kmac_irq_get_type(kmac_ctx.
kmac, irq, &type));
554 CHECK_DIF_OK(dif_kmac_irq_acknowledge(kmac_ctx.
kmac, irq));
555 }
else if (mute_status_irq) {
561 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
567 dif_mbx_irq_t *irq_serviced) {
572 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
576 top_dragonfly_plic_interrupt_for_peripheral[plic_irq_id];
586 CHECK_DIF_OK(dif_mbx_irq_get_state(mbx_ctx.
mbx, &snapshot));
588 "Only mbx IRQ %d expected to fire. Actual IRQ state = %x", irq,
594 CHECK_DIF_OK(dif_mbx_irq_get_type(mbx_ctx.
mbx, irq, &type));
596 CHECK_DIF_OK(dif_mbx_irq_acknowledge(mbx_ctx.
mbx, irq));
600 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
604void isr_testutils_otp_ctrl_isr(
607 dif_otp_ctrl_irq_t *irq_serviced) {
612 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
616 top_dragonfly_plic_interrupt_for_peripheral[plic_irq_id];
619 dif_otp_ctrl_irq_t irq =
620 (dif_otp_ctrl_irq_t)(plic_irq_id -
627 CHECK_DIF_OK(dif_otp_ctrl_irq_get_state(otp_ctrl_ctx.
otp_ctrl, &snapshot));
629 "Only otp_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
635 CHECK_DIF_OK(dif_otp_ctrl_irq_get_type(otp_ctrl_ctx.
otp_ctrl, irq, &type));
637 CHECK_DIF_OK(dif_otp_ctrl_irq_acknowledge(otp_ctrl_ctx.
otp_ctrl, irq));
641 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
645void isr_testutils_pwrmgr_isr(
648 dif_pwrmgr_irq_t *irq_serviced) {
653 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
657 top_dragonfly_plic_interrupt_for_peripheral[plic_irq_id];
660 dif_pwrmgr_irq_t irq =
667 CHECK_DIF_OK(dif_pwrmgr_irq_get_state(pwrmgr_ctx.
pwrmgr, &snapshot));
669 "Only pwrmgr IRQ %d expected to fire. Actual IRQ state = %x", irq,
675 CHECK_DIF_OK(dif_pwrmgr_irq_get_type(pwrmgr_ctx.
pwrmgr, irq, &type));
677 CHECK_DIF_OK(dif_pwrmgr_irq_acknowledge(pwrmgr_ctx.
pwrmgr, irq));
681 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
685void isr_testutils_racl_ctrl_isr(
688 dif_racl_ctrl_irq_t *irq_serviced) {
693 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
697 top_dragonfly_plic_interrupt_for_peripheral[plic_irq_id];
700 dif_racl_ctrl_irq_t irq =
701 (dif_racl_ctrl_irq_t)(plic_irq_id -
709 dif_racl_ctrl_irq_get_state(racl_ctrl_ctx.
racl_ctrl, &snapshot));
711 "Only racl_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
717 CHECK_DIF_OK(dif_racl_ctrl_irq_get_type(racl_ctrl_ctx.
racl_ctrl, irq, &type));
719 CHECK_DIF_OK(dif_racl_ctrl_irq_acknowledge(racl_ctrl_ctx.
racl_ctrl, irq));
720 }
else if (mute_status_irq) {
721 CHECK_DIF_OK(dif_racl_ctrl_irq_set_enabled(racl_ctrl_ctx.
racl_ctrl, irq,
726 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
730void isr_testutils_rv_timer_isr(
733 dif_rv_timer_irq_t *irq_serviced) {
738 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
742 top_dragonfly_plic_interrupt_for_peripheral[plic_irq_id];
745 dif_rv_timer_irq_t irq =
746 (dif_rv_timer_irq_t)(plic_irq_id -
753 CHECK_DIF_OK(dif_rv_timer_irq_get_state(rv_timer_ctx.
rv_timer,
756 "Only rv_timer IRQ %d expected to fire. Actual IRQ state = %x", irq,
762 CHECK_DIF_OK(dif_rv_timer_irq_get_type(rv_timer_ctx.
rv_timer, irq, &type));
764 CHECK_DIF_OK(dif_rv_timer_irq_acknowledge(rv_timer_ctx.
rv_timer, irq));
768 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
772void isr_testutils_spi_device_isr(
775 dif_spi_device_irq_t *irq_serviced) {
780 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
784 top_dragonfly_plic_interrupt_for_peripheral[plic_irq_id];
787 dif_spi_device_irq_t irq =
788 (dif_spi_device_irq_t)(plic_irq_id -
796 dif_spi_device_irq_get_state(spi_device_ctx.
spi_device, &snapshot));
798 "Only spi_device IRQ %d expected to fire. Actual IRQ state = %x", irq,
805 dif_spi_device_irq_get_type(spi_device_ctx.
spi_device, irq, &type));
808 dif_spi_device_irq_acknowledge(spi_device_ctx.
spi_device, irq));
809 }
else if (mute_status_irq) {
810 CHECK_DIF_OK(dif_spi_device_irq_set_enabled(spi_device_ctx.
spi_device, irq,
815 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
819void isr_testutils_spi_host_isr(
822 dif_spi_host_irq_t *irq_serviced) {
827 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
831 top_dragonfly_plic_interrupt_for_peripheral[plic_irq_id];
834 dif_spi_host_irq_t irq =
835 (dif_spi_host_irq_t)(plic_irq_id -
842 CHECK_DIF_OK(dif_spi_host_irq_get_state(spi_host_ctx.
spi_host, &snapshot));
844 "Only spi_host IRQ %d expected to fire. Actual IRQ state = %x", irq,
850 CHECK_DIF_OK(dif_spi_host_irq_get_type(spi_host_ctx.
spi_host, irq, &type));
852 CHECK_DIF_OK(dif_spi_host_irq_acknowledge(spi_host_ctx.
spi_host, irq));
853 }
else if (mute_status_irq) {
854 CHECK_DIF_OK(dif_spi_host_irq_set_enabled(spi_host_ctx.
spi_host, irq,
859 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
863void isr_testutils_uart_isr(
866 dif_uart_irq_t *irq_serviced) {
871 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
875 top_dragonfly_plic_interrupt_for_peripheral[plic_irq_id];
885 CHECK_DIF_OK(dif_uart_irq_get_state(uart_ctx.
uart, &snapshot));
887 "Only uart IRQ %d expected to fire. Actual IRQ state = %x", irq,
893 CHECK_DIF_OK(dif_uart_irq_get_type(uart_ctx.
uart, irq, &type));
895 CHECK_DIF_OK(dif_uart_irq_acknowledge(uart_ctx.
uart, irq));
896 }
else if (mute_status_irq) {
902 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,