17 dif_acc_irq_t *irq_serviced) {
22 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
26 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
36 CHECK_DIF_OK(dif_acc_irq_get_state(acc_ctx.
acc, &snapshot));
38 "Only acc IRQ %d expected to fire. Actual IRQ state = %x", irq,
44 CHECK_DIF_OK(dif_acc_irq_get_type(acc_ctx.
acc, irq, &type));
46 CHECK_DIF_OK(dif_acc_irq_acknowledge(acc_ctx.
acc, irq));
50 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
54void isr_testutils_adc_ctrl_isr(
57 dif_adc_ctrl_irq_t *irq_serviced) {
62 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
66 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
69 dif_adc_ctrl_irq_t irq =
70 (dif_adc_ctrl_irq_t)(plic_irq_id -
77 CHECK_DIF_OK(dif_adc_ctrl_irq_get_state(adc_ctrl_ctx.
adc_ctrl, &snapshot));
79 "Only adc_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
86 CHECK_DIF_OK(dif_adc_ctrl_irq_clear_causes(adc_ctrl_ctx.
adc_ctrl,
91 CHECK_DIF_OK(dif_adc_ctrl_irq_get_type(adc_ctrl_ctx.
adc_ctrl, irq, &type));
93 CHECK_DIF_OK(dif_adc_ctrl_irq_acknowledge(adc_ctrl_ctx.
adc_ctrl, irq));
94 }
else if (mute_status_irq) {
95 CHECK_DIF_OK(dif_adc_ctrl_irq_set_enabled(adc_ctrl_ctx.
adc_ctrl, irq,
100 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
104void isr_testutils_alert_handler_isr(
107 dif_alert_handler_irq_t *irq_serviced) {
112 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
116 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
119 dif_alert_handler_irq_t irq =
120 (dif_alert_handler_irq_t)(plic_irq_id -
122 .plic_alert_handler_start_irq_id);
128 CHECK_DIF_OK(dif_alert_handler_irq_get_state(
131 "Only alert_handler IRQ %d expected to fire. Actual IRQ state = %x",
137 CHECK_DIF_OK(dif_alert_handler_irq_get_type(alert_handler_ctx.
alert_handler,
140 CHECK_DIF_OK(dif_alert_handler_irq_acknowledge(
145 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
149void isr_testutils_aon_timer_isr(
152 dif_aon_timer_irq_t *irq_serviced) {
157 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
161 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
164 dif_aon_timer_irq_t irq =
165 (dif_aon_timer_irq_t)(plic_irq_id -
173 dif_aon_timer_irq_get_state(aon_timer_ctx.
aon_timer, &snapshot));
175 "Only aon_timer IRQ %d expected to fire. Actual IRQ state = %x", irq,
181 CHECK_DIF_OK(dif_aon_timer_irq_get_type(aon_timer_ctx.
aon_timer, irq, &type));
183 CHECK_DIF_OK(dif_aon_timer_irq_acknowledge(aon_timer_ctx.
aon_timer, irq));
187 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
193 dif_csrng_irq_t *irq_serviced) {
198 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
202 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
205 dif_csrng_irq_t irq =
212 CHECK_DIF_OK(dif_csrng_irq_get_state(csrng_ctx.
csrng, &snapshot));
214 "Only csrng IRQ %d expected to fire. Actual IRQ state = %x", irq,
220 CHECK_DIF_OK(dif_csrng_irq_get_type(csrng_ctx.
csrng, irq, &type));
222 CHECK_DIF_OK(dif_csrng_irq_acknowledge(csrng_ctx.
csrng, irq));
226 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
232 dif_edn_irq_t *irq_serviced) {
237 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
241 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
251 CHECK_DIF_OK(dif_edn_irq_get_state(edn_ctx.
edn, &snapshot));
253 "Only edn IRQ %d expected to fire. Actual IRQ state = %x", irq,
259 CHECK_DIF_OK(dif_edn_irq_get_type(edn_ctx.
edn, irq, &type));
261 CHECK_DIF_OK(dif_edn_irq_acknowledge(edn_ctx.
edn, irq));
265 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
269void isr_testutils_entropy_src_isr(
272 dif_entropy_src_irq_t *irq_serviced) {
277 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
281 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
284 dif_entropy_src_irq_t irq =
285 (dif_entropy_src_irq_t)(plic_irq_id -
293 dif_entropy_src_irq_get_state(entropy_src_ctx.
entropy_src, &snapshot));
295 "Only entropy_src IRQ %d expected to fire. Actual IRQ state = %x",
302 dif_entropy_src_irq_get_type(entropy_src_ctx.
entropy_src, irq, &type));
305 dif_entropy_src_irq_acknowledge(entropy_src_ctx.
entropy_src, irq));
309 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
313void isr_testutils_flash_ctrl_isr(
316 dif_flash_ctrl_irq_t *irq_serviced) {
321 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
325 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
328 dif_flash_ctrl_irq_t irq =
329 (dif_flash_ctrl_irq_t)(plic_irq_id -
337 dif_flash_ctrl_irq_get_state(flash_ctrl_ctx.
flash_ctrl, &snapshot));
339 "Only flash_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
346 dif_flash_ctrl_irq_get_type(flash_ctrl_ctx.
flash_ctrl, irq, &type));
349 dif_flash_ctrl_irq_acknowledge(flash_ctrl_ctx.
flash_ctrl, irq));
350 }
else if (mute_status_irq) {
351 CHECK_DIF_OK(dif_flash_ctrl_irq_set_enabled(flash_ctrl_ctx.
flash_ctrl, irq,
356 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
362 dif_gpio_irq_t *irq_serviced) {
367 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
371 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
381 CHECK_DIF_OK(dif_gpio_irq_get_state(gpio_ctx.
gpio, &snapshot));
383 "Only gpio IRQ %d expected to fire. Actual IRQ state = %x", irq,
389 CHECK_DIF_OK(dif_gpio_irq_get_type(gpio_ctx.
gpio, irq, &type));
391 CHECK_DIF_OK(dif_gpio_irq_acknowledge(gpio_ctx.
gpio, irq));
395 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
400 bool mute_status_irq,
402 dif_hmac_irq_t *irq_serviced) {
407 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
411 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
421 CHECK_DIF_OK(dif_hmac_irq_get_state(hmac_ctx.
hmac, &snapshot));
423 "Only hmac IRQ %d expected to fire. Actual IRQ state = %x", irq,
429 CHECK_DIF_OK(dif_hmac_irq_get_type(hmac_ctx.
hmac, irq, &type));
431 CHECK_DIF_OK(dif_hmac_irq_acknowledge(hmac_ctx.
hmac, irq));
432 }
else if (mute_status_irq) {
438 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
443 bool mute_status_irq,
445 dif_i2c_irq_t *irq_serviced) {
450 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
454 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
464 CHECK_DIF_OK(dif_i2c_irq_get_state(i2c_ctx.
i2c, &snapshot));
466 "Only i2c IRQ %d expected to fire. Actual IRQ state = %x", irq,
472 CHECK_DIF_OK(dif_i2c_irq_get_type(i2c_ctx.
i2c, irq, &type));
474 CHECK_DIF_OK(dif_i2c_irq_acknowledge(i2c_ctx.
i2c, irq));
475 }
else if (mute_status_irq) {
480 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
487 dif_keymgr_irq_t *irq_serviced) {
492 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
496 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
499 dif_keymgr_irq_t irq =
506 CHECK_DIF_OK(dif_keymgr_irq_get_state(keymgr_ctx.
keymgr, &snapshot));
508 "Only keymgr IRQ %d expected to fire. Actual IRQ state = %x", irq,
514 CHECK_DIF_OK(dif_keymgr_irq_get_type(keymgr_ctx.
keymgr, irq, &type));
516 CHECK_DIF_OK(dif_keymgr_irq_acknowledge(keymgr_ctx.
keymgr, irq));
520 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
525 bool mute_status_irq,
527 dif_kmac_irq_t *irq_serviced) {
532 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
536 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
546 CHECK_DIF_OK(dif_kmac_irq_get_state(kmac_ctx.
kmac, &snapshot));
548 "Only kmac IRQ %d expected to fire. Actual IRQ state = %x", irq,
554 CHECK_DIF_OK(dif_kmac_irq_get_type(kmac_ctx.
kmac, irq, &type));
556 CHECK_DIF_OK(dif_kmac_irq_acknowledge(kmac_ctx.
kmac, irq));
557 }
else if (mute_status_irq) {
563 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
567void isr_testutils_otp_ctrl_isr(
570 dif_otp_ctrl_irq_t *irq_serviced) {
575 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
579 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
582 dif_otp_ctrl_irq_t irq =
583 (dif_otp_ctrl_irq_t)(plic_irq_id -
590 CHECK_DIF_OK(dif_otp_ctrl_irq_get_state(otp_ctrl_ctx.
otp_ctrl, &snapshot));
592 "Only otp_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
598 CHECK_DIF_OK(dif_otp_ctrl_irq_get_type(otp_ctrl_ctx.
otp_ctrl, irq, &type));
600 CHECK_DIF_OK(dif_otp_ctrl_irq_acknowledge(otp_ctrl_ctx.
otp_ctrl, irq));
604 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
611 dif_pattgen_irq_t *irq_serviced) {
616 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
620 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
623 dif_pattgen_irq_t irq =
630 CHECK_DIF_OK(dif_pattgen_irq_get_state(pattgen_ctx.
pattgen, &snapshot));
632 "Only pattgen IRQ %d expected to fire. Actual IRQ state = %x", irq,
638 CHECK_DIF_OK(dif_pattgen_irq_get_type(pattgen_ctx.
pattgen, irq, &type));
640 CHECK_DIF_OK(dif_pattgen_irq_acknowledge(pattgen_ctx.
pattgen, irq));
644 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
651 dif_pwrmgr_irq_t *irq_serviced) {
656 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
660 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
663 dif_pwrmgr_irq_t irq =
670 CHECK_DIF_OK(dif_pwrmgr_irq_get_state(pwrmgr_ctx.
pwrmgr, &snapshot));
672 "Only pwrmgr IRQ %d expected to fire. Actual IRQ state = %x", irq,
678 CHECK_DIF_OK(dif_pwrmgr_irq_get_type(pwrmgr_ctx.
pwrmgr, irq, &type));
680 CHECK_DIF_OK(dif_pwrmgr_irq_acknowledge(pwrmgr_ctx.
pwrmgr, irq));
684 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
688void isr_testutils_rv_timer_isr(
691 dif_rv_timer_irq_t *irq_serviced) {
696 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
700 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
703 dif_rv_timer_irq_t irq =
704 (dif_rv_timer_irq_t)(plic_irq_id -
711 CHECK_DIF_OK(dif_rv_timer_irq_get_state(rv_timer_ctx.
rv_timer,
714 "Only rv_timer IRQ %d expected to fire. Actual IRQ state = %x", irq,
720 CHECK_DIF_OK(dif_rv_timer_irq_get_type(rv_timer_ctx.
rv_timer, irq, &type));
722 CHECK_DIF_OK(dif_rv_timer_irq_acknowledge(rv_timer_ctx.
rv_timer, irq));
726 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
730void isr_testutils_sensor_ctrl_isr(
733 dif_sensor_ctrl_irq_t *irq_serviced) {
738 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
742 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
745 dif_sensor_ctrl_irq_t irq =
746 (dif_sensor_ctrl_irq_t)(plic_irq_id -
754 dif_sensor_ctrl_irq_get_state(sensor_ctrl_ctx.
sensor_ctrl, &snapshot));
756 "Only sensor_ctrl IRQ %d expected to fire. Actual IRQ state = %x",
763 dif_sensor_ctrl_irq_get_type(sensor_ctrl_ctx.
sensor_ctrl, irq, &type));
766 dif_sensor_ctrl_irq_acknowledge(sensor_ctrl_ctx.
sensor_ctrl, irq));
770 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
774void isr_testutils_spi_device_isr(
777 dif_spi_device_irq_t *irq_serviced) {
782 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
786 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
789 dif_spi_device_irq_t irq =
790 (dif_spi_device_irq_t)(plic_irq_id -
798 dif_spi_device_irq_get_state(spi_device_ctx.
spi_device, &snapshot));
800 "Only spi_device IRQ %d expected to fire. Actual IRQ state = %x", irq,
807 dif_spi_device_irq_get_type(spi_device_ctx.
spi_device, irq, &type));
810 dif_spi_device_irq_acknowledge(spi_device_ctx.
spi_device, irq));
811 }
else if (mute_status_irq) {
812 CHECK_DIF_OK(dif_spi_device_irq_set_enabled(spi_device_ctx.
spi_device, irq,
817 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
821void isr_testutils_spi_host_isr(
824 dif_spi_host_irq_t *irq_serviced) {
829 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
833 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
836 dif_spi_host_irq_t irq =
837 (dif_spi_host_irq_t)(plic_irq_id -
844 CHECK_DIF_OK(dif_spi_host_irq_get_state(spi_host_ctx.
spi_host, &snapshot));
846 "Only spi_host IRQ %d expected to fire. Actual IRQ state = %x", irq,
852 CHECK_DIF_OK(dif_spi_host_irq_get_type(spi_host_ctx.
spi_host, irq, &type));
854 CHECK_DIF_OK(dif_spi_host_irq_acknowledge(spi_host_ctx.
spi_host, irq));
855 }
else if (mute_status_irq) {
856 CHECK_DIF_OK(dif_spi_host_irq_set_enabled(spi_host_ctx.
spi_host, irq,
861 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
865void isr_testutils_sysrst_ctrl_isr(
868 dif_sysrst_ctrl_irq_t *irq_serviced) {
873 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
877 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
880 dif_sysrst_ctrl_irq_t irq =
881 (dif_sysrst_ctrl_irq_t)(plic_irq_id -
889 dif_sysrst_ctrl_irq_get_state(sysrst_ctrl_ctx.
sysrst_ctrl, &snapshot));
891 "Only sysrst_ctrl IRQ %d expected to fire. Actual IRQ state = %x",
898 dif_sysrst_ctrl_irq_get_type(sysrst_ctrl_ctx.
sysrst_ctrl, irq, &type));
901 dif_sysrst_ctrl_irq_acknowledge(sysrst_ctrl_ctx.
sysrst_ctrl, irq));
902 }
else if (mute_status_irq) {
903 CHECK_DIF_OK(dif_sysrst_ctrl_irq_set_enabled(sysrst_ctrl_ctx.
sysrst_ctrl,
908 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
913 bool mute_status_irq,
915 dif_uart_irq_t *irq_serviced) {
920 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
924 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
934 CHECK_DIF_OK(dif_uart_irq_get_state(uart_ctx.
uart, &snapshot));
936 "Only uart IRQ %d expected to fire. Actual IRQ state = %x", irq,
942 CHECK_DIF_OK(dif_uart_irq_get_type(uart_ctx.
uart, irq, &type));
944 CHECK_DIF_OK(dif_uart_irq_acknowledge(uart_ctx.
uart, irq));
945 }
else if (mute_status_irq) {
951 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
958 dif_usbdev_irq_t *irq_serviced) {
963 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
967 top_egret_plic_interrupt_for_peripheral[plic_irq_id];
970 dif_usbdev_irq_t irq =
977 CHECK_DIF_OK(dif_usbdev_irq_get_state(usbdev_ctx.
usbdev, &snapshot));
979 "Only usbdev IRQ %d expected to fire. Actual IRQ state = %x", irq,
985 CHECK_DIF_OK(dif_usbdev_irq_get_type(usbdev_ctx.
usbdev, irq, &type));
987 CHECK_DIF_OK(dif_usbdev_irq_acknowledge(usbdev_ctx.
usbdev, irq));
988 }
else if (mute_status_irq) {
994 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,