Top-specific Definitions. More...

Macros
#define	TOP_EGRET_UART0_BASE_ADDR 0x40000000u
	Peripheral base address for uart0 in top egret.

#define	TOP_EGRET_UART0_SIZE_BYTES 0x40u
	Peripheral size for uart0 in top egret.

#define	TOP_EGRET_UART1_BASE_ADDR 0x40010000u
	Peripheral base address for uart1 in top egret.

#define	TOP_EGRET_UART1_SIZE_BYTES 0x40u
	Peripheral size for uart1 in top egret.

#define	TOP_EGRET_UART2_BASE_ADDR 0x40020000u
	Peripheral base address for uart2 in top egret.

#define	TOP_EGRET_UART2_SIZE_BYTES 0x40u
	Peripheral size for uart2 in top egret.

#define	TOP_EGRET_UART3_BASE_ADDR 0x40030000u
	Peripheral base address for uart3 in top egret.

#define	TOP_EGRET_UART3_SIZE_BYTES 0x40u
	Peripheral size for uart3 in top egret.

#define	TOP_EGRET_GPIO_BASE_ADDR 0x40040000u
	Peripheral base address for gpio in top egret.

#define	TOP_EGRET_GPIO_SIZE_BYTES 0x80u
	Peripheral size for gpio in top egret.

#define	TOP_EGRET_SPI_DEVICE_BASE_ADDR 0x40050000u
	Peripheral base address for spi_device in top egret.

#define	TOP_EGRET_SPI_DEVICE_SIZE_BYTES 0x2000u
	Peripheral size for spi_device in top egret.

#define	TOP_EGRET_I2C0_BASE_ADDR 0x40080000u
	Peripheral base address for i2c0 in top egret.

#define	TOP_EGRET_I2C0_SIZE_BYTES 0x80u
	Peripheral size for i2c0 in top egret.

#define	TOP_EGRET_I2C1_BASE_ADDR 0x40090000u
	Peripheral base address for i2c1 in top egret.

#define	TOP_EGRET_I2C1_SIZE_BYTES 0x80u
	Peripheral size for i2c1 in top egret.

#define	TOP_EGRET_I2C2_BASE_ADDR 0x400A0000u
	Peripheral base address for i2c2 in top egret.

#define	TOP_EGRET_I2C2_SIZE_BYTES 0x80u
	Peripheral size for i2c2 in top egret.

#define	TOP_EGRET_PATTGEN_BASE_ADDR 0x400E0000u
	Peripheral base address for pattgen in top egret.

#define	TOP_EGRET_PATTGEN_SIZE_BYTES 0x40u
	Peripheral size for pattgen in top egret.

#define	TOP_EGRET_RV_TIMER_BASE_ADDR 0x40100000u
	Peripheral base address for rv_timer in top egret.

#define	TOP_EGRET_RV_TIMER_SIZE_BYTES 0x200u
	Peripheral size for rv_timer in top egret.

#define	TOP_EGRET_OTP_CTRL_CORE_BASE_ADDR 0x40130000u
	Peripheral base address for core device on otp_ctrl in top egret.

#define	TOP_EGRET_OTP_CTRL_CORE_SIZE_BYTES 0x1000u
	Peripheral size for core device on otp_ctrl in top egret.

#define	TOP_EGRET_OTP_MACRO_PRIM_BASE_ADDR 0x40138000u
	Peripheral base address for prim device on otp_macro in top egret.

#define	TOP_EGRET_OTP_MACRO_PRIM_SIZE_BYTES 0x20u
	Peripheral size for prim device on otp_macro in top egret.

#define	TOP_EGRET_LC_CTRL_REGS_BASE_ADDR 0x40140000u
	Peripheral base address for regs device on lc_ctrl in top egret.

#define	TOP_EGRET_LC_CTRL_REGS_SIZE_BYTES 0x100u
	Peripheral size for regs device on lc_ctrl in top egret.

#define	TOP_EGRET_LC_CTRL_DMI_BASE_ADDR 0x0u
	Peripheral base address for dmi device on lc_ctrl in top egret.

#define	TOP_EGRET_LC_CTRL_DMI_SIZE_BYTES 0x1000u
	Peripheral size for dmi device on lc_ctrl in top egret.

#define	TOP_EGRET_ALERT_HANDLER_BASE_ADDR 0x40150000u
	Peripheral base address for alert_handler in top egret.

#define	TOP_EGRET_ALERT_HANDLER_SIZE_BYTES 0x800u
	Peripheral size for alert_handler in top egret.

#define	TOP_EGRET_SPI_HOST0_BASE_ADDR 0x40300000u
	Peripheral base address for spi_host0 in top egret.

#define	TOP_EGRET_SPI_HOST0_SIZE_BYTES 0x40u
	Peripheral size for spi_host0 in top egret.

#define	TOP_EGRET_SPI_HOST1_BASE_ADDR 0x40310000u
	Peripheral base address for spi_host1 in top egret.

#define	TOP_EGRET_SPI_HOST1_SIZE_BYTES 0x40u
	Peripheral size for spi_host1 in top egret.

#define	TOP_EGRET_USBDEV_BASE_ADDR 0x40320000u
	Peripheral base address for usbdev in top egret.

#define	TOP_EGRET_USBDEV_SIZE_BYTES 0x1000u
	Peripheral size for usbdev in top egret.

#define	TOP_EGRET_PWRMGR_AON_BASE_ADDR 0x40400000u
	Peripheral base address for pwrmgr_aon in top egret.

#define	TOP_EGRET_PWRMGR_AON_SIZE_BYTES 0x80u
	Peripheral size for pwrmgr_aon in top egret.

#define	TOP_EGRET_RSTMGR_AON_BASE_ADDR 0x40410000u
	Peripheral base address for rstmgr_aon in top egret.

#define	TOP_EGRET_RSTMGR_AON_SIZE_BYTES 0x80u
	Peripheral size for rstmgr_aon in top egret.

#define	TOP_EGRET_CLKMGR_AON_BASE_ADDR 0x40420000u
	Peripheral base address for clkmgr_aon in top egret.

#define	TOP_EGRET_CLKMGR_AON_SIZE_BYTES 0x80u
	Peripheral size for clkmgr_aon in top egret.

#define	TOP_EGRET_SYSRST_CTRL_AON_BASE_ADDR 0x40430000u
	Peripheral base address for sysrst_ctrl_aon in top egret.

#define	TOP_EGRET_SYSRST_CTRL_AON_SIZE_BYTES 0x100u
	Peripheral size for sysrst_ctrl_aon in top egret.

#define	TOP_EGRET_ADC_CTRL_AON_BASE_ADDR 0x40440000u
	Peripheral base address for adc_ctrl_aon in top egret.

#define	TOP_EGRET_ADC_CTRL_AON_SIZE_BYTES 0x80u
	Peripheral size for adc_ctrl_aon in top egret.

#define	TOP_EGRET_PWM_AON_BASE_ADDR 0x40450000u
	Peripheral base address for pwm_aon in top egret.

#define	TOP_EGRET_PWM_AON_SIZE_BYTES 0x80u
	Peripheral size for pwm_aon in top egret.

#define	TOP_EGRET_PINMUX_AON_BASE_ADDR 0x40460000u
	Peripheral base address for pinmux_aon in top egret.

#define	TOP_EGRET_PINMUX_AON_SIZE_BYTES 0x1000u
	Peripheral size for pinmux_aon in top egret.

#define	TOP_EGRET_AON_TIMER_AON_BASE_ADDR 0x40470000u
	Peripheral base address for aon_timer_aon in top egret.

#define	TOP_EGRET_AON_TIMER_AON_SIZE_BYTES 0x40u
	Peripheral size for aon_timer_aon in top egret.

#define	TOP_EGRET_AST_BASE_ADDR 0x40480000u
	Peripheral base address for ast in top egret.

#define	TOP_EGRET_AST_SIZE_BYTES 0x400u
	Peripheral size for ast in top egret.

#define	TOP_EGRET_SENSOR_CTRL_AON_BASE_ADDR 0x40490000u
	Peripheral base address for sensor_ctrl_aon in top egret.

#define	TOP_EGRET_SENSOR_CTRL_AON_SIZE_BYTES 0x80u
	Peripheral size for sensor_ctrl_aon in top egret.

#define	TOP_EGRET_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x40500000u
	Peripheral base address for regs device on sram_ctrl_ret_aon in top egret.

#define	TOP_EGRET_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x40u
	Peripheral size for regs device on sram_ctrl_ret_aon in top egret.

#define	TOP_EGRET_FLASH_CTRL_CORE_BASE_ADDR 0x41000000u
	Peripheral base address for core device on flash_ctrl in top egret.

#define	TOP_EGRET_FLASH_CTRL_CORE_SIZE_BYTES 0x200u
	Peripheral size for core device on flash_ctrl in top egret.

#define	TOP_EGRET_FLASH_MACRO_WRAPPER_BASE_ADDR 0x41008000u
	Peripheral base address for flash_macro_wrapper in top egret.

#define	TOP_EGRET_FLASH_MACRO_WRAPPER_SIZE_BYTES 0x80u
	Peripheral size for flash_macro_wrapper in top egret.

#define	TOP_EGRET_RV_DM_REGS_BASE_ADDR 0x41200000u
	Peripheral base address for regs device on rv_dm in top egret.

#define	TOP_EGRET_RV_DM_REGS_SIZE_BYTES 0x10u
	Peripheral size for regs device on rv_dm in top egret.

#define	TOP_EGRET_RV_DM_MEM_BASE_ADDR 0x10000u
	Peripheral base address for mem device on rv_dm in top egret.

#define	TOP_EGRET_RV_DM_MEM_SIZE_BYTES 0x1000u
	Peripheral size for mem device on rv_dm in top egret.

#define	TOP_EGRET_RV_DM_DBG_BASE_ADDR 0x1000u
	Peripheral base address for dbg device on rv_dm in top egret.

#define	TOP_EGRET_RV_DM_DBG_SIZE_BYTES 0x200u
	Peripheral size for dbg device on rv_dm in top egret.

#define	TOP_EGRET_RV_PLIC_BASE_ADDR 0x48000000u
	Peripheral base address for rv_plic in top egret.

#define	TOP_EGRET_RV_PLIC_SIZE_BYTES 0x8000000u
	Peripheral size for rv_plic in top egret.

#define	TOP_EGRET_ACC_BASE_ADDR 0x41300000u
	Peripheral base address for acc in top egret.

#define	TOP_EGRET_ACC_SIZE_BYTES 0x20000u
	Peripheral size for acc in top egret.

#define	TOP_EGRET_AES_BASE_ADDR 0x41100000u
	Peripheral base address for aes in top egret.

#define	TOP_EGRET_AES_SIZE_BYTES 0x100u
	Peripheral size for aes in top egret.

#define	TOP_EGRET_HMAC_BASE_ADDR 0x41110000u
	Peripheral base address for hmac in top egret.

#define	TOP_EGRET_HMAC_SIZE_BYTES 0x2000u
	Peripheral size for hmac in top egret.

#define	TOP_EGRET_KMAC_BASE_ADDR 0x41120000u
	Peripheral base address for kmac in top egret.

#define	TOP_EGRET_KMAC_SIZE_BYTES 0x1000u
	Peripheral size for kmac in top egret.

#define	TOP_EGRET_KEYMGR_BASE_ADDR 0x41140000u
	Peripheral base address for keymgr in top egret.

#define	TOP_EGRET_KEYMGR_SIZE_BYTES 0x100u
	Peripheral size for keymgr in top egret.

#define	TOP_EGRET_CSRNG_BASE_ADDR 0x41150000u
	Peripheral base address for csrng in top egret.

#define	TOP_EGRET_CSRNG_SIZE_BYTES 0x80u
	Peripheral size for csrng in top egret.

#define	TOP_EGRET_ENTROPY_SRC_BASE_ADDR 0x41160000u
	Peripheral base address for entropy_src in top egret.

#define	TOP_EGRET_ENTROPY_SRC_SIZE_BYTES 0x100u
	Peripheral size for entropy_src in top egret.

#define	TOP_EGRET_EDN0_BASE_ADDR 0x41170000u
	Peripheral base address for edn0 in top egret.

#define	TOP_EGRET_EDN0_SIZE_BYTES 0x80u
	Peripheral size for edn0 in top egret.

#define	TOP_EGRET_EDN1_BASE_ADDR 0x41180000u
	Peripheral base address for edn1 in top egret.

#define	TOP_EGRET_EDN1_SIZE_BYTES 0x80u
	Peripheral size for edn1 in top egret.

#define	TOP_EGRET_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000u
	Peripheral base address for regs device on sram_ctrl_main in top egret.

#define	TOP_EGRET_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40u
	Peripheral size for regs device on sram_ctrl_main in top egret.

#define	TOP_EGRET_ROM_CTRL_REGS_BASE_ADDR 0x411E0000u
	Peripheral base address for regs device on rom_ctrl in top egret.

#define	TOP_EGRET_ROM_CTRL_REGS_SIZE_BYTES 0x80u
	Peripheral size for regs device on rom_ctrl in top egret.

#define	TOP_EGRET_RV_CORE_IBEX_CFG_BASE_ADDR 0x411F0000u
	Peripheral base address for cfg device on rv_core_ibex in top egret.

#define	TOP_EGRET_RV_CORE_IBEX_CFG_SIZE_BYTES 0x100u
	Peripheral size for cfg device on rv_core_ibex in top egret.

#define	TOP_EGRET_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x40600000u
	Memory base address for ram memory on sram_ctrl_ret_aon in top egret.

#define	TOP_EGRET_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000u
	Memory size for ram memory on sram_ctrl_ret_aon in top egret.

#define	TOP_EGRET_FLASH_CTRL_MEM_BASE_ADDR 0x20000000u
	Memory base address for mem memory on flash_ctrl in top egret.

#define	TOP_EGRET_FLASH_CTRL_MEM_SIZE_BYTES 0x100000u
	Memory size for mem memory on flash_ctrl in top egret.

#define	TOP_EGRET_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000u
	Memory base address for ram memory on sram_ctrl_main in top egret.

#define	TOP_EGRET_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000u
	Memory size for ram memory on sram_ctrl_main in top egret.

#define	TOP_EGRET_ROM_CTRL_ROM_BASE_ADDR 0x8000u
	Memory base address for rom memory on rom_ctrl in top egret.

#define	TOP_EGRET_ROM_CTRL_ROM_SIZE_BYTES 0x8000u
	Memory size for rom memory on rom_ctrl in top egret.

#define	PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2

#define	NUM_MIO_PADS 47

#define	NUM_DIO_PADS 16

#define	PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3

#define	TOP_EGRET_MMIO_BASE_ADDR 0x40000000u
	MMIO Region.

#define	TOP_EGRET_MMIO_SIZE_BYTES 0x10000000u

Typedefs
typedef enum top_egret_plic_peripheral	top_egret_plic_peripheral_t
	PLIC Interrupt Source Peripheral.

typedef enum top_egret_plic_irq_id	top_egret_plic_irq_id_t
	PLIC Interrupt Source.

typedef enum top_egret_plic_target	top_egret_plic_target_t
	PLIC Interrupt Target.

typedef enum top_egret_alert_peripheral	top_egret_alert_peripheral_t
	Alert Handler Source Peripheral.

typedef enum top_egret_alert_id	top_egret_alert_id_t
	Alert Handler Alert Source.

typedef enum top_egret_pinmux_peripheral_in	top_egret_pinmux_peripheral_in_t
	Pinmux Peripheral Input.

typedef enum top_egret_pinmux_insel	top_egret_pinmux_insel_t
	Pinmux MIO Input Selector.

typedef enum top_egret_pinmux_mio_out	top_egret_pinmux_mio_out_t
	Pinmux MIO Output.

typedef enum top_egret_pinmux_outsel	top_egret_pinmux_outsel_t
	Pinmux Peripheral Output Selector.

typedef enum top_egret_direct_pads	top_egret_direct_pads_t
	Dedicated Pad Selects.

typedef enum top_egret_muxed_pads	top_egret_muxed_pads_t
	Muxed Pad Selects.

typedef enum top_egret_power_manager_wake_ups	top_egret_power_manager_wake_ups_t
	Power Manager Wakeup Signals.

typedef enum top_egret_reset_manager_sw_resets	top_egret_reset_manager_sw_resets_t
	Reset Manager Software Controlled Resets.

typedef enum top_egret_power_manager_reset_requests	top_egret_power_manager_reset_requests_t
	Power Manager Reset Request Signals.

typedef enum top_egret_gateable_clocks	top_egret_gateable_clocks_t
	Clock Manager Software-Controlled ("Gated") Clocks.

typedef enum top_egret_hintable_clocks	top_egret_hintable_clocks_t
	Clock Manager Software-Hinted Clocks.

Enumerations
enum	top_egret_plic_peripheral { kTopEgretPlicPeripheralUnknown = 0 , kTopEgretPlicPeripheralUart0 = 1 , kTopEgretPlicPeripheralUart1 = 2 , kTopEgretPlicPeripheralUart2 = 3 , kTopEgretPlicPeripheralUart3 = 4 , kTopEgretPlicPeripheralGpio = 5 , kTopEgretPlicPeripheralSpiDevice = 6 , kTopEgretPlicPeripheralI2c0 = 7 , kTopEgretPlicPeripheralI2c1 = 8 , kTopEgretPlicPeripheralI2c2 = 9 , kTopEgretPlicPeripheralPattgen = 10 , kTopEgretPlicPeripheralRvTimer = 11 , kTopEgretPlicPeripheralOtpCtrl = 12 , kTopEgretPlicPeripheralAlertHandler = 13 , kTopEgretPlicPeripheralSpiHost0 = 14 , kTopEgretPlicPeripheralSpiHost1 = 15 , kTopEgretPlicPeripheralUsbdev = 16 , kTopEgretPlicPeripheralPwrmgrAon = 17 , kTopEgretPlicPeripheralSysrstCtrlAon = 18 , kTopEgretPlicPeripheralAdcCtrlAon = 19 , kTopEgretPlicPeripheralAonTimerAon = 20 , kTopEgretPlicPeripheralSensorCtrlAon = 21 , kTopEgretPlicPeripheralFlashCtrl = 22 , kTopEgretPlicPeripheralAcc = 23 , kTopEgretPlicPeripheralHmac = 24 , kTopEgretPlicPeripheralKmac = 25 , kTopEgretPlicPeripheralKeymgr = 26 , kTopEgretPlicPeripheralCsrng = 27 , kTopEgretPlicPeripheralEntropySrc = 28 , kTopEgretPlicPeripheralEdn0 = 29 , kTopEgretPlicPeripheralEdn1 = 30 , kTopEgretPlicPeripheralLast = 30 }
	PLIC Interrupt Source Peripheral. More...

enum	top_egret_plic_irq_id { kTopEgretPlicIrqIdNone = 0 , kTopEgretPlicIrqIdUart0TxWatermark = 1 , kTopEgretPlicIrqIdUart0RxWatermark = 2 , kTopEgretPlicIrqIdUart0TxDone = 3 , kTopEgretPlicIrqIdUart0RxOverflow = 4 , kTopEgretPlicIrqIdUart0RxFrameErr = 5 , kTopEgretPlicIrqIdUart0RxBreakErr = 6 , kTopEgretPlicIrqIdUart0RxTimeout = 7 , kTopEgretPlicIrqIdUart0RxParityErr = 8 , kTopEgretPlicIrqIdUart0TxEmpty = 9 , kTopEgretPlicIrqIdUart1TxWatermark = 10 , kTopEgretPlicIrqIdUart1RxWatermark = 11 , kTopEgretPlicIrqIdUart1TxDone = 12 , kTopEgretPlicIrqIdUart1RxOverflow = 13 , kTopEgretPlicIrqIdUart1RxFrameErr = 14 , kTopEgretPlicIrqIdUart1RxBreakErr = 15 , kTopEgretPlicIrqIdUart1RxTimeout = 16 , kTopEgretPlicIrqIdUart1RxParityErr = 17 , kTopEgretPlicIrqIdUart1TxEmpty = 18 , kTopEgretPlicIrqIdUart2TxWatermark = 19 , kTopEgretPlicIrqIdUart2RxWatermark = 20 , kTopEgretPlicIrqIdUart2TxDone = 21 , kTopEgretPlicIrqIdUart2RxOverflow = 22 , kTopEgretPlicIrqIdUart2RxFrameErr = 23 , kTopEgretPlicIrqIdUart2RxBreakErr = 24 , kTopEgretPlicIrqIdUart2RxTimeout = 25 , kTopEgretPlicIrqIdUart2RxParityErr = 26 , kTopEgretPlicIrqIdUart2TxEmpty = 27 , kTopEgretPlicIrqIdUart3TxWatermark = 28 , kTopEgretPlicIrqIdUart3RxWatermark = 29 , kTopEgretPlicIrqIdUart3TxDone = 30 , kTopEgretPlicIrqIdUart3RxOverflow = 31 , kTopEgretPlicIrqIdUart3RxFrameErr = 32 , kTopEgretPlicIrqIdUart3RxBreakErr = 33 , kTopEgretPlicIrqIdUart3RxTimeout = 34 , kTopEgretPlicIrqIdUart3RxParityErr = 35 , kTopEgretPlicIrqIdUart3TxEmpty = 36 , kTopEgretPlicIrqIdGpioGpio0 = 37 , kTopEgretPlicIrqIdGpioGpio1 = 38 , kTopEgretPlicIrqIdGpioGpio2 = 39 , kTopEgretPlicIrqIdGpioGpio3 = 40 , kTopEgretPlicIrqIdGpioGpio4 = 41 , kTopEgretPlicIrqIdGpioGpio5 = 42 , kTopEgretPlicIrqIdGpioGpio6 = 43 , kTopEgretPlicIrqIdGpioGpio7 = 44 , kTopEgretPlicIrqIdGpioGpio8 = 45 , kTopEgretPlicIrqIdGpioGpio9 = 46 , kTopEgretPlicIrqIdGpioGpio10 = 47 , kTopEgretPlicIrqIdGpioGpio11 = 48 , kTopEgretPlicIrqIdGpioGpio12 = 49 , kTopEgretPlicIrqIdGpioGpio13 = 50 , kTopEgretPlicIrqIdGpioGpio14 = 51 , kTopEgretPlicIrqIdGpioGpio15 = 52 , kTopEgretPlicIrqIdGpioGpio16 = 53 , kTopEgretPlicIrqIdGpioGpio17 = 54 , kTopEgretPlicIrqIdGpioGpio18 = 55 , kTopEgretPlicIrqIdGpioGpio19 = 56 , kTopEgretPlicIrqIdGpioGpio20 = 57 , kTopEgretPlicIrqIdGpioGpio21 = 58 , kTopEgretPlicIrqIdGpioGpio22 = 59 , kTopEgretPlicIrqIdGpioGpio23 = 60 , kTopEgretPlicIrqIdGpioGpio24 = 61 , kTopEgretPlicIrqIdGpioGpio25 = 62 , kTopEgretPlicIrqIdGpioGpio26 = 63 , kTopEgretPlicIrqIdGpioGpio27 = 64 , kTopEgretPlicIrqIdGpioGpio28 = 65 , kTopEgretPlicIrqIdGpioGpio29 = 66 , kTopEgretPlicIrqIdGpioGpio30 = 67 , kTopEgretPlicIrqIdGpioGpio31 = 68 , kTopEgretPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty = 69 , kTopEgretPlicIrqIdSpiDeviceUploadPayloadNotEmpty = 70 , kTopEgretPlicIrqIdSpiDeviceUploadPayloadOverflow = 71 , kTopEgretPlicIrqIdSpiDeviceReadbufWatermark = 72 , kTopEgretPlicIrqIdSpiDeviceReadbufFlip = 73 , kTopEgretPlicIrqIdSpiDeviceTpmHeaderNotEmpty = 74 , kTopEgretPlicIrqIdSpiDeviceTpmRdfifoCmdEnd = 75 , kTopEgretPlicIrqIdSpiDeviceTpmRdfifoDrop = 76 , kTopEgretPlicIrqIdI2c0FmtThreshold = 77 , kTopEgretPlicIrqIdI2c0RxThreshold = 78 , kTopEgretPlicIrqIdI2c0AcqThreshold = 79 , kTopEgretPlicIrqIdI2c0RxOverflow = 80 , kTopEgretPlicIrqIdI2c0ControllerHalt = 81 , kTopEgretPlicIrqIdI2c0SclInterference = 82 , kTopEgretPlicIrqIdI2c0SdaInterference = 83 , kTopEgretPlicIrqIdI2c0StretchTimeout = 84 , kTopEgretPlicIrqIdI2c0SdaUnstable = 85 , kTopEgretPlicIrqIdI2c0CmdComplete = 86 , kTopEgretPlicIrqIdI2c0TxStretch = 87 , kTopEgretPlicIrqIdI2c0TxThreshold = 88 , kTopEgretPlicIrqIdI2c0AcqStretch = 89 , kTopEgretPlicIrqIdI2c0UnexpStop = 90 , kTopEgretPlicIrqIdI2c0HostTimeout = 91 , kTopEgretPlicIrqIdI2c1FmtThreshold = 92 , kTopEgretPlicIrqIdI2c1RxThreshold = 93 , kTopEgretPlicIrqIdI2c1AcqThreshold = 94 , kTopEgretPlicIrqIdI2c1RxOverflow = 95 , kTopEgretPlicIrqIdI2c1ControllerHalt = 96 , kTopEgretPlicIrqIdI2c1SclInterference = 97 , kTopEgretPlicIrqIdI2c1SdaInterference = 98 , kTopEgretPlicIrqIdI2c1StretchTimeout = 99 , kTopEgretPlicIrqIdI2c1SdaUnstable = 100 , kTopEgretPlicIrqIdI2c1CmdComplete = 101 , kTopEgretPlicIrqIdI2c1TxStretch = 102 , kTopEgretPlicIrqIdI2c1TxThreshold = 103 , kTopEgretPlicIrqIdI2c1AcqStretch = 104 , kTopEgretPlicIrqIdI2c1UnexpStop = 105 , kTopEgretPlicIrqIdI2c1HostTimeout = 106 , kTopEgretPlicIrqIdI2c2FmtThreshold = 107 , kTopEgretPlicIrqIdI2c2RxThreshold = 108 , kTopEgretPlicIrqIdI2c2AcqThreshold = 109 , kTopEgretPlicIrqIdI2c2RxOverflow = 110 , kTopEgretPlicIrqIdI2c2ControllerHalt = 111 , kTopEgretPlicIrqIdI2c2SclInterference = 112 , kTopEgretPlicIrqIdI2c2SdaInterference = 113 , kTopEgretPlicIrqIdI2c2StretchTimeout = 114 , kTopEgretPlicIrqIdI2c2SdaUnstable = 115 , kTopEgretPlicIrqIdI2c2CmdComplete = 116 , kTopEgretPlicIrqIdI2c2TxStretch = 117 , kTopEgretPlicIrqIdI2c2TxThreshold = 118 , kTopEgretPlicIrqIdI2c2AcqStretch = 119 , kTopEgretPlicIrqIdI2c2UnexpStop = 120 , kTopEgretPlicIrqIdI2c2HostTimeout = 121 , kTopEgretPlicIrqIdPattgenDoneCh0 = 122 , kTopEgretPlicIrqIdPattgenDoneCh1 = 123 , kTopEgretPlicIrqIdRvTimerTimerExpiredHart0Timer0 = 124 , kTopEgretPlicIrqIdOtpCtrlOtpOperationDone = 125 , kTopEgretPlicIrqIdOtpCtrlOtpError = 126 , kTopEgretPlicIrqIdAlertHandlerClassa = 127 , kTopEgretPlicIrqIdAlertHandlerClassb = 128 , kTopEgretPlicIrqIdAlertHandlerClassc = 129 , kTopEgretPlicIrqIdAlertHandlerClassd = 130 , kTopEgretPlicIrqIdSpiHost0Error = 131 , kTopEgretPlicIrqIdSpiHost0SpiEvent = 132 , kTopEgretPlicIrqIdSpiHost1Error = 133 , kTopEgretPlicIrqIdSpiHost1SpiEvent = 134 , kTopEgretPlicIrqIdUsbdevPktReceived = 135 , kTopEgretPlicIrqIdUsbdevPktSent = 136 , kTopEgretPlicIrqIdUsbdevDisconnected = 137 , kTopEgretPlicIrqIdUsbdevHostLost = 138 , kTopEgretPlicIrqIdUsbdevLinkReset = 139 , kTopEgretPlicIrqIdUsbdevLinkSuspend = 140 , kTopEgretPlicIrqIdUsbdevLinkResume = 141 , kTopEgretPlicIrqIdUsbdevAvOutEmpty = 142 , kTopEgretPlicIrqIdUsbdevRxFull = 143 , kTopEgretPlicIrqIdUsbdevAvOverflow = 144 , kTopEgretPlicIrqIdUsbdevLinkInErr = 145 , kTopEgretPlicIrqIdUsbdevRxCrcErr = 146 , kTopEgretPlicIrqIdUsbdevRxPidErr = 147 , kTopEgretPlicIrqIdUsbdevRxBitstuffErr = 148 , kTopEgretPlicIrqIdUsbdevFrame = 149 , kTopEgretPlicIrqIdUsbdevPowered = 150 , kTopEgretPlicIrqIdUsbdevLinkOutErr = 151 , kTopEgretPlicIrqIdUsbdevAvSetupEmpty = 152 , kTopEgretPlicIrqIdPwrmgrAonWakeup = 153 , kTopEgretPlicIrqIdSysrstCtrlAonEventDetected = 154 , kTopEgretPlicIrqIdAdcCtrlAonMatchPending = 155 , kTopEgretPlicIrqIdAonTimerAonWkupTimerExpired = 156 , kTopEgretPlicIrqIdAonTimerAonWdogTimerBark = 157 , kTopEgretPlicIrqIdSensorCtrlAonIoStatusChange = 158 , kTopEgretPlicIrqIdSensorCtrlAonInitStatusChange = 159 , kTopEgretPlicIrqIdFlashCtrlProgEmpty = 160 , kTopEgretPlicIrqIdFlashCtrlProgLvl = 161 , kTopEgretPlicIrqIdFlashCtrlRdFull = 162 , kTopEgretPlicIrqIdFlashCtrlRdLvl = 163 , kTopEgretPlicIrqIdFlashCtrlOpDone = 164 , kTopEgretPlicIrqIdFlashCtrlCorrErr = 165 , kTopEgretPlicIrqIdAccDone = 166 , kTopEgretPlicIrqIdHmacHmacDone = 167 , kTopEgretPlicIrqIdHmacFifoEmpty = 168 , kTopEgretPlicIrqIdHmacHmacErr = 169 , kTopEgretPlicIrqIdKmacKmacDone = 170 , kTopEgretPlicIrqIdKmacFifoEmpty = 171 , kTopEgretPlicIrqIdKmacKmacErr = 172 , kTopEgretPlicIrqIdKeymgrOpDone = 173 , kTopEgretPlicIrqIdCsrngCsCmdReqDone = 174 , kTopEgretPlicIrqIdCsrngCsEntropyReq = 175 , kTopEgretPlicIrqIdCsrngCsHwInstExc = 176 , kTopEgretPlicIrqIdCsrngCsFatalErr = 177 , kTopEgretPlicIrqIdEntropySrcEsEntropyValid = 178 , kTopEgretPlicIrqIdEntropySrcEsHealthTestFailed = 179 , kTopEgretPlicIrqIdEntropySrcEsObserveFifoReady = 180 , kTopEgretPlicIrqIdEntropySrcEsFatalErr = 181 , kTopEgretPlicIrqIdEdn0EdnCmdReqDone = 182 , kTopEgretPlicIrqIdEdn0EdnFatalErr = 183 , kTopEgretPlicIrqIdEdn1EdnCmdReqDone = 184 , kTopEgretPlicIrqIdEdn1EdnFatalErr = 185 , kTopEgretPlicIrqIdLast = 185 }
	PLIC Interrupt Source. More...

enum	top_egret_plic_target { kTopEgretPlicTargetIbex0 = 0 , kTopEgretPlicTargetLast = 0 }
	PLIC Interrupt Target. More...

enum	top_egret_alert_peripheral { kTopEgretAlertPeripheralExternal = 0 , kTopEgretAlertPeripheralUart0 = 1 , kTopEgretAlertPeripheralUart1 = 2 , kTopEgretAlertPeripheralUart2 = 3 , kTopEgretAlertPeripheralUart3 = 4 , kTopEgretAlertPeripheralGpio = 5 , kTopEgretAlertPeripheralSpiDevice = 6 , kTopEgretAlertPeripheralI2c0 = 7 , kTopEgretAlertPeripheralI2c1 = 8 , kTopEgretAlertPeripheralI2c2 = 9 , kTopEgretAlertPeripheralPattgen = 10 , kTopEgretAlertPeripheralRvTimer = 11 , kTopEgretAlertPeripheralOtpCtrl = 12 , kTopEgretAlertPeripheralLcCtrl = 13 , kTopEgretAlertPeripheralSpiHost0 = 14 , kTopEgretAlertPeripheralSpiHost1 = 15 , kTopEgretAlertPeripheralUsbdev = 16 , kTopEgretAlertPeripheralPwrmgrAon = 17 , kTopEgretAlertPeripheralRstmgrAon = 18 , kTopEgretAlertPeripheralClkmgrAon = 19 , kTopEgretAlertPeripheralSysrstCtrlAon = 20 , kTopEgretAlertPeripheralAdcCtrlAon = 21 , kTopEgretAlertPeripheralPwmAon = 22 , kTopEgretAlertPeripheralPinmuxAon = 23 , kTopEgretAlertPeripheralAonTimerAon = 24 , kTopEgretAlertPeripheralSensorCtrlAon = 25 , kTopEgretAlertPeripheralSramCtrlRetAon = 26 , kTopEgretAlertPeripheralFlashCtrl = 27 , kTopEgretAlertPeripheralRvDm = 28 , kTopEgretAlertPeripheralRvPlic = 29 , kTopEgretAlertPeripheralAcc = 30 , kTopEgretAlertPeripheralAes = 31 , kTopEgretAlertPeripheralHmac = 32 , kTopEgretAlertPeripheralKmac = 33 , kTopEgretAlertPeripheralKeymgr = 34 , kTopEgretAlertPeripheralCsrng = 35 , kTopEgretAlertPeripheralEntropySrc = 36 , kTopEgretAlertPeripheralEdn0 = 37 , kTopEgretAlertPeripheralEdn1 = 38 , kTopEgretAlertPeripheralSramCtrlMain = 39 , kTopEgretAlertPeripheralRomCtrl = 40 , kTopEgretAlertPeripheralRvCoreIbex = 41 , kTopEgretAlertPeripheralLast = 41 }
	Alert Handler Source Peripheral. More...

enum	top_egret_alert_id { kTopEgretAlertIdUart0FatalFault = 0 , kTopEgretAlertIdUart1FatalFault = 1 , kTopEgretAlertIdUart2FatalFault = 2 , kTopEgretAlertIdUart3FatalFault = 3 , kTopEgretAlertIdGpioFatalFault = 4 , kTopEgretAlertIdSpiDeviceFatalFault = 5 , kTopEgretAlertIdI2c0FatalFault = 6 , kTopEgretAlertIdI2c1FatalFault = 7 , kTopEgretAlertIdI2c2FatalFault = 8 , kTopEgretAlertIdPattgenFatalFault = 9 , kTopEgretAlertIdRvTimerFatalFault = 10 , kTopEgretAlertIdOtpCtrlFatalMacroError = 11 , kTopEgretAlertIdOtpCtrlFatalCheckError = 12 , kTopEgretAlertIdOtpCtrlFatalBusIntegError = 13 , kTopEgretAlertIdOtpCtrlFatalPrimOtpAlert = 14 , kTopEgretAlertIdOtpCtrlRecovPrimOtpAlert = 15 , kTopEgretAlertIdLcCtrlFatalProgError = 16 , kTopEgretAlertIdLcCtrlFatalStateError = 17 , kTopEgretAlertIdLcCtrlFatalBusIntegError = 18 , kTopEgretAlertIdSpiHost0FatalFault = 19 , kTopEgretAlertIdSpiHost1FatalFault = 20 , kTopEgretAlertIdUsbdevFatalFault = 21 , kTopEgretAlertIdPwrmgrAonFatalFault = 22 , kTopEgretAlertIdRstmgrAonFatalFault = 23 , kTopEgretAlertIdRstmgrAonFatalCnstyFault = 24 , kTopEgretAlertIdClkmgrAonRecovFault = 25 , kTopEgretAlertIdClkmgrAonFatalFault = 26 , kTopEgretAlertIdSysrstCtrlAonFatalFault = 27 , kTopEgretAlertIdAdcCtrlAonFatalFault = 28 , kTopEgretAlertIdPwmAonFatalFault = 29 , kTopEgretAlertIdPinmuxAonFatalFault = 30 , kTopEgretAlertIdAonTimerAonFatalFault = 31 , kTopEgretAlertIdSensorCtrlAonRecovAlert = 32 , kTopEgretAlertIdSensorCtrlAonFatalAlert = 33 , kTopEgretAlertIdSramCtrlRetAonFatalError = 34 , kTopEgretAlertIdFlashCtrlRecovErr = 35 , kTopEgretAlertIdFlashCtrlFatalStdErr = 36 , kTopEgretAlertIdFlashCtrlFatalErr = 37 , kTopEgretAlertIdFlashCtrlFatalPrimFlashAlert = 38 , kTopEgretAlertIdFlashCtrlRecovPrimFlashAlert = 39 , kTopEgretAlertIdRvDmFatalFault = 40 , kTopEgretAlertIdRvPlicFatalFault = 41 , kTopEgretAlertIdAccFatal = 42 , kTopEgretAlertIdAccRecov = 43 , kTopEgretAlertIdAesRecovCtrlUpdateErr = 44 , kTopEgretAlertIdAesFatalFault = 45 , kTopEgretAlertIdHmacFatalFault = 46 , kTopEgretAlertIdKmacRecovOperationErr = 47 , kTopEgretAlertIdKmacFatalFaultErr = 48 , kTopEgretAlertIdKeymgrRecovOperationErr = 49 , kTopEgretAlertIdKeymgrFatalFaultErr = 50 , kTopEgretAlertIdCsrngRecovAlert = 51 , kTopEgretAlertIdCsrngFatalAlert = 52 , kTopEgretAlertIdEntropySrcRecovAlert = 53 , kTopEgretAlertIdEntropySrcFatalAlert = 54 , kTopEgretAlertIdEdn0RecovAlert = 55 , kTopEgretAlertIdEdn0FatalAlert = 56 , kTopEgretAlertIdEdn1RecovAlert = 57 , kTopEgretAlertIdEdn1FatalAlert = 58 , kTopEgretAlertIdSramCtrlMainFatalError = 59 , kTopEgretAlertIdRomCtrlFatal = 60 , kTopEgretAlertIdRvCoreIbexFatalSwErr = 61 , kTopEgretAlertIdRvCoreIbexRecovSwErr = 62 , kTopEgretAlertIdRvCoreIbexFatalHwErr = 63 , kTopEgretAlertIdRvCoreIbexRecovHwErr = 64 , kTopEgretAlertIdLast = 64 }
	Alert Handler Alert Source. More...

enum	top_egret_pinmux_peripheral_in { kTopEgretPinmuxPeripheralInGpioGpio0 = 0 , kTopEgretPinmuxPeripheralInGpioGpio1 = 1 , kTopEgretPinmuxPeripheralInGpioGpio2 = 2 , kTopEgretPinmuxPeripheralInGpioGpio3 = 3 , kTopEgretPinmuxPeripheralInGpioGpio4 = 4 , kTopEgretPinmuxPeripheralInGpioGpio5 = 5 , kTopEgretPinmuxPeripheralInGpioGpio6 = 6 , kTopEgretPinmuxPeripheralInGpioGpio7 = 7 , kTopEgretPinmuxPeripheralInGpioGpio8 = 8 , kTopEgretPinmuxPeripheralInGpioGpio9 = 9 , kTopEgretPinmuxPeripheralInGpioGpio10 = 10 , kTopEgretPinmuxPeripheralInGpioGpio11 = 11 , kTopEgretPinmuxPeripheralInGpioGpio12 = 12 , kTopEgretPinmuxPeripheralInGpioGpio13 = 13 , kTopEgretPinmuxPeripheralInGpioGpio14 = 14 , kTopEgretPinmuxPeripheralInGpioGpio15 = 15 , kTopEgretPinmuxPeripheralInGpioGpio16 = 16 , kTopEgretPinmuxPeripheralInGpioGpio17 = 17 , kTopEgretPinmuxPeripheralInGpioGpio18 = 18 , kTopEgretPinmuxPeripheralInGpioGpio19 = 19 , kTopEgretPinmuxPeripheralInGpioGpio20 = 20 , kTopEgretPinmuxPeripheralInGpioGpio21 = 21 , kTopEgretPinmuxPeripheralInGpioGpio22 = 22 , kTopEgretPinmuxPeripheralInGpioGpio23 = 23 , kTopEgretPinmuxPeripheralInGpioGpio24 = 24 , kTopEgretPinmuxPeripheralInGpioGpio25 = 25 , kTopEgretPinmuxPeripheralInGpioGpio26 = 26 , kTopEgretPinmuxPeripheralInGpioGpio27 = 27 , kTopEgretPinmuxPeripheralInGpioGpio28 = 28 , kTopEgretPinmuxPeripheralInGpioGpio29 = 29 , kTopEgretPinmuxPeripheralInGpioGpio30 = 30 , kTopEgretPinmuxPeripheralInGpioGpio31 = 31 , kTopEgretPinmuxPeripheralInI2c0Sda = 32 , kTopEgretPinmuxPeripheralInI2c0Scl = 33 , kTopEgretPinmuxPeripheralInI2c1Sda = 34 , kTopEgretPinmuxPeripheralInI2c1Scl = 35 , kTopEgretPinmuxPeripheralInI2c2Sda = 36 , kTopEgretPinmuxPeripheralInI2c2Scl = 37 , kTopEgretPinmuxPeripheralInSpiHost1Sd0 = 38 , kTopEgretPinmuxPeripheralInSpiHost1Sd1 = 39 , kTopEgretPinmuxPeripheralInSpiHost1Sd2 = 40 , kTopEgretPinmuxPeripheralInSpiHost1Sd3 = 41 , kTopEgretPinmuxPeripheralInUart0Rx = 42 , kTopEgretPinmuxPeripheralInUart1Rx = 43 , kTopEgretPinmuxPeripheralInUart2Rx = 44 , kTopEgretPinmuxPeripheralInUart3Rx = 45 , kTopEgretPinmuxPeripheralInSpiDeviceTpmCsb = 46 , kTopEgretPinmuxPeripheralInFlashMacroWrapperTck = 47 , kTopEgretPinmuxPeripheralInFlashMacroWrapperTms = 48 , kTopEgretPinmuxPeripheralInFlashMacroWrapperTdi = 49 , kTopEgretPinmuxPeripheralInSysrstCtrlAonAcPresent = 50 , kTopEgretPinmuxPeripheralInSysrstCtrlAonKey0In = 51 , kTopEgretPinmuxPeripheralInSysrstCtrlAonKey1In = 52 , kTopEgretPinmuxPeripheralInSysrstCtrlAonKey2In = 53 , kTopEgretPinmuxPeripheralInSysrstCtrlAonPwrbIn = 54 , kTopEgretPinmuxPeripheralInSysrstCtrlAonLidOpen = 55 , kTopEgretPinmuxPeripheralInUsbdevSense = 56 , kTopEgretPinmuxPeripheralInLast = 56 }
	Pinmux Peripheral Input. More...

enum	top_egret_pinmux_insel { kTopEgretPinmuxInselConstantZero = 0 , kTopEgretPinmuxInselConstantOne = 1 , kTopEgretPinmuxInselIoa0 = 2 , kTopEgretPinmuxInselIoa1 = 3 , kTopEgretPinmuxInselIoa2 = 4 , kTopEgretPinmuxInselIoa3 = 5 , kTopEgretPinmuxInselIoa4 = 6 , kTopEgretPinmuxInselIoa5 = 7 , kTopEgretPinmuxInselIoa6 = 8 , kTopEgretPinmuxInselIoa7 = 9 , kTopEgretPinmuxInselIoa8 = 10 , kTopEgretPinmuxInselIob0 = 11 , kTopEgretPinmuxInselIob1 = 12 , kTopEgretPinmuxInselIob2 = 13 , kTopEgretPinmuxInselIob3 = 14 , kTopEgretPinmuxInselIob4 = 15 , kTopEgretPinmuxInselIob5 = 16 , kTopEgretPinmuxInselIob6 = 17 , kTopEgretPinmuxInselIob7 = 18 , kTopEgretPinmuxInselIob8 = 19 , kTopEgretPinmuxInselIob9 = 20 , kTopEgretPinmuxInselIob10 = 21 , kTopEgretPinmuxInselIob11 = 22 , kTopEgretPinmuxInselIob12 = 23 , kTopEgretPinmuxInselIoc0 = 24 , kTopEgretPinmuxInselIoc1 = 25 , kTopEgretPinmuxInselIoc2 = 26 , kTopEgretPinmuxInselIoc3 = 27 , kTopEgretPinmuxInselIoc4 = 28 , kTopEgretPinmuxInselIoc5 = 29 , kTopEgretPinmuxInselIoc6 = 30 , kTopEgretPinmuxInselIoc7 = 31 , kTopEgretPinmuxInselIoc8 = 32 , kTopEgretPinmuxInselIoc9 = 33 , kTopEgretPinmuxInselIoc10 = 34 , kTopEgretPinmuxInselIoc11 = 35 , kTopEgretPinmuxInselIoc12 = 36 , kTopEgretPinmuxInselIor0 = 37 , kTopEgretPinmuxInselIor1 = 38 , kTopEgretPinmuxInselIor2 = 39 , kTopEgretPinmuxInselIor3 = 40 , kTopEgretPinmuxInselIor4 = 41 , kTopEgretPinmuxInselIor5 = 42 , kTopEgretPinmuxInselIor6 = 43 , kTopEgretPinmuxInselIor7 = 44 , kTopEgretPinmuxInselIor10 = 45 , kTopEgretPinmuxInselIor11 = 46 , kTopEgretPinmuxInselIor12 = 47 , kTopEgretPinmuxInselIor13 = 48 , kTopEgretPinmuxInselLast = 48 }
	Pinmux MIO Input Selector. More...

enum	top_egret_pinmux_mio_out { kTopEgretPinmuxMioOutIoa0 = 0 , kTopEgretPinmuxMioOutIoa1 = 1 , kTopEgretPinmuxMioOutIoa2 = 2 , kTopEgretPinmuxMioOutIoa3 = 3 , kTopEgretPinmuxMioOutIoa4 = 4 , kTopEgretPinmuxMioOutIoa5 = 5 , kTopEgretPinmuxMioOutIoa6 = 6 , kTopEgretPinmuxMioOutIoa7 = 7 , kTopEgretPinmuxMioOutIoa8 = 8 , kTopEgretPinmuxMioOutIob0 = 9 , kTopEgretPinmuxMioOutIob1 = 10 , kTopEgretPinmuxMioOutIob2 = 11 , kTopEgretPinmuxMioOutIob3 = 12 , kTopEgretPinmuxMioOutIob4 = 13 , kTopEgretPinmuxMioOutIob5 = 14 , kTopEgretPinmuxMioOutIob6 = 15 , kTopEgretPinmuxMioOutIob7 = 16 , kTopEgretPinmuxMioOutIob8 = 17 , kTopEgretPinmuxMioOutIob9 = 18 , kTopEgretPinmuxMioOutIob10 = 19 , kTopEgretPinmuxMioOutIob11 = 20 , kTopEgretPinmuxMioOutIob12 = 21 , kTopEgretPinmuxMioOutIoc0 = 22 , kTopEgretPinmuxMioOutIoc1 = 23 , kTopEgretPinmuxMioOutIoc2 = 24 , kTopEgretPinmuxMioOutIoc3 = 25 , kTopEgretPinmuxMioOutIoc4 = 26 , kTopEgretPinmuxMioOutIoc5 = 27 , kTopEgretPinmuxMioOutIoc6 = 28 , kTopEgretPinmuxMioOutIoc7 = 29 , kTopEgretPinmuxMioOutIoc8 = 30 , kTopEgretPinmuxMioOutIoc9 = 31 , kTopEgretPinmuxMioOutIoc10 = 32 , kTopEgretPinmuxMioOutIoc11 = 33 , kTopEgretPinmuxMioOutIoc12 = 34 , kTopEgretPinmuxMioOutIor0 = 35 , kTopEgretPinmuxMioOutIor1 = 36 , kTopEgretPinmuxMioOutIor2 = 37 , kTopEgretPinmuxMioOutIor3 = 38 , kTopEgretPinmuxMioOutIor4 = 39 , kTopEgretPinmuxMioOutIor5 = 40 , kTopEgretPinmuxMioOutIor6 = 41 , kTopEgretPinmuxMioOutIor7 = 42 , kTopEgretPinmuxMioOutIor10 = 43 , kTopEgretPinmuxMioOutIor11 = 44 , kTopEgretPinmuxMioOutIor12 = 45 , kTopEgretPinmuxMioOutIor13 = 46 , kTopEgretPinmuxMioOutLast = 46 }
	Pinmux MIO Output. More...

enum	top_egret_pinmux_outsel { kTopEgretPinmuxOutselConstantZero = 0 , kTopEgretPinmuxOutselConstantOne = 1 , kTopEgretPinmuxOutselConstantHighZ = 2 , kTopEgretPinmuxOutselGpioGpio0 = 3 , kTopEgretPinmuxOutselGpioGpio1 = 4 , kTopEgretPinmuxOutselGpioGpio2 = 5 , kTopEgretPinmuxOutselGpioGpio3 = 6 , kTopEgretPinmuxOutselGpioGpio4 = 7 , kTopEgretPinmuxOutselGpioGpio5 = 8 , kTopEgretPinmuxOutselGpioGpio6 = 9 , kTopEgretPinmuxOutselGpioGpio7 = 10 , kTopEgretPinmuxOutselGpioGpio8 = 11 , kTopEgretPinmuxOutselGpioGpio9 = 12 , kTopEgretPinmuxOutselGpioGpio10 = 13 , kTopEgretPinmuxOutselGpioGpio11 = 14 , kTopEgretPinmuxOutselGpioGpio12 = 15 , kTopEgretPinmuxOutselGpioGpio13 = 16 , kTopEgretPinmuxOutselGpioGpio14 = 17 , kTopEgretPinmuxOutselGpioGpio15 = 18 , kTopEgretPinmuxOutselGpioGpio16 = 19 , kTopEgretPinmuxOutselGpioGpio17 = 20 , kTopEgretPinmuxOutselGpioGpio18 = 21 , kTopEgretPinmuxOutselGpioGpio19 = 22 , kTopEgretPinmuxOutselGpioGpio20 = 23 , kTopEgretPinmuxOutselGpioGpio21 = 24 , kTopEgretPinmuxOutselGpioGpio22 = 25 , kTopEgretPinmuxOutselGpioGpio23 = 26 , kTopEgretPinmuxOutselGpioGpio24 = 27 , kTopEgretPinmuxOutselGpioGpio25 = 28 , kTopEgretPinmuxOutselGpioGpio26 = 29 , kTopEgretPinmuxOutselGpioGpio27 = 30 , kTopEgretPinmuxOutselGpioGpio28 = 31 , kTopEgretPinmuxOutselGpioGpio29 = 32 , kTopEgretPinmuxOutselGpioGpio30 = 33 , kTopEgretPinmuxOutselGpioGpio31 = 34 , kTopEgretPinmuxOutselI2c0Sda = 35 , kTopEgretPinmuxOutselI2c0Scl = 36 , kTopEgretPinmuxOutselI2c1Sda = 37 , kTopEgretPinmuxOutselI2c1Scl = 38 , kTopEgretPinmuxOutselI2c2Sda = 39 , kTopEgretPinmuxOutselI2c2Scl = 40 , kTopEgretPinmuxOutselSpiHost1Sd0 = 41 , kTopEgretPinmuxOutselSpiHost1Sd1 = 42 , kTopEgretPinmuxOutselSpiHost1Sd2 = 43 , kTopEgretPinmuxOutselSpiHost1Sd3 = 44 , kTopEgretPinmuxOutselUart0Tx = 45 , kTopEgretPinmuxOutselUart1Tx = 46 , kTopEgretPinmuxOutselUart2Tx = 47 , kTopEgretPinmuxOutselUart3Tx = 48 , kTopEgretPinmuxOutselPattgenPda0Tx = 49 , kTopEgretPinmuxOutselPattgenPcl0Tx = 50 , kTopEgretPinmuxOutselPattgenPda1Tx = 51 , kTopEgretPinmuxOutselPattgenPcl1Tx = 52 , kTopEgretPinmuxOutselSpiHost1Sck = 53 , kTopEgretPinmuxOutselSpiHost1Csb = 54 , kTopEgretPinmuxOutselFlashMacroWrapperTdo = 55 , kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut0 = 56 , kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut1 = 57 , kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut2 = 58 , kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut3 = 59 , kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut4 = 60 , kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut5 = 61 , kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut6 = 62 , kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut7 = 63 , kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut8 = 64 , kTopEgretPinmuxOutselPwmAonPwm0 = 65 , kTopEgretPinmuxOutselPwmAonPwm1 = 66 , kTopEgretPinmuxOutselPwmAonPwm2 = 67 , kTopEgretPinmuxOutselPwmAonPwm3 = 68 , kTopEgretPinmuxOutselPwmAonPwm4 = 69 , kTopEgretPinmuxOutselPwmAonPwm5 = 70 , kTopEgretPinmuxOutselOtpMacroTest0 = 71 , kTopEgretPinmuxOutselSysrstCtrlAonBatDisable = 72 , kTopEgretPinmuxOutselSysrstCtrlAonKey0Out = 73 , kTopEgretPinmuxOutselSysrstCtrlAonKey1Out = 74 , kTopEgretPinmuxOutselSysrstCtrlAonKey2Out = 75 , kTopEgretPinmuxOutselSysrstCtrlAonPwrbOut = 76 , kTopEgretPinmuxOutselSysrstCtrlAonZ3Wakeup = 77 , kTopEgretPinmuxOutselLast = 77 }
	Pinmux Peripheral Output Selector. More...

enum	top_egret_direct_pads { kTopEgretDirectPadsUsbdevUsbDp = 0 , kTopEgretDirectPadsUsbdevUsbDn = 1 , kTopEgretDirectPadsSpiHost0Sd0 = 2 , kTopEgretDirectPadsSpiHost0Sd1 = 3 , kTopEgretDirectPadsSpiHost0Sd2 = 4 , kTopEgretDirectPadsSpiHost0Sd3 = 5 , kTopEgretDirectPadsSpiDeviceSd0 = 6 , kTopEgretDirectPadsSpiDeviceSd1 = 7 , kTopEgretDirectPadsSpiDeviceSd2 = 8 , kTopEgretDirectPadsSpiDeviceSd3 = 9 , kTopEgretDirectPadsSysrstCtrlAonEcRstL = 10 , kTopEgretDirectPadsSysrstCtrlAonFlashWpL = 11 , kTopEgretDirectPadsSpiDeviceSck = 12 , kTopEgretDirectPadsSpiDeviceCsb = 13 , kTopEgretDirectPadsSpiHost0Sck = 14 , kTopEgretDirectPadsSpiHost0Csb = 15 , kTopEgretDirectPadsLast = 15 }
	Dedicated Pad Selects. More...

enum	top_egret_muxed_pads { kTopEgretMuxedPadsIoa0 = 0 , kTopEgretMuxedPadsIoa1 = 1 , kTopEgretMuxedPadsIoa2 = 2 , kTopEgretMuxedPadsIoa3 = 3 , kTopEgretMuxedPadsIoa4 = 4 , kTopEgretMuxedPadsIoa5 = 5 , kTopEgretMuxedPadsIoa6 = 6 , kTopEgretMuxedPadsIoa7 = 7 , kTopEgretMuxedPadsIoa8 = 8 , kTopEgretMuxedPadsIob0 = 9 , kTopEgretMuxedPadsIob1 = 10 , kTopEgretMuxedPadsIob2 = 11 , kTopEgretMuxedPadsIob3 = 12 , kTopEgretMuxedPadsIob4 = 13 , kTopEgretMuxedPadsIob5 = 14 , kTopEgretMuxedPadsIob6 = 15 , kTopEgretMuxedPadsIob7 = 16 , kTopEgretMuxedPadsIob8 = 17 , kTopEgretMuxedPadsIob9 = 18 , kTopEgretMuxedPadsIob10 = 19 , kTopEgretMuxedPadsIob11 = 20 , kTopEgretMuxedPadsIob12 = 21 , kTopEgretMuxedPadsIoc0 = 22 , kTopEgretMuxedPadsIoc1 = 23 , kTopEgretMuxedPadsIoc2 = 24 , kTopEgretMuxedPadsIoc3 = 25 , kTopEgretMuxedPadsIoc4 = 26 , kTopEgretMuxedPadsIoc5 = 27 , kTopEgretMuxedPadsIoc6 = 28 , kTopEgretMuxedPadsIoc7 = 29 , kTopEgretMuxedPadsIoc8 = 30 , kTopEgretMuxedPadsIoc9 = 31 , kTopEgretMuxedPadsIoc10 = 32 , kTopEgretMuxedPadsIoc11 = 33 , kTopEgretMuxedPadsIoc12 = 34 , kTopEgretMuxedPadsIor0 = 35 , kTopEgretMuxedPadsIor1 = 36 , kTopEgretMuxedPadsIor2 = 37 , kTopEgretMuxedPadsIor3 = 38 , kTopEgretMuxedPadsIor4 = 39 , kTopEgretMuxedPadsIor5 = 40 , kTopEgretMuxedPadsIor6 = 41 , kTopEgretMuxedPadsIor7 = 42 , kTopEgretMuxedPadsIor10 = 43 , kTopEgretMuxedPadsIor11 = 44 , kTopEgretMuxedPadsIor12 = 45 , kTopEgretMuxedPadsIor13 = 46 , kTopEgretMuxedPadsLast = 46 }
	Muxed Pad Selects. More...

enum	top_egret_power_manager_wake_ups { kTopEgretPowerManagerWakeUpsSysrstCtrlAonWkupReq = 0 , kTopEgretPowerManagerWakeUpsAdcCtrlAonWkupReq = 1 , kTopEgretPowerManagerWakeUpsPinmuxAonPinWkupReq = 2 , kTopEgretPowerManagerWakeUpsPinmuxAonUsbWkupReq = 3 , kTopEgretPowerManagerWakeUpsAonTimerAonWkupReq = 4 , kTopEgretPowerManagerWakeUpsSensorCtrlAonWkupReq = 5 , kTopEgretPowerManagerWakeUpsLast = 5 }
	Power Manager Wakeup Signals. More...

enum	top_egret_reset_manager_sw_resets { kTopEgretResetManagerSwResetsSpiDevice = 0 , kTopEgretResetManagerSwResetsSpiHost0 = 1 , kTopEgretResetManagerSwResetsSpiHost1 = 2 , kTopEgretResetManagerSwResetsUsb = 3 , kTopEgretResetManagerSwResetsUsbAon = 4 , kTopEgretResetManagerSwResetsI2c0 = 5 , kTopEgretResetManagerSwResetsI2c1 = 6 , kTopEgretResetManagerSwResetsI2c2 = 7 , kTopEgretResetManagerSwResetsLast = 7 }
	Reset Manager Software Controlled Resets. More...

enum	top_egret_power_manager_reset_requests { kTopEgretPowerManagerResetRequestsSysrstCtrlAonRstReq = 0 , kTopEgretPowerManagerResetRequestsAonTimerAonAonTimerRstReq = 1 , kTopEgretPowerManagerResetRequestsLast = 1 }
	Power Manager Reset Request Signals. More...

enum	top_egret_gateable_clocks { kTopEgretGateableClocksIoDiv4Peri = 0 , kTopEgretGateableClocksIoDiv2Peri = 1 , kTopEgretGateableClocksIoPeri = 2 , kTopEgretGateableClocksUsbPeri = 3 , kTopEgretGateableClocksLast = 3 }
	Clock Manager Software-Controlled ("Gated") Clocks. More...

enum	top_egret_hintable_clocks { kTopEgretHintableClocksMainAcc = 0 , kTopEgretHintableClocksMainAes = 1 , kTopEgretHintableClocksMainHmac = 2 , kTopEgretHintableClocksMainKmac = 3 , kTopEgretHintableClocksLast = 3 }
	Clock Manager Software-Hinted Clocks. More...

Variables
const top_egret_plic_peripheral_t	top_egret_plic_interrupt_for_peripheral [186]
	PLIC Interrupt Source to Peripheral Map.

const top_egret_alert_peripheral_t	top_egret_alert_for_peripheral [65]
	Alert Handler Alert Source to Peripheral Map.

Detailed Description

Top-specific Definitions.

This file contains preprocessor and type definitions for use within the device C/C++ codebase.

These definitions are for information that depends on the top-specific chip configuration, which includes:

Device Memory Information (for Peripherals and Memory)
PLIC Interrupt ID Names and Source Mappings
Alert ID Names and Source Mappings
Pinmux Pin/Select Names
Power Manager Wakeups

Definition in file top_egret.h.

Macro Definition Documentation

◆ NUM_DIO_PADS

#define NUM_DIO_PADS 16

Definition at line 1338 of file top_egret.h.

◆ NUM_MIO_PADS

#define NUM_MIO_PADS 47

Definition at line 1337 of file top_egret.h.

◆ PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET

#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2

Definition at line 1333 of file top_egret.h.

◆ PINMUX_PERIPH_OUTSEL_IDX_OFFSET

#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3

Definition at line 1340 of file top_egret.h.

◆ TOP_EGRET_ACC_BASE_ADDR

#define TOP_EGRET_ACC_BASE_ADDR 0x41300000u

Peripheral base address for acc in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 687 of file top_egret.h.

◆ TOP_EGRET_ACC_SIZE_BYTES

#define TOP_EGRET_ACC_SIZE_BYTES 0x20000u

Peripheral size for acc in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_ACC_BASE_ADDR and TOP_EGRET_ACC_BASE_ADDR + TOP_EGRET_ACC_SIZE_BYTES.

Definition at line 697 of file top_egret.h.

◆ TOP_EGRET_ADC_CTRL_AON_BASE_ADDR

#define TOP_EGRET_ADC_CTRL_AON_BASE_ADDR 0x40440000u

Peripheral base address for adc_ctrl_aon in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 453 of file top_egret.h.

◆ TOP_EGRET_ADC_CTRL_AON_SIZE_BYTES

#define TOP_EGRET_ADC_CTRL_AON_SIZE_BYTES 0x80u

Peripheral size for adc_ctrl_aon in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_ADC_CTRL_AON_BASE_ADDR and TOP_EGRET_ADC_CTRL_AON_BASE_ADDR + TOP_EGRET_ADC_CTRL_AON_SIZE_BYTES.

Definition at line 463 of file top_egret.h.

◆ TOP_EGRET_AES_BASE_ADDR

#define TOP_EGRET_AES_BASE_ADDR 0x41100000u

Peripheral base address for aes in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 705 of file top_egret.h.

◆ TOP_EGRET_AES_SIZE_BYTES

#define TOP_EGRET_AES_SIZE_BYTES 0x100u

Peripheral size for aes in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_AES_BASE_ADDR and TOP_EGRET_AES_BASE_ADDR + TOP_EGRET_AES_SIZE_BYTES.

Definition at line 715 of file top_egret.h.

◆ TOP_EGRET_ALERT_HANDLER_BASE_ADDR

#define TOP_EGRET_ALERT_HANDLER_BASE_ADDR 0x40150000u

Peripheral base address for alert_handler in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 309 of file top_egret.h.

◆ TOP_EGRET_ALERT_HANDLER_SIZE_BYTES

#define TOP_EGRET_ALERT_HANDLER_SIZE_BYTES 0x800u

Peripheral size for alert_handler in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_ALERT_HANDLER_BASE_ADDR and TOP_EGRET_ALERT_HANDLER_BASE_ADDR + TOP_EGRET_ALERT_HANDLER_SIZE_BYTES.

Definition at line 319 of file top_egret.h.

◆ TOP_EGRET_AON_TIMER_AON_BASE_ADDR

#define TOP_EGRET_AON_TIMER_AON_BASE_ADDR 0x40470000u

Peripheral base address for aon_timer_aon in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 507 of file top_egret.h.

◆ TOP_EGRET_AON_TIMER_AON_SIZE_BYTES

#define TOP_EGRET_AON_TIMER_AON_SIZE_BYTES 0x40u

Peripheral size for aon_timer_aon in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_AON_TIMER_AON_BASE_ADDR and TOP_EGRET_AON_TIMER_AON_BASE_ADDR + TOP_EGRET_AON_TIMER_AON_SIZE_BYTES.

Definition at line 517 of file top_egret.h.

◆ TOP_EGRET_AST_BASE_ADDR

#define TOP_EGRET_AST_BASE_ADDR 0x40480000u

Peripheral base address for ast in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 525 of file top_egret.h.

◆ TOP_EGRET_AST_SIZE_BYTES

#define TOP_EGRET_AST_SIZE_BYTES 0x400u

Peripheral size for ast in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_AST_BASE_ADDR and TOP_EGRET_AST_BASE_ADDR + TOP_EGRET_AST_SIZE_BYTES.

Definition at line 535 of file top_egret.h.

◆ TOP_EGRET_CLKMGR_AON_BASE_ADDR

#define TOP_EGRET_CLKMGR_AON_BASE_ADDR 0x40420000u

Peripheral base address for clkmgr_aon in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 417 of file top_egret.h.

◆ TOP_EGRET_CLKMGR_AON_SIZE_BYTES

#define TOP_EGRET_CLKMGR_AON_SIZE_BYTES 0x80u

Peripheral size for clkmgr_aon in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_CLKMGR_AON_BASE_ADDR and TOP_EGRET_CLKMGR_AON_BASE_ADDR + TOP_EGRET_CLKMGR_AON_SIZE_BYTES.

Definition at line 427 of file top_egret.h.

◆ TOP_EGRET_CSRNG_BASE_ADDR

#define TOP_EGRET_CSRNG_BASE_ADDR 0x41150000u

Peripheral base address for csrng in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 777 of file top_egret.h.

◆ TOP_EGRET_CSRNG_SIZE_BYTES

#define TOP_EGRET_CSRNG_SIZE_BYTES 0x80u

Peripheral size for csrng in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_CSRNG_BASE_ADDR and TOP_EGRET_CSRNG_BASE_ADDR + TOP_EGRET_CSRNG_SIZE_BYTES.

Definition at line 787 of file top_egret.h.

◆ TOP_EGRET_EDN0_BASE_ADDR

#define TOP_EGRET_EDN0_BASE_ADDR 0x41170000u

Peripheral base address for edn0 in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 813 of file top_egret.h.

◆ TOP_EGRET_EDN0_SIZE_BYTES

#define TOP_EGRET_EDN0_SIZE_BYTES 0x80u

Peripheral size for edn0 in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_EDN0_BASE_ADDR and TOP_EGRET_EDN0_BASE_ADDR + TOP_EGRET_EDN0_SIZE_BYTES.

Definition at line 823 of file top_egret.h.

◆ TOP_EGRET_EDN1_BASE_ADDR

#define TOP_EGRET_EDN1_BASE_ADDR 0x41180000u

Peripheral base address for edn1 in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 831 of file top_egret.h.

◆ TOP_EGRET_EDN1_SIZE_BYTES

#define TOP_EGRET_EDN1_SIZE_BYTES 0x80u

Peripheral size for edn1 in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_EDN1_BASE_ADDR and TOP_EGRET_EDN1_BASE_ADDR + TOP_EGRET_EDN1_SIZE_BYTES.

Definition at line 841 of file top_egret.h.

◆ TOP_EGRET_ENTROPY_SRC_BASE_ADDR

#define TOP_EGRET_ENTROPY_SRC_BASE_ADDR 0x41160000u

Peripheral base address for entropy_src in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 795 of file top_egret.h.

◆ TOP_EGRET_ENTROPY_SRC_SIZE_BYTES

#define TOP_EGRET_ENTROPY_SRC_SIZE_BYTES 0x100u

Peripheral size for entropy_src in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_ENTROPY_SRC_BASE_ADDR and TOP_EGRET_ENTROPY_SRC_BASE_ADDR + TOP_EGRET_ENTROPY_SRC_SIZE_BYTES.

Definition at line 805 of file top_egret.h.

◆ TOP_EGRET_FLASH_CTRL_CORE_BASE_ADDR

#define TOP_EGRET_FLASH_CTRL_CORE_BASE_ADDR 0x41000000u

Peripheral base address for core device on flash_ctrl in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 579 of file top_egret.h.

◆ TOP_EGRET_FLASH_CTRL_CORE_SIZE_BYTES

#define TOP_EGRET_FLASH_CTRL_CORE_SIZE_BYTES 0x200u

Peripheral size for core device on flash_ctrl in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_FLASH_CTRL_CORE_BASE_ADDR and TOP_EGRET_FLASH_CTRL_CORE_BASE_ADDR + TOP_EGRET_FLASH_CTRL_CORE_SIZE_BYTES.

Definition at line 589 of file top_egret.h.

◆ TOP_EGRET_FLASH_CTRL_MEM_BASE_ADDR

#define TOP_EGRET_FLASH_CTRL_MEM_BASE_ADDR 0x20000000u

Memory base address for mem memory on flash_ctrl in top egret.

Definition at line 911 of file top_egret.h.

◆ TOP_EGRET_FLASH_CTRL_MEM_SIZE_BYTES

#define TOP_EGRET_FLASH_CTRL_MEM_SIZE_BYTES 0x100000u

Memory size for mem memory on flash_ctrl in top egret.

Definition at line 916 of file top_egret.h.

◆ TOP_EGRET_FLASH_MACRO_WRAPPER_BASE_ADDR

#define TOP_EGRET_FLASH_MACRO_WRAPPER_BASE_ADDR 0x41008000u

Peripheral base address for flash_macro_wrapper in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 597 of file top_egret.h.

◆ TOP_EGRET_FLASH_MACRO_WRAPPER_SIZE_BYTES

#define TOP_EGRET_FLASH_MACRO_WRAPPER_SIZE_BYTES 0x80u

Peripheral size for flash_macro_wrapper in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_FLASH_MACRO_WRAPPER_BASE_ADDR and TOP_EGRET_FLASH_MACRO_WRAPPER_BASE_ADDR + TOP_EGRET_FLASH_MACRO_WRAPPER_SIZE_BYTES.

Definition at line 607 of file top_egret.h.

◆ TOP_EGRET_GPIO_BASE_ADDR

#define TOP_EGRET_GPIO_BASE_ADDR 0x40040000u

Peripheral base address for gpio in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 111 of file top_egret.h.

◆ TOP_EGRET_GPIO_SIZE_BYTES

#define TOP_EGRET_GPIO_SIZE_BYTES 0x80u

Peripheral size for gpio in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_GPIO_BASE_ADDR and TOP_EGRET_GPIO_BASE_ADDR + TOP_EGRET_GPIO_SIZE_BYTES.

Definition at line 121 of file top_egret.h.

◆ TOP_EGRET_HMAC_BASE_ADDR

#define TOP_EGRET_HMAC_BASE_ADDR 0x41110000u

Peripheral base address for hmac in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 723 of file top_egret.h.

◆ TOP_EGRET_HMAC_SIZE_BYTES

#define TOP_EGRET_HMAC_SIZE_BYTES 0x2000u

Peripheral size for hmac in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_HMAC_BASE_ADDR and TOP_EGRET_HMAC_BASE_ADDR + TOP_EGRET_HMAC_SIZE_BYTES.

Definition at line 733 of file top_egret.h.

◆ TOP_EGRET_I2C0_BASE_ADDR

#define TOP_EGRET_I2C0_BASE_ADDR 0x40080000u

Peripheral base address for i2c0 in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 147 of file top_egret.h.

◆ TOP_EGRET_I2C0_SIZE_BYTES

#define TOP_EGRET_I2C0_SIZE_BYTES 0x80u

Peripheral size for i2c0 in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_I2C0_BASE_ADDR and TOP_EGRET_I2C0_BASE_ADDR + TOP_EGRET_I2C0_SIZE_BYTES.

Definition at line 157 of file top_egret.h.

◆ TOP_EGRET_I2C1_BASE_ADDR

#define TOP_EGRET_I2C1_BASE_ADDR 0x40090000u

Peripheral base address for i2c1 in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 165 of file top_egret.h.

◆ TOP_EGRET_I2C1_SIZE_BYTES

#define TOP_EGRET_I2C1_SIZE_BYTES 0x80u

Peripheral size for i2c1 in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_I2C1_BASE_ADDR and TOP_EGRET_I2C1_BASE_ADDR + TOP_EGRET_I2C1_SIZE_BYTES.

Definition at line 175 of file top_egret.h.

◆ TOP_EGRET_I2C2_BASE_ADDR

#define TOP_EGRET_I2C2_BASE_ADDR 0x400A0000u

Peripheral base address for i2c2 in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 183 of file top_egret.h.

◆ TOP_EGRET_I2C2_SIZE_BYTES

#define TOP_EGRET_I2C2_SIZE_BYTES 0x80u

Peripheral size for i2c2 in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_I2C2_BASE_ADDR and TOP_EGRET_I2C2_BASE_ADDR + TOP_EGRET_I2C2_SIZE_BYTES.

Definition at line 193 of file top_egret.h.

◆ TOP_EGRET_KEYMGR_BASE_ADDR

#define TOP_EGRET_KEYMGR_BASE_ADDR 0x41140000u

Peripheral base address for keymgr in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 759 of file top_egret.h.

◆ TOP_EGRET_KEYMGR_SIZE_BYTES

#define TOP_EGRET_KEYMGR_SIZE_BYTES 0x100u

Peripheral size for keymgr in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_KEYMGR_BASE_ADDR and TOP_EGRET_KEYMGR_BASE_ADDR + TOP_EGRET_KEYMGR_SIZE_BYTES.

Definition at line 769 of file top_egret.h.

◆ TOP_EGRET_KMAC_BASE_ADDR

#define TOP_EGRET_KMAC_BASE_ADDR 0x41120000u

Peripheral base address for kmac in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 741 of file top_egret.h.

◆ TOP_EGRET_KMAC_SIZE_BYTES

#define TOP_EGRET_KMAC_SIZE_BYTES 0x1000u

Peripheral size for kmac in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_KMAC_BASE_ADDR and TOP_EGRET_KMAC_BASE_ADDR + TOP_EGRET_KMAC_SIZE_BYTES.

Definition at line 751 of file top_egret.h.

◆ TOP_EGRET_LC_CTRL_DMI_BASE_ADDR

#define TOP_EGRET_LC_CTRL_DMI_BASE_ADDR 0x0u

Peripheral base address for dmi device on lc_ctrl in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 291 of file top_egret.h.

◆ TOP_EGRET_LC_CTRL_DMI_SIZE_BYTES

#define TOP_EGRET_LC_CTRL_DMI_SIZE_BYTES 0x1000u

Peripheral size for dmi device on lc_ctrl in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_LC_CTRL_DMI_BASE_ADDR and TOP_EGRET_LC_CTRL_DMI_BASE_ADDR + TOP_EGRET_LC_CTRL_DMI_SIZE_BYTES.

Definition at line 301 of file top_egret.h.

◆ TOP_EGRET_LC_CTRL_REGS_BASE_ADDR

#define TOP_EGRET_LC_CTRL_REGS_BASE_ADDR 0x40140000u

Peripheral base address for regs device on lc_ctrl in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 273 of file top_egret.h.

◆ TOP_EGRET_LC_CTRL_REGS_SIZE_BYTES

#define TOP_EGRET_LC_CTRL_REGS_SIZE_BYTES 0x100u

Peripheral size for regs device on lc_ctrl in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_LC_CTRL_REGS_BASE_ADDR and TOP_EGRET_LC_CTRL_REGS_BASE_ADDR + TOP_EGRET_LC_CTRL_REGS_SIZE_BYTES.

Definition at line 283 of file top_egret.h.

◆ TOP_EGRET_MMIO_BASE_ADDR

#define TOP_EGRET_MMIO_BASE_ADDR 0x40000000u

MMIO Region.

MMIO region excludes any memory that is separate from the module configuration space, i.e. ROM, main SRAM, and flash are excluded but retention SRAM, spi_device memory, or usbdev memory are included.

Definition at line 1749 of file top_egret.h.

◆ TOP_EGRET_MMIO_SIZE_BYTES

#define TOP_EGRET_MMIO_SIZE_BYTES 0x10000000u

Definition at line 1750 of file top_egret.h.

◆ TOP_EGRET_OTP_CTRL_CORE_BASE_ADDR

#define TOP_EGRET_OTP_CTRL_CORE_BASE_ADDR 0x40130000u

Peripheral base address for core device on otp_ctrl in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 237 of file top_egret.h.

◆ TOP_EGRET_OTP_CTRL_CORE_SIZE_BYTES

#define TOP_EGRET_OTP_CTRL_CORE_SIZE_BYTES 0x1000u

Peripheral size for core device on otp_ctrl in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_OTP_CTRL_CORE_BASE_ADDR and TOP_EGRET_OTP_CTRL_CORE_BASE_ADDR + TOP_EGRET_OTP_CTRL_CORE_SIZE_BYTES.

Definition at line 247 of file top_egret.h.

◆ TOP_EGRET_OTP_MACRO_PRIM_BASE_ADDR

#define TOP_EGRET_OTP_MACRO_PRIM_BASE_ADDR 0x40138000u

Peripheral base address for prim device on otp_macro in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 255 of file top_egret.h.

◆ TOP_EGRET_OTP_MACRO_PRIM_SIZE_BYTES

#define TOP_EGRET_OTP_MACRO_PRIM_SIZE_BYTES 0x20u

Peripheral size for prim device on otp_macro in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_OTP_MACRO_PRIM_BASE_ADDR and TOP_EGRET_OTP_MACRO_PRIM_BASE_ADDR + TOP_EGRET_OTP_MACRO_PRIM_SIZE_BYTES.

Definition at line 265 of file top_egret.h.

◆ TOP_EGRET_PATTGEN_BASE_ADDR

#define TOP_EGRET_PATTGEN_BASE_ADDR 0x400E0000u

Peripheral base address for pattgen in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 201 of file top_egret.h.

◆ TOP_EGRET_PATTGEN_SIZE_BYTES

#define TOP_EGRET_PATTGEN_SIZE_BYTES 0x40u

Peripheral size for pattgen in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_PATTGEN_BASE_ADDR and TOP_EGRET_PATTGEN_BASE_ADDR + TOP_EGRET_PATTGEN_SIZE_BYTES.

Definition at line 211 of file top_egret.h.

◆ TOP_EGRET_PINMUX_AON_BASE_ADDR

#define TOP_EGRET_PINMUX_AON_BASE_ADDR 0x40460000u

Peripheral base address for pinmux_aon in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 489 of file top_egret.h.

◆ TOP_EGRET_PINMUX_AON_SIZE_BYTES

#define TOP_EGRET_PINMUX_AON_SIZE_BYTES 0x1000u

Peripheral size for pinmux_aon in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_PINMUX_AON_BASE_ADDR and TOP_EGRET_PINMUX_AON_BASE_ADDR + TOP_EGRET_PINMUX_AON_SIZE_BYTES.

Definition at line 499 of file top_egret.h.

◆ TOP_EGRET_PWM_AON_BASE_ADDR

#define TOP_EGRET_PWM_AON_BASE_ADDR 0x40450000u

Peripheral base address for pwm_aon in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 471 of file top_egret.h.

◆ TOP_EGRET_PWM_AON_SIZE_BYTES

#define TOP_EGRET_PWM_AON_SIZE_BYTES 0x80u

Peripheral size for pwm_aon in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_PWM_AON_BASE_ADDR and TOP_EGRET_PWM_AON_BASE_ADDR + TOP_EGRET_PWM_AON_SIZE_BYTES.

Definition at line 481 of file top_egret.h.

◆ TOP_EGRET_PWRMGR_AON_BASE_ADDR

#define TOP_EGRET_PWRMGR_AON_BASE_ADDR 0x40400000u

Peripheral base address for pwrmgr_aon in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 381 of file top_egret.h.

◆ TOP_EGRET_PWRMGR_AON_SIZE_BYTES

#define TOP_EGRET_PWRMGR_AON_SIZE_BYTES 0x80u

Peripheral size for pwrmgr_aon in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_PWRMGR_AON_BASE_ADDR and TOP_EGRET_PWRMGR_AON_BASE_ADDR + TOP_EGRET_PWRMGR_AON_SIZE_BYTES.

Definition at line 391 of file top_egret.h.

◆ TOP_EGRET_ROM_CTRL_REGS_BASE_ADDR

#define TOP_EGRET_ROM_CTRL_REGS_BASE_ADDR 0x411E0000u

Peripheral base address for regs device on rom_ctrl in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 867 of file top_egret.h.

◆ TOP_EGRET_ROM_CTRL_REGS_SIZE_BYTES

#define TOP_EGRET_ROM_CTRL_REGS_SIZE_BYTES 0x80u

Peripheral size for regs device on rom_ctrl in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_ROM_CTRL_REGS_BASE_ADDR and TOP_EGRET_ROM_CTRL_REGS_BASE_ADDR + TOP_EGRET_ROM_CTRL_REGS_SIZE_BYTES.

Definition at line 877 of file top_egret.h.

◆ TOP_EGRET_ROM_CTRL_ROM_BASE_ADDR

#define TOP_EGRET_ROM_CTRL_ROM_BASE_ADDR 0x8000u

Memory base address for rom memory on rom_ctrl in top egret.

Definition at line 931 of file top_egret.h.

◆ TOP_EGRET_ROM_CTRL_ROM_SIZE_BYTES

#define TOP_EGRET_ROM_CTRL_ROM_SIZE_BYTES 0x8000u

Memory size for rom memory on rom_ctrl in top egret.

Definition at line 936 of file top_egret.h.

◆ TOP_EGRET_RSTMGR_AON_BASE_ADDR

#define TOP_EGRET_RSTMGR_AON_BASE_ADDR 0x40410000u

Peripheral base address for rstmgr_aon in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 399 of file top_egret.h.

◆ TOP_EGRET_RSTMGR_AON_SIZE_BYTES

#define TOP_EGRET_RSTMGR_AON_SIZE_BYTES 0x80u

Peripheral size for rstmgr_aon in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_RSTMGR_AON_BASE_ADDR and TOP_EGRET_RSTMGR_AON_BASE_ADDR + TOP_EGRET_RSTMGR_AON_SIZE_BYTES.

Definition at line 409 of file top_egret.h.

◆ TOP_EGRET_RV_CORE_IBEX_CFG_BASE_ADDR

#define TOP_EGRET_RV_CORE_IBEX_CFG_BASE_ADDR 0x411F0000u

Peripheral base address for cfg device on rv_core_ibex in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 885 of file top_egret.h.

◆ TOP_EGRET_RV_CORE_IBEX_CFG_SIZE_BYTES

#define TOP_EGRET_RV_CORE_IBEX_CFG_SIZE_BYTES 0x100u

Peripheral size for cfg device on rv_core_ibex in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_RV_CORE_IBEX_CFG_BASE_ADDR and TOP_EGRET_RV_CORE_IBEX_CFG_BASE_ADDR + TOP_EGRET_RV_CORE_IBEX_CFG_SIZE_BYTES.

Definition at line 895 of file top_egret.h.

◆ TOP_EGRET_RV_DM_DBG_BASE_ADDR

#define TOP_EGRET_RV_DM_DBG_BASE_ADDR 0x1000u

Peripheral base address for dbg device on rv_dm in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 651 of file top_egret.h.

◆ TOP_EGRET_RV_DM_DBG_SIZE_BYTES

#define TOP_EGRET_RV_DM_DBG_SIZE_BYTES 0x200u

Peripheral size for dbg device on rv_dm in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_RV_DM_DBG_BASE_ADDR and TOP_EGRET_RV_DM_DBG_BASE_ADDR + TOP_EGRET_RV_DM_DBG_SIZE_BYTES.

Definition at line 661 of file top_egret.h.

◆ TOP_EGRET_RV_DM_MEM_BASE_ADDR

#define TOP_EGRET_RV_DM_MEM_BASE_ADDR 0x10000u

Peripheral base address for mem device on rv_dm in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 633 of file top_egret.h.

◆ TOP_EGRET_RV_DM_MEM_SIZE_BYTES

#define TOP_EGRET_RV_DM_MEM_SIZE_BYTES 0x1000u

Peripheral size for mem device on rv_dm in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_RV_DM_MEM_BASE_ADDR and TOP_EGRET_RV_DM_MEM_BASE_ADDR + TOP_EGRET_RV_DM_MEM_SIZE_BYTES.

Definition at line 643 of file top_egret.h.

◆ TOP_EGRET_RV_DM_REGS_BASE_ADDR

#define TOP_EGRET_RV_DM_REGS_BASE_ADDR 0x41200000u

Peripheral base address for regs device on rv_dm in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 615 of file top_egret.h.

◆ TOP_EGRET_RV_DM_REGS_SIZE_BYTES

#define TOP_EGRET_RV_DM_REGS_SIZE_BYTES 0x10u

Peripheral size for regs device on rv_dm in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_RV_DM_REGS_BASE_ADDR and TOP_EGRET_RV_DM_REGS_BASE_ADDR + TOP_EGRET_RV_DM_REGS_SIZE_BYTES.

Definition at line 625 of file top_egret.h.

◆ TOP_EGRET_RV_PLIC_BASE_ADDR

#define TOP_EGRET_RV_PLIC_BASE_ADDR 0x48000000u

Peripheral base address for rv_plic in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 669 of file top_egret.h.

◆ TOP_EGRET_RV_PLIC_SIZE_BYTES

#define TOP_EGRET_RV_PLIC_SIZE_BYTES 0x8000000u

Peripheral size for rv_plic in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_RV_PLIC_BASE_ADDR and TOP_EGRET_RV_PLIC_BASE_ADDR + TOP_EGRET_RV_PLIC_SIZE_BYTES.

Definition at line 679 of file top_egret.h.

◆ TOP_EGRET_RV_TIMER_BASE_ADDR

#define TOP_EGRET_RV_TIMER_BASE_ADDR 0x40100000u

Peripheral base address for rv_timer in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 219 of file top_egret.h.

◆ TOP_EGRET_RV_TIMER_SIZE_BYTES

#define TOP_EGRET_RV_TIMER_SIZE_BYTES 0x200u

Peripheral size for rv_timer in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_RV_TIMER_BASE_ADDR and TOP_EGRET_RV_TIMER_BASE_ADDR + TOP_EGRET_RV_TIMER_SIZE_BYTES.

Definition at line 229 of file top_egret.h.

◆ TOP_EGRET_SENSOR_CTRL_AON_BASE_ADDR

#define TOP_EGRET_SENSOR_CTRL_AON_BASE_ADDR 0x40490000u

Peripheral base address for sensor_ctrl_aon in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 543 of file top_egret.h.

◆ TOP_EGRET_SENSOR_CTRL_AON_SIZE_BYTES

#define TOP_EGRET_SENSOR_CTRL_AON_SIZE_BYTES 0x80u

Peripheral size for sensor_ctrl_aon in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_SENSOR_CTRL_AON_BASE_ADDR and TOP_EGRET_SENSOR_CTRL_AON_BASE_ADDR + TOP_EGRET_SENSOR_CTRL_AON_SIZE_BYTES.

Definition at line 553 of file top_egret.h.

◆ TOP_EGRET_SPI_DEVICE_BASE_ADDR

#define TOP_EGRET_SPI_DEVICE_BASE_ADDR 0x40050000u

Peripheral base address for spi_device in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 129 of file top_egret.h.

◆ TOP_EGRET_SPI_DEVICE_SIZE_BYTES

#define TOP_EGRET_SPI_DEVICE_SIZE_BYTES 0x2000u

Peripheral size for spi_device in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_SPI_DEVICE_BASE_ADDR and TOP_EGRET_SPI_DEVICE_BASE_ADDR + TOP_EGRET_SPI_DEVICE_SIZE_BYTES.

Definition at line 139 of file top_egret.h.

◆ TOP_EGRET_SPI_HOST0_BASE_ADDR

#define TOP_EGRET_SPI_HOST0_BASE_ADDR 0x40300000u

Peripheral base address for spi_host0 in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 327 of file top_egret.h.

◆ TOP_EGRET_SPI_HOST0_SIZE_BYTES

#define TOP_EGRET_SPI_HOST0_SIZE_BYTES 0x40u

Peripheral size for spi_host0 in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_SPI_HOST0_BASE_ADDR and TOP_EGRET_SPI_HOST0_BASE_ADDR + TOP_EGRET_SPI_HOST0_SIZE_BYTES.

Definition at line 337 of file top_egret.h.

◆ TOP_EGRET_SPI_HOST1_BASE_ADDR

#define TOP_EGRET_SPI_HOST1_BASE_ADDR 0x40310000u

Peripheral base address for spi_host1 in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 345 of file top_egret.h.

◆ TOP_EGRET_SPI_HOST1_SIZE_BYTES

#define TOP_EGRET_SPI_HOST1_SIZE_BYTES 0x40u

Peripheral size for spi_host1 in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_SPI_HOST1_BASE_ADDR and TOP_EGRET_SPI_HOST1_BASE_ADDR + TOP_EGRET_SPI_HOST1_SIZE_BYTES.

Definition at line 355 of file top_egret.h.

◆ TOP_EGRET_SRAM_CTRL_MAIN_RAM_BASE_ADDR

#define TOP_EGRET_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000u

Memory base address for ram memory on sram_ctrl_main in top egret.

Definition at line 921 of file top_egret.h.

◆ TOP_EGRET_SRAM_CTRL_MAIN_RAM_SIZE_BYTES

#define TOP_EGRET_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000u

Memory size for ram memory on sram_ctrl_main in top egret.

Definition at line 926 of file top_egret.h.

◆ TOP_EGRET_SRAM_CTRL_MAIN_REGS_BASE_ADDR

#define TOP_EGRET_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000u

Peripheral base address for regs device on sram_ctrl_main in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 849 of file top_egret.h.

◆ TOP_EGRET_SRAM_CTRL_MAIN_REGS_SIZE_BYTES

#define TOP_EGRET_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40u

Peripheral size for regs device on sram_ctrl_main in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_SRAM_CTRL_MAIN_REGS_BASE_ADDR and TOP_EGRET_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_EGRET_SRAM_CTRL_MAIN_REGS_SIZE_BYTES.

Definition at line 859 of file top_egret.h.

◆ TOP_EGRET_SRAM_CTRL_RET_AON_RAM_BASE_ADDR

#define TOP_EGRET_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x40600000u

Memory base address for ram memory on sram_ctrl_ret_aon in top egret.

Definition at line 901 of file top_egret.h.

◆ TOP_EGRET_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES

#define TOP_EGRET_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000u

Memory size for ram memory on sram_ctrl_ret_aon in top egret.

Definition at line 906 of file top_egret.h.

◆ TOP_EGRET_SRAM_CTRL_RET_AON_REGS_BASE_ADDR

#define TOP_EGRET_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x40500000u

Peripheral base address for regs device on sram_ctrl_ret_aon in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 561 of file top_egret.h.

◆ TOP_EGRET_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES

#define TOP_EGRET_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x40u

Peripheral size for regs device on sram_ctrl_ret_aon in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_SRAM_CTRL_RET_AON_REGS_BASE_ADDR and TOP_EGRET_SRAM_CTRL_RET_AON_REGS_BASE_ADDR + TOP_EGRET_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES.

Definition at line 571 of file top_egret.h.

◆ TOP_EGRET_SYSRST_CTRL_AON_BASE_ADDR

#define TOP_EGRET_SYSRST_CTRL_AON_BASE_ADDR 0x40430000u

Peripheral base address for sysrst_ctrl_aon in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 435 of file top_egret.h.

◆ TOP_EGRET_SYSRST_CTRL_AON_SIZE_BYTES

#define TOP_EGRET_SYSRST_CTRL_AON_SIZE_BYTES 0x100u

Peripheral size for sysrst_ctrl_aon in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_SYSRST_CTRL_AON_BASE_ADDR and TOP_EGRET_SYSRST_CTRL_AON_BASE_ADDR + TOP_EGRET_SYSRST_CTRL_AON_SIZE_BYTES.

Definition at line 445 of file top_egret.h.

◆ TOP_EGRET_UART0_BASE_ADDR

#define TOP_EGRET_UART0_BASE_ADDR 0x40000000u

Peripheral base address for uart0 in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 39 of file top_egret.h.

◆ TOP_EGRET_UART0_SIZE_BYTES

#define TOP_EGRET_UART0_SIZE_BYTES 0x40u

Peripheral size for uart0 in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_UART0_BASE_ADDR and TOP_EGRET_UART0_BASE_ADDR + TOP_EGRET_UART0_SIZE_BYTES.

Definition at line 49 of file top_egret.h.

◆ TOP_EGRET_UART1_BASE_ADDR

#define TOP_EGRET_UART1_BASE_ADDR 0x40010000u

Peripheral base address for uart1 in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 57 of file top_egret.h.

◆ TOP_EGRET_UART1_SIZE_BYTES

#define TOP_EGRET_UART1_SIZE_BYTES 0x40u

Peripheral size for uart1 in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_UART1_BASE_ADDR and TOP_EGRET_UART1_BASE_ADDR + TOP_EGRET_UART1_SIZE_BYTES.

Definition at line 67 of file top_egret.h.

◆ TOP_EGRET_UART2_BASE_ADDR

#define TOP_EGRET_UART2_BASE_ADDR 0x40020000u

Peripheral base address for uart2 in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 75 of file top_egret.h.

◆ TOP_EGRET_UART2_SIZE_BYTES

#define TOP_EGRET_UART2_SIZE_BYTES 0x40u

Peripheral size for uart2 in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_UART2_BASE_ADDR and TOP_EGRET_UART2_BASE_ADDR + TOP_EGRET_UART2_SIZE_BYTES.

Definition at line 85 of file top_egret.h.

◆ TOP_EGRET_UART3_BASE_ADDR

#define TOP_EGRET_UART3_BASE_ADDR 0x40030000u

Peripheral base address for uart3 in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 93 of file top_egret.h.

◆ TOP_EGRET_UART3_SIZE_BYTES

#define TOP_EGRET_UART3_SIZE_BYTES 0x40u

Peripheral size for uart3 in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_UART3_BASE_ADDR and TOP_EGRET_UART3_BASE_ADDR + TOP_EGRET_UART3_SIZE_BYTES.

Definition at line 103 of file top_egret.h.

◆ TOP_EGRET_USBDEV_BASE_ADDR

#define TOP_EGRET_USBDEV_BASE_ADDR 0x40320000u

Peripheral base address for usbdev in top egret.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 363 of file top_egret.h.

◆ TOP_EGRET_USBDEV_SIZE_BYTES

#define TOP_EGRET_USBDEV_SIZE_BYTES 0x1000u

Peripheral size for usbdev in top egret.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EGRET_USBDEV_BASE_ADDR and TOP_EGRET_USBDEV_BASE_ADDR + TOP_EGRET_USBDEV_SIZE_BYTES.

Definition at line 373 of file top_egret.h.

Typedef Documentation

◆ top_egret_alert_id_t

typedef enum top_egret_alert_id top_egret_alert_id_t

Alert Handler Alert Source.

Enumeration of all Alert Handler Alert Sources. The alert sources belonging to the same peripheral are guaranteed to be consecutive.

◆ top_egret_alert_peripheral_t

typedef enum top_egret_alert_peripheral top_egret_alert_peripheral_t

Alert Handler Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding alert.

◆ top_egret_gateable_clocks_t

typedef enum top_egret_gateable_clocks top_egret_gateable_clocks_t

Clock Manager Software-Controlled ("Gated") Clocks.

The Software has full control over these clocks.

◆ top_egret_hintable_clocks_t

typedef enum top_egret_hintable_clocks top_egret_hintable_clocks_t

Clock Manager Software-Hinted Clocks.

The Software has partial control over these clocks. It can ask them to stop, but the clock manager is in control of whether the clock actually is stopped.

◆ top_egret_plic_irq_id_t

typedef enum top_egret_plic_irq_id top_egret_plic_irq_id_t

PLIC Interrupt Source.

Enumeration of all PLIC interrupt sources. The interrupt sources belonging to the same peripheral are guaranteed to be consecutive.

◆ top_egret_plic_peripheral_t

typedef enum top_egret_plic_peripheral top_egret_plic_peripheral_t

PLIC Interrupt Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding interrupt.

◆ top_egret_plic_target_t

typedef enum top_egret_plic_target top_egret_plic_target_t

PLIC Interrupt Target.

Enumeration used to determine which set of IE, CC, threshold registers to access for a given interrupt target.

Enumeration Type Documentation

◆ top_egret_alert_id

enum top_egret_alert_id

Alert Handler Alert Source.

Enumeration of all Alert Handler Alert Sources. The alert sources belonging to the same peripheral are guaranteed to be consecutive.

Enumerator
kTopEgretAlertIdUart0FatalFault	uart0_fatal_fault
kTopEgretAlertIdUart1FatalFault	uart1_fatal_fault
kTopEgretAlertIdUart2FatalFault	uart2_fatal_fault
kTopEgretAlertIdUart3FatalFault	uart3_fatal_fault
kTopEgretAlertIdGpioFatalFault	gpio_fatal_fault
kTopEgretAlertIdSpiDeviceFatalFault	spi_device_fatal_fault
kTopEgretAlertIdI2c0FatalFault	i2c0_fatal_fault
kTopEgretAlertIdI2c1FatalFault	i2c1_fatal_fault
kTopEgretAlertIdI2c2FatalFault	i2c2_fatal_fault
kTopEgretAlertIdPattgenFatalFault	pattgen_fatal_fault
kTopEgretAlertIdRvTimerFatalFault	rv_timer_fatal_fault
kTopEgretAlertIdOtpCtrlFatalMacroError	otp_ctrl_fatal_macro_error
kTopEgretAlertIdOtpCtrlFatalCheckError	otp_ctrl_fatal_check_error
kTopEgretAlertIdOtpCtrlFatalBusIntegError	otp_ctrl_fatal_bus_integ_error
kTopEgretAlertIdOtpCtrlFatalPrimOtpAlert	otp_ctrl_fatal_prim_otp_alert
kTopEgretAlertIdOtpCtrlRecovPrimOtpAlert	otp_ctrl_recov_prim_otp_alert
kTopEgretAlertIdLcCtrlFatalProgError	lc_ctrl_fatal_prog_error
kTopEgretAlertIdLcCtrlFatalStateError	lc_ctrl_fatal_state_error
kTopEgretAlertIdLcCtrlFatalBusIntegError	lc_ctrl_fatal_bus_integ_error
kTopEgretAlertIdSpiHost0FatalFault	spi_host0_fatal_fault
kTopEgretAlertIdSpiHost1FatalFault	spi_host1_fatal_fault
kTopEgretAlertIdUsbdevFatalFault	usbdev_fatal_fault
kTopEgretAlertIdPwrmgrAonFatalFault	pwrmgr_aon_fatal_fault
kTopEgretAlertIdRstmgrAonFatalFault	rstmgr_aon_fatal_fault
kTopEgretAlertIdRstmgrAonFatalCnstyFault	rstmgr_aon_fatal_cnsty_fault
kTopEgretAlertIdClkmgrAonRecovFault	clkmgr_aon_recov_fault
kTopEgretAlertIdClkmgrAonFatalFault	clkmgr_aon_fatal_fault
kTopEgretAlertIdSysrstCtrlAonFatalFault	sysrst_ctrl_aon_fatal_fault
kTopEgretAlertIdAdcCtrlAonFatalFault	adc_ctrl_aon_fatal_fault
kTopEgretAlertIdPwmAonFatalFault	pwm_aon_fatal_fault
kTopEgretAlertIdPinmuxAonFatalFault	pinmux_aon_fatal_fault
kTopEgretAlertIdAonTimerAonFatalFault	aon_timer_aon_fatal_fault
kTopEgretAlertIdSensorCtrlAonRecovAlert	sensor_ctrl_aon_recov_alert
kTopEgretAlertIdSensorCtrlAonFatalAlert	sensor_ctrl_aon_fatal_alert
kTopEgretAlertIdSramCtrlRetAonFatalError	sram_ctrl_ret_aon_fatal_error
kTopEgretAlertIdFlashCtrlRecovErr	flash_ctrl_recov_err
kTopEgretAlertIdFlashCtrlFatalStdErr	flash_ctrl_fatal_std_err
kTopEgretAlertIdFlashCtrlFatalErr	flash_ctrl_fatal_err
kTopEgretAlertIdFlashCtrlFatalPrimFlashAlert	flash_ctrl_fatal_prim_flash_alert
kTopEgretAlertIdFlashCtrlRecovPrimFlashAlert	flash_ctrl_recov_prim_flash_alert
kTopEgretAlertIdRvDmFatalFault	rv_dm_fatal_fault
kTopEgretAlertIdRvPlicFatalFault	rv_plic_fatal_fault
kTopEgretAlertIdAccFatal	acc_fatal
kTopEgretAlertIdAccRecov	acc_recov
kTopEgretAlertIdAesRecovCtrlUpdateErr	aes_recov_ctrl_update_err
kTopEgretAlertIdAesFatalFault	aes_fatal_fault
kTopEgretAlertIdHmacFatalFault	hmac_fatal_fault
kTopEgretAlertIdKmacRecovOperationErr	kmac_recov_operation_err
kTopEgretAlertIdKmacFatalFaultErr	kmac_fatal_fault_err
kTopEgretAlertIdKeymgrRecovOperationErr	keymgr_recov_operation_err
kTopEgretAlertIdKeymgrFatalFaultErr	keymgr_fatal_fault_err
kTopEgretAlertIdCsrngRecovAlert	csrng_recov_alert
kTopEgretAlertIdCsrngFatalAlert	csrng_fatal_alert
kTopEgretAlertIdEntropySrcRecovAlert	entropy_src_recov_alert
kTopEgretAlertIdEntropySrcFatalAlert	entropy_src_fatal_alert
kTopEgretAlertIdEdn0RecovAlert	edn0_recov_alert
kTopEgretAlertIdEdn0FatalAlert	edn0_fatal_alert
kTopEgretAlertIdEdn1RecovAlert	edn1_recov_alert
kTopEgretAlertIdEdn1FatalAlert	edn1_fatal_alert
kTopEgretAlertIdSramCtrlMainFatalError	sram_ctrl_main_fatal_error
kTopEgretAlertIdRomCtrlFatal	rom_ctrl_fatal
kTopEgretAlertIdRvCoreIbexFatalSwErr	rv_core_ibex_fatal_sw_err
kTopEgretAlertIdRvCoreIbexRecovSwErr	rv_core_ibex_recov_sw_err
kTopEgretAlertIdRvCoreIbexFatalHwErr	rv_core_ibex_fatal_hw_err
kTopEgretAlertIdRvCoreIbexRecovHwErr	rv_core_ibex_recov_hw_err

Definition at line 1255 of file top_egret.h.

◆ top_egret_alert_peripheral

enum top_egret_alert_peripheral

Alert Handler Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding alert.

Enumerator
kTopEgretAlertPeripheralExternal	External Peripheral.
kTopEgretAlertPeripheralUart0	uart0
kTopEgretAlertPeripheralUart1	uart1
kTopEgretAlertPeripheralUart2	uart2
kTopEgretAlertPeripheralUart3	uart3
kTopEgretAlertPeripheralGpio	gpio
kTopEgretAlertPeripheralSpiDevice	spi_device
kTopEgretAlertPeripheralI2c0	i2c0
kTopEgretAlertPeripheralI2c1	i2c1
kTopEgretAlertPeripheralI2c2	i2c2
kTopEgretAlertPeripheralPattgen	pattgen
kTopEgretAlertPeripheralRvTimer	rv_timer
kTopEgretAlertPeripheralOtpCtrl	otp_ctrl
kTopEgretAlertPeripheralLcCtrl	lc_ctrl
kTopEgretAlertPeripheralSpiHost0	spi_host0
kTopEgretAlertPeripheralSpiHost1	spi_host1
kTopEgretAlertPeripheralUsbdev	usbdev
kTopEgretAlertPeripheralPwrmgrAon	pwrmgr_aon
kTopEgretAlertPeripheralRstmgrAon	rstmgr_aon
kTopEgretAlertPeripheralClkmgrAon	clkmgr_aon
kTopEgretAlertPeripheralSysrstCtrlAon	sysrst_ctrl_aon
kTopEgretAlertPeripheralAdcCtrlAon	adc_ctrl_aon
kTopEgretAlertPeripheralPwmAon	pwm_aon
kTopEgretAlertPeripheralPinmuxAon	pinmux_aon
kTopEgretAlertPeripheralAonTimerAon	aon_timer_aon
kTopEgretAlertPeripheralSensorCtrlAon	sensor_ctrl_aon
kTopEgretAlertPeripheralSramCtrlRetAon	sram_ctrl_ret_aon
kTopEgretAlertPeripheralFlashCtrl	flash_ctrl
kTopEgretAlertPeripheralRvDm	rv_dm
kTopEgretAlertPeripheralRvPlic	rv_plic
kTopEgretAlertPeripheralAcc	acc
kTopEgretAlertPeripheralAes	aes
kTopEgretAlertPeripheralHmac	hmac
kTopEgretAlertPeripheralKmac	kmac
kTopEgretAlertPeripheralKeymgr	keymgr
kTopEgretAlertPeripheralCsrng	csrng
kTopEgretAlertPeripheralEntropySrc	entropy_src
kTopEgretAlertPeripheralEdn0	edn0
kTopEgretAlertPeripheralEdn1	edn1
kTopEgretAlertPeripheralSramCtrlMain	sram_ctrl_main
kTopEgretAlertPeripheralRomCtrl	rom_ctrl
kTopEgretAlertPeripheralRvCoreIbex	rv_core_ibex

Definition at line 1203 of file top_egret.h.

◆ top_egret_direct_pads

enum top_egret_direct_pads

Dedicated Pad Selects.

Definition at line 1604 of file top_egret.h.

◆ top_egret_gateable_clocks

enum top_egret_gateable_clocks

Clock Manager Software-Controlled ("Gated") Clocks.

The Software has full control over these clocks.

Enumerator
kTopEgretGateableClocksIoDiv4Peri	Clock clk_io_div4_peri in group peri.
kTopEgretGateableClocksIoDiv2Peri	Clock clk_io_div2_peri in group peri.
kTopEgretGateableClocksIoPeri	Clock clk_io_peri in group peri.
kTopEgretGateableClocksUsbPeri	Clock clk_usb_peri in group peri.

Definition at line 1720 of file top_egret.h.

◆ top_egret_hintable_clocks

enum top_egret_hintable_clocks

Clock Manager Software-Hinted Clocks.

The Software has partial control over these clocks. It can ask them to stop, but the clock manager is in control of whether the clock actually is stopped.

Enumerator
kTopEgretHintableClocksMainAcc	Clock clk_main_acc in group trans.
kTopEgretHintableClocksMainAes	Clock clk_main_aes in group trans.
kTopEgretHintableClocksMainHmac	Clock clk_main_hmac in group trans.
kTopEgretHintableClocksMainKmac	Clock clk_main_kmac in group trans.

Definition at line 1734 of file top_egret.h.

◆ top_egret_muxed_pads

enum top_egret_muxed_pads

Muxed Pad Selects.

Definition at line 1627 of file top_egret.h.

◆ top_egret_pinmux_insel

enum top_egret_pinmux_insel

Pinmux MIO Input Selector.

Enumerator
kTopEgretPinmuxInselConstantZero	Tie constantly to zero.
kTopEgretPinmuxInselConstantOne	Tie constantly to one.
kTopEgretPinmuxInselIoa0	MIO Pad 0.
kTopEgretPinmuxInselIoa1	MIO Pad 1.
kTopEgretPinmuxInselIoa2	MIO Pad 2.
kTopEgretPinmuxInselIoa3	MIO Pad 3.
kTopEgretPinmuxInselIoa4	MIO Pad 4.
kTopEgretPinmuxInselIoa5	MIO Pad 5.
kTopEgretPinmuxInselIoa6	MIO Pad 6.
kTopEgretPinmuxInselIoa7	MIO Pad 7.
kTopEgretPinmuxInselIoa8	MIO Pad 8.
kTopEgretPinmuxInselIob0	MIO Pad 9.
kTopEgretPinmuxInselIob1	MIO Pad 10.
kTopEgretPinmuxInselIob2	MIO Pad 11.
kTopEgretPinmuxInselIob3	MIO Pad 12.
kTopEgretPinmuxInselIob4	MIO Pad 13.
kTopEgretPinmuxInselIob5	MIO Pad 14.
kTopEgretPinmuxInselIob6	MIO Pad 15.
kTopEgretPinmuxInselIob7	MIO Pad 16.
kTopEgretPinmuxInselIob8	MIO Pad 17.
kTopEgretPinmuxInselIob9	MIO Pad 18.
kTopEgretPinmuxInselIob10	MIO Pad 19.
kTopEgretPinmuxInselIob11	MIO Pad 20.
kTopEgretPinmuxInselIob12	MIO Pad 21.
kTopEgretPinmuxInselIoc0	MIO Pad 22.
kTopEgretPinmuxInselIoc1	MIO Pad 23.
kTopEgretPinmuxInselIoc2	MIO Pad 24.
kTopEgretPinmuxInselIoc3	MIO Pad 25.
kTopEgretPinmuxInselIoc4	MIO Pad 26.
kTopEgretPinmuxInselIoc5	MIO Pad 27.
kTopEgretPinmuxInselIoc6	MIO Pad 28.
kTopEgretPinmuxInselIoc7	MIO Pad 29.
kTopEgretPinmuxInselIoc8	MIO Pad 30.
kTopEgretPinmuxInselIoc9	MIO Pad 31.
kTopEgretPinmuxInselIoc10	MIO Pad 32.
kTopEgretPinmuxInselIoc11	MIO Pad 33.
kTopEgretPinmuxInselIoc12	MIO Pad 34.
kTopEgretPinmuxInselIor0	MIO Pad 35.
kTopEgretPinmuxInselIor1	MIO Pad 36.
kTopEgretPinmuxInselIor2	MIO Pad 37.
kTopEgretPinmuxInselIor3	MIO Pad 38.
kTopEgretPinmuxInselIor4	MIO Pad 39.
kTopEgretPinmuxInselIor5	MIO Pad 40.
kTopEgretPinmuxInselIor6	MIO Pad 41.
kTopEgretPinmuxInselIor7	MIO Pad 42.
kTopEgretPinmuxInselIor10	MIO Pad 43.
kTopEgretPinmuxInselIor11	MIO Pad 44.
kTopEgretPinmuxInselIor12	MIO Pad 45.
kTopEgretPinmuxInselIor13	MIO Pad 46.

Definition at line 1409 of file top_egret.h.

◆ top_egret_pinmux_mio_out

enum top_egret_pinmux_mio_out

Pinmux MIO Output.

Enumerator
kTopEgretPinmuxMioOutIoa0	MIO Pad 0.
kTopEgretPinmuxMioOutIoa1	MIO Pad 1.
kTopEgretPinmuxMioOutIoa2	MIO Pad 2.
kTopEgretPinmuxMioOutIoa3	MIO Pad 3.
kTopEgretPinmuxMioOutIoa4	MIO Pad 4.
kTopEgretPinmuxMioOutIoa5	MIO Pad 5.
kTopEgretPinmuxMioOutIoa6	MIO Pad 6.
kTopEgretPinmuxMioOutIoa7	MIO Pad 7.
kTopEgretPinmuxMioOutIoa8	MIO Pad 8.
kTopEgretPinmuxMioOutIob0	MIO Pad 9.
kTopEgretPinmuxMioOutIob1	MIO Pad 10.
kTopEgretPinmuxMioOutIob2	MIO Pad 11.
kTopEgretPinmuxMioOutIob3	MIO Pad 12.
kTopEgretPinmuxMioOutIob4	MIO Pad 13.
kTopEgretPinmuxMioOutIob5	MIO Pad 14.
kTopEgretPinmuxMioOutIob6	MIO Pad 15.
kTopEgretPinmuxMioOutIob7	MIO Pad 16.
kTopEgretPinmuxMioOutIob8	MIO Pad 17.
kTopEgretPinmuxMioOutIob9	MIO Pad 18.
kTopEgretPinmuxMioOutIob10	MIO Pad 19.
kTopEgretPinmuxMioOutIob11	MIO Pad 20.
kTopEgretPinmuxMioOutIob12	MIO Pad 21.
kTopEgretPinmuxMioOutIoc0	MIO Pad 22.
kTopEgretPinmuxMioOutIoc1	MIO Pad 23.
kTopEgretPinmuxMioOutIoc2	MIO Pad 24.
kTopEgretPinmuxMioOutIoc3	MIO Pad 25.
kTopEgretPinmuxMioOutIoc4	MIO Pad 26.
kTopEgretPinmuxMioOutIoc5	MIO Pad 27.
kTopEgretPinmuxMioOutIoc6	MIO Pad 28.
kTopEgretPinmuxMioOutIoc7	MIO Pad 29.
kTopEgretPinmuxMioOutIoc8	MIO Pad 30.
kTopEgretPinmuxMioOutIoc9	MIO Pad 31.
kTopEgretPinmuxMioOutIoc10	MIO Pad 32.
kTopEgretPinmuxMioOutIoc11	MIO Pad 33.
kTopEgretPinmuxMioOutIoc12	MIO Pad 34.
kTopEgretPinmuxMioOutIor0	MIO Pad 35.
kTopEgretPinmuxMioOutIor1	MIO Pad 36.
kTopEgretPinmuxMioOutIor2	MIO Pad 37.
kTopEgretPinmuxMioOutIor3	MIO Pad 38.
kTopEgretPinmuxMioOutIor4	MIO Pad 39.
kTopEgretPinmuxMioOutIor5	MIO Pad 40.
kTopEgretPinmuxMioOutIor6	MIO Pad 41.
kTopEgretPinmuxMioOutIor7	MIO Pad 42.
kTopEgretPinmuxMioOutIor10	MIO Pad 43.
kTopEgretPinmuxMioOutIor11	MIO Pad 44.
kTopEgretPinmuxMioOutIor12	MIO Pad 45.
kTopEgretPinmuxMioOutIor13	MIO Pad 46.

Definition at line 1465 of file top_egret.h.

◆ top_egret_pinmux_outsel

enum top_egret_pinmux_outsel

Pinmux Peripheral Output Selector.

Enumerator
kTopEgretPinmuxOutselConstantZero	Tie constantly to zero.
kTopEgretPinmuxOutselConstantOne	Tie constantly to one.
kTopEgretPinmuxOutselConstantHighZ	Tie constantly to high-Z.
kTopEgretPinmuxOutselGpioGpio0	Peripheral Output 0.
kTopEgretPinmuxOutselGpioGpio1	Peripheral Output 1.
kTopEgretPinmuxOutselGpioGpio2	Peripheral Output 2.
kTopEgretPinmuxOutselGpioGpio3	Peripheral Output 3.
kTopEgretPinmuxOutselGpioGpio4	Peripheral Output 4.
kTopEgretPinmuxOutselGpioGpio5	Peripheral Output 5.
kTopEgretPinmuxOutselGpioGpio6	Peripheral Output 6.
kTopEgretPinmuxOutselGpioGpio7	Peripheral Output 7.
kTopEgretPinmuxOutselGpioGpio8	Peripheral Output 8.
kTopEgretPinmuxOutselGpioGpio9	Peripheral Output 9.
kTopEgretPinmuxOutselGpioGpio10	Peripheral Output 10.
kTopEgretPinmuxOutselGpioGpio11	Peripheral Output 11.
kTopEgretPinmuxOutselGpioGpio12	Peripheral Output 12.
kTopEgretPinmuxOutselGpioGpio13	Peripheral Output 13.
kTopEgretPinmuxOutselGpioGpio14	Peripheral Output 14.
kTopEgretPinmuxOutselGpioGpio15	Peripheral Output 15.
kTopEgretPinmuxOutselGpioGpio16	Peripheral Output 16.
kTopEgretPinmuxOutselGpioGpio17	Peripheral Output 17.
kTopEgretPinmuxOutselGpioGpio18	Peripheral Output 18.
kTopEgretPinmuxOutselGpioGpio19	Peripheral Output 19.
kTopEgretPinmuxOutselGpioGpio20	Peripheral Output 20.
kTopEgretPinmuxOutselGpioGpio21	Peripheral Output 21.
kTopEgretPinmuxOutselGpioGpio22	Peripheral Output 22.
kTopEgretPinmuxOutselGpioGpio23	Peripheral Output 23.
kTopEgretPinmuxOutselGpioGpio24	Peripheral Output 24.
kTopEgretPinmuxOutselGpioGpio25	Peripheral Output 25.
kTopEgretPinmuxOutselGpioGpio26	Peripheral Output 26.
kTopEgretPinmuxOutselGpioGpio27	Peripheral Output 27.
kTopEgretPinmuxOutselGpioGpio28	Peripheral Output 28.
kTopEgretPinmuxOutselGpioGpio29	Peripheral Output 29.
kTopEgretPinmuxOutselGpioGpio30	Peripheral Output 30.
kTopEgretPinmuxOutselGpioGpio31	Peripheral Output 31.
kTopEgretPinmuxOutselI2c0Sda	Peripheral Output 32.
kTopEgretPinmuxOutselI2c0Scl	Peripheral Output 33.
kTopEgretPinmuxOutselI2c1Sda	Peripheral Output 34.
kTopEgretPinmuxOutselI2c1Scl	Peripheral Output 35.
kTopEgretPinmuxOutselI2c2Sda	Peripheral Output 36.
kTopEgretPinmuxOutselI2c2Scl	Peripheral Output 37.
kTopEgretPinmuxOutselSpiHost1Sd0	Peripheral Output 38.
kTopEgretPinmuxOutselSpiHost1Sd1	Peripheral Output 39.
kTopEgretPinmuxOutselSpiHost1Sd2	Peripheral Output 40.
kTopEgretPinmuxOutselSpiHost1Sd3	Peripheral Output 41.
kTopEgretPinmuxOutselUart0Tx	Peripheral Output 42.
kTopEgretPinmuxOutselUart1Tx	Peripheral Output 43.
kTopEgretPinmuxOutselUart2Tx	Peripheral Output 44.
kTopEgretPinmuxOutselUart3Tx	Peripheral Output 45.
kTopEgretPinmuxOutselPattgenPda0Tx	Peripheral Output 46.
kTopEgretPinmuxOutselPattgenPcl0Tx	Peripheral Output 47.
kTopEgretPinmuxOutselPattgenPda1Tx	Peripheral Output 48.
kTopEgretPinmuxOutselPattgenPcl1Tx	Peripheral Output 49.
kTopEgretPinmuxOutselSpiHost1Sck	Peripheral Output 50.
kTopEgretPinmuxOutselSpiHost1Csb	Peripheral Output 51.
kTopEgretPinmuxOutselFlashMacroWrapperTdo	Peripheral Output 52.
kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut0	Peripheral Output 53.
kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut1	Peripheral Output 54.
kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut2	Peripheral Output 55.
kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut3	Peripheral Output 56.
kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut4	Peripheral Output 57.
kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut5	Peripheral Output 58.
kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut6	Peripheral Output 59.
kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut7	Peripheral Output 60.
kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut8	Peripheral Output 61.
kTopEgretPinmuxOutselPwmAonPwm0	Peripheral Output 62.
kTopEgretPinmuxOutselPwmAonPwm1	Peripheral Output 63.
kTopEgretPinmuxOutselPwmAonPwm2	Peripheral Output 64.
kTopEgretPinmuxOutselPwmAonPwm3	Peripheral Output 65.
kTopEgretPinmuxOutselPwmAonPwm4	Peripheral Output 66.
kTopEgretPinmuxOutselPwmAonPwm5	Peripheral Output 67.
kTopEgretPinmuxOutselOtpMacroTest0	Peripheral Output 68.
kTopEgretPinmuxOutselSysrstCtrlAonBatDisable	Peripheral Output 69.
kTopEgretPinmuxOutselSysrstCtrlAonKey0Out	Peripheral Output 70.
kTopEgretPinmuxOutselSysrstCtrlAonKey1Out	Peripheral Output 71.
kTopEgretPinmuxOutselSysrstCtrlAonKey2Out	Peripheral Output 72.
kTopEgretPinmuxOutselSysrstCtrlAonPwrbOut	Peripheral Output 73.
kTopEgretPinmuxOutselSysrstCtrlAonZ3Wakeup	Peripheral Output 74.

Definition at line 1519 of file top_egret.h.

◆ top_egret_pinmux_peripheral_in

enum top_egret_pinmux_peripheral_in

Pinmux Peripheral Input.

Enumerator
kTopEgretPinmuxPeripheralInGpioGpio0	Peripheral Input 0.
kTopEgretPinmuxPeripheralInGpioGpio1	Peripheral Input 1.
kTopEgretPinmuxPeripheralInGpioGpio2	Peripheral Input 2.
kTopEgretPinmuxPeripheralInGpioGpio3	Peripheral Input 3.
kTopEgretPinmuxPeripheralInGpioGpio4	Peripheral Input 4.
kTopEgretPinmuxPeripheralInGpioGpio5	Peripheral Input 5.
kTopEgretPinmuxPeripheralInGpioGpio6	Peripheral Input 6.
kTopEgretPinmuxPeripheralInGpioGpio7	Peripheral Input 7.
kTopEgretPinmuxPeripheralInGpioGpio8	Peripheral Input 8.
kTopEgretPinmuxPeripheralInGpioGpio9	Peripheral Input 9.
kTopEgretPinmuxPeripheralInGpioGpio10	Peripheral Input 10.
kTopEgretPinmuxPeripheralInGpioGpio11	Peripheral Input 11.
kTopEgretPinmuxPeripheralInGpioGpio12	Peripheral Input 12.
kTopEgretPinmuxPeripheralInGpioGpio13	Peripheral Input 13.
kTopEgretPinmuxPeripheralInGpioGpio14	Peripheral Input 14.
kTopEgretPinmuxPeripheralInGpioGpio15	Peripheral Input 15.
kTopEgretPinmuxPeripheralInGpioGpio16	Peripheral Input 16.
kTopEgretPinmuxPeripheralInGpioGpio17	Peripheral Input 17.
kTopEgretPinmuxPeripheralInGpioGpio18	Peripheral Input 18.
kTopEgretPinmuxPeripheralInGpioGpio19	Peripheral Input 19.
kTopEgretPinmuxPeripheralInGpioGpio20	Peripheral Input 20.
kTopEgretPinmuxPeripheralInGpioGpio21	Peripheral Input 21.
kTopEgretPinmuxPeripheralInGpioGpio22	Peripheral Input 22.
kTopEgretPinmuxPeripheralInGpioGpio23	Peripheral Input 23.
kTopEgretPinmuxPeripheralInGpioGpio24	Peripheral Input 24.
kTopEgretPinmuxPeripheralInGpioGpio25	Peripheral Input 25.
kTopEgretPinmuxPeripheralInGpioGpio26	Peripheral Input 26.
kTopEgretPinmuxPeripheralInGpioGpio27	Peripheral Input 27.
kTopEgretPinmuxPeripheralInGpioGpio28	Peripheral Input 28.
kTopEgretPinmuxPeripheralInGpioGpio29	Peripheral Input 29.
kTopEgretPinmuxPeripheralInGpioGpio30	Peripheral Input 30.
kTopEgretPinmuxPeripheralInGpioGpio31	Peripheral Input 31.
kTopEgretPinmuxPeripheralInI2c0Sda	Peripheral Input 32.
kTopEgretPinmuxPeripheralInI2c0Scl	Peripheral Input 33.
kTopEgretPinmuxPeripheralInI2c1Sda	Peripheral Input 34.
kTopEgretPinmuxPeripheralInI2c1Scl	Peripheral Input 35.
kTopEgretPinmuxPeripheralInI2c2Sda	Peripheral Input 36.
kTopEgretPinmuxPeripheralInI2c2Scl	Peripheral Input 37.
kTopEgretPinmuxPeripheralInSpiHost1Sd0	Peripheral Input 38.
kTopEgretPinmuxPeripheralInSpiHost1Sd1	Peripheral Input 39.
kTopEgretPinmuxPeripheralInSpiHost1Sd2	Peripheral Input 40.
kTopEgretPinmuxPeripheralInSpiHost1Sd3	Peripheral Input 41.
kTopEgretPinmuxPeripheralInUart0Rx	Peripheral Input 42.
kTopEgretPinmuxPeripheralInUart1Rx	Peripheral Input 43.
kTopEgretPinmuxPeripheralInUart2Rx	Peripheral Input 44.
kTopEgretPinmuxPeripheralInUart3Rx	Peripheral Input 45.
kTopEgretPinmuxPeripheralInSpiDeviceTpmCsb	Peripheral Input 46.
kTopEgretPinmuxPeripheralInFlashMacroWrapperTck	Peripheral Input 47.
kTopEgretPinmuxPeripheralInFlashMacroWrapperTms	Peripheral Input 48.
kTopEgretPinmuxPeripheralInFlashMacroWrapperTdi	Peripheral Input 49.
kTopEgretPinmuxPeripheralInSysrstCtrlAonAcPresent	Peripheral Input 50.
kTopEgretPinmuxPeripheralInSysrstCtrlAonKey0In	Peripheral Input 51.
kTopEgretPinmuxPeripheralInSysrstCtrlAonKey1In	Peripheral Input 52.
kTopEgretPinmuxPeripheralInSysrstCtrlAonKey2In	Peripheral Input 53.
kTopEgretPinmuxPeripheralInSysrstCtrlAonPwrbIn	Peripheral Input 54.
kTopEgretPinmuxPeripheralInSysrstCtrlAonLidOpen	Peripheral Input 55.
kTopEgretPinmuxPeripheralInUsbdevSense	Peripheral Input 56.

Definition at line 1345 of file top_egret.h.

◆ top_egret_plic_irq_id

enum top_egret_plic_irq_id

PLIC Interrupt Source.

Enumeration of all PLIC interrupt sources. The interrupt sources belonging to the same peripheral are guaranteed to be consecutive.

Enumerator
kTopEgretPlicIrqIdNone	No Interrupt.
kTopEgretPlicIrqIdUart0TxWatermark	uart0_tx_watermark
kTopEgretPlicIrqIdUart0RxWatermark	uart0_rx_watermark
kTopEgretPlicIrqIdUart0TxDone	uart0_tx_done
kTopEgretPlicIrqIdUart0RxOverflow	uart0_rx_overflow
kTopEgretPlicIrqIdUart0RxFrameErr	uart0_rx_frame_err
kTopEgretPlicIrqIdUart0RxBreakErr	uart0_rx_break_err
kTopEgretPlicIrqIdUart0RxTimeout	uart0_rx_timeout
kTopEgretPlicIrqIdUart0RxParityErr	uart0_rx_parity_err
kTopEgretPlicIrqIdUart0TxEmpty	uart0_tx_empty
kTopEgretPlicIrqIdUart1TxWatermark	uart1_tx_watermark
kTopEgretPlicIrqIdUart1RxWatermark	uart1_rx_watermark
kTopEgretPlicIrqIdUart1TxDone	uart1_tx_done
kTopEgretPlicIrqIdUart1RxOverflow	uart1_rx_overflow
kTopEgretPlicIrqIdUart1RxFrameErr	uart1_rx_frame_err
kTopEgretPlicIrqIdUart1RxBreakErr	uart1_rx_break_err
kTopEgretPlicIrqIdUart1RxTimeout	uart1_rx_timeout
kTopEgretPlicIrqIdUart1RxParityErr	uart1_rx_parity_err
kTopEgretPlicIrqIdUart1TxEmpty	uart1_tx_empty
kTopEgretPlicIrqIdUart2TxWatermark	uart2_tx_watermark
kTopEgretPlicIrqIdUart2RxWatermark	uart2_rx_watermark
kTopEgretPlicIrqIdUart2TxDone	uart2_tx_done
kTopEgretPlicIrqIdUart2RxOverflow	uart2_rx_overflow
kTopEgretPlicIrqIdUart2RxFrameErr	uart2_rx_frame_err
kTopEgretPlicIrqIdUart2RxBreakErr	uart2_rx_break_err
kTopEgretPlicIrqIdUart2RxTimeout	uart2_rx_timeout
kTopEgretPlicIrqIdUart2RxParityErr	uart2_rx_parity_err
kTopEgretPlicIrqIdUart2TxEmpty	uart2_tx_empty
kTopEgretPlicIrqIdUart3TxWatermark	uart3_tx_watermark
kTopEgretPlicIrqIdUart3RxWatermark	uart3_rx_watermark
kTopEgretPlicIrqIdUart3TxDone	uart3_tx_done
kTopEgretPlicIrqIdUart3RxOverflow	uart3_rx_overflow
kTopEgretPlicIrqIdUart3RxFrameErr	uart3_rx_frame_err
kTopEgretPlicIrqIdUart3RxBreakErr	uart3_rx_break_err
kTopEgretPlicIrqIdUart3RxTimeout	uart3_rx_timeout
kTopEgretPlicIrqIdUart3RxParityErr	uart3_rx_parity_err
kTopEgretPlicIrqIdUart3TxEmpty	uart3_tx_empty
kTopEgretPlicIrqIdGpioGpio0	gpio_gpio 0
kTopEgretPlicIrqIdGpioGpio1	gpio_gpio 1
kTopEgretPlicIrqIdGpioGpio2	gpio_gpio 2
kTopEgretPlicIrqIdGpioGpio3	gpio_gpio 3
kTopEgretPlicIrqIdGpioGpio4	gpio_gpio 4
kTopEgretPlicIrqIdGpioGpio5	gpio_gpio 5
kTopEgretPlicIrqIdGpioGpio6	gpio_gpio 6
kTopEgretPlicIrqIdGpioGpio7	gpio_gpio 7
kTopEgretPlicIrqIdGpioGpio8	gpio_gpio 8
kTopEgretPlicIrqIdGpioGpio9	gpio_gpio 9
kTopEgretPlicIrqIdGpioGpio10	gpio_gpio 10
kTopEgretPlicIrqIdGpioGpio11	gpio_gpio 11
kTopEgretPlicIrqIdGpioGpio12	gpio_gpio 12
kTopEgretPlicIrqIdGpioGpio13	gpio_gpio 13
kTopEgretPlicIrqIdGpioGpio14	gpio_gpio 14
kTopEgretPlicIrqIdGpioGpio15	gpio_gpio 15
kTopEgretPlicIrqIdGpioGpio16	gpio_gpio 16
kTopEgretPlicIrqIdGpioGpio17	gpio_gpio 17
kTopEgretPlicIrqIdGpioGpio18	gpio_gpio 18
kTopEgretPlicIrqIdGpioGpio19	gpio_gpio 19
kTopEgretPlicIrqIdGpioGpio20	gpio_gpio 20
kTopEgretPlicIrqIdGpioGpio21	gpio_gpio 21
kTopEgretPlicIrqIdGpioGpio22	gpio_gpio 22
kTopEgretPlicIrqIdGpioGpio23	gpio_gpio 23
kTopEgretPlicIrqIdGpioGpio24	gpio_gpio 24
kTopEgretPlicIrqIdGpioGpio25	gpio_gpio 25
kTopEgretPlicIrqIdGpioGpio26	gpio_gpio 26
kTopEgretPlicIrqIdGpioGpio27	gpio_gpio 27
kTopEgretPlicIrqIdGpioGpio28	gpio_gpio 28
kTopEgretPlicIrqIdGpioGpio29	gpio_gpio 29
kTopEgretPlicIrqIdGpioGpio30	gpio_gpio 30
kTopEgretPlicIrqIdGpioGpio31	gpio_gpio 31
kTopEgretPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty	spi_device_upload_cmdfifo_not_empty
kTopEgretPlicIrqIdSpiDeviceUploadPayloadNotEmpty	spi_device_upload_payload_not_empty
kTopEgretPlicIrqIdSpiDeviceUploadPayloadOverflow	spi_device_upload_payload_overflow
kTopEgretPlicIrqIdSpiDeviceReadbufWatermark	spi_device_readbuf_watermark
kTopEgretPlicIrqIdSpiDeviceReadbufFlip	spi_device_readbuf_flip
kTopEgretPlicIrqIdSpiDeviceTpmHeaderNotEmpty	spi_device_tpm_header_not_empty
kTopEgretPlicIrqIdSpiDeviceTpmRdfifoCmdEnd	spi_device_tpm_rdfifo_cmd_end
kTopEgretPlicIrqIdSpiDeviceTpmRdfifoDrop	spi_device_tpm_rdfifo_drop
kTopEgretPlicIrqIdI2c0FmtThreshold	i2c0_fmt_threshold
kTopEgretPlicIrqIdI2c0RxThreshold	i2c0_rx_threshold
kTopEgretPlicIrqIdI2c0AcqThreshold	i2c0_acq_threshold
kTopEgretPlicIrqIdI2c0RxOverflow	i2c0_rx_overflow
kTopEgretPlicIrqIdI2c0ControllerHalt	i2c0_controller_halt
kTopEgretPlicIrqIdI2c0SclInterference	i2c0_scl_interference
kTopEgretPlicIrqIdI2c0SdaInterference	i2c0_sda_interference
kTopEgretPlicIrqIdI2c0StretchTimeout	i2c0_stretch_timeout
kTopEgretPlicIrqIdI2c0SdaUnstable	i2c0_sda_unstable
kTopEgretPlicIrqIdI2c0CmdComplete	i2c0_cmd_complete
kTopEgretPlicIrqIdI2c0TxStretch	i2c0_tx_stretch
kTopEgretPlicIrqIdI2c0TxThreshold	i2c0_tx_threshold
kTopEgretPlicIrqIdI2c0AcqStretch	i2c0_acq_stretch
kTopEgretPlicIrqIdI2c0UnexpStop	i2c0_unexp_stop
kTopEgretPlicIrqIdI2c0HostTimeout	i2c0_host_timeout
kTopEgretPlicIrqIdI2c1FmtThreshold	i2c1_fmt_threshold
kTopEgretPlicIrqIdI2c1RxThreshold	i2c1_rx_threshold
kTopEgretPlicIrqIdI2c1AcqThreshold	i2c1_acq_threshold
kTopEgretPlicIrqIdI2c1RxOverflow	i2c1_rx_overflow
kTopEgretPlicIrqIdI2c1ControllerHalt	i2c1_controller_halt
kTopEgretPlicIrqIdI2c1SclInterference	i2c1_scl_interference
kTopEgretPlicIrqIdI2c1SdaInterference	i2c1_sda_interference
kTopEgretPlicIrqIdI2c1StretchTimeout	i2c1_stretch_timeout
kTopEgretPlicIrqIdI2c1SdaUnstable	i2c1_sda_unstable
kTopEgretPlicIrqIdI2c1CmdComplete	i2c1_cmd_complete
kTopEgretPlicIrqIdI2c1TxStretch	i2c1_tx_stretch
kTopEgretPlicIrqIdI2c1TxThreshold	i2c1_tx_threshold
kTopEgretPlicIrqIdI2c1AcqStretch	i2c1_acq_stretch
kTopEgretPlicIrqIdI2c1UnexpStop	i2c1_unexp_stop
kTopEgretPlicIrqIdI2c1HostTimeout	i2c1_host_timeout
kTopEgretPlicIrqIdI2c2FmtThreshold	i2c2_fmt_threshold
kTopEgretPlicIrqIdI2c2RxThreshold	i2c2_rx_threshold
kTopEgretPlicIrqIdI2c2AcqThreshold	i2c2_acq_threshold
kTopEgretPlicIrqIdI2c2RxOverflow	i2c2_rx_overflow
kTopEgretPlicIrqIdI2c2ControllerHalt	i2c2_controller_halt
kTopEgretPlicIrqIdI2c2SclInterference	i2c2_scl_interference
kTopEgretPlicIrqIdI2c2SdaInterference	i2c2_sda_interference
kTopEgretPlicIrqIdI2c2StretchTimeout	i2c2_stretch_timeout
kTopEgretPlicIrqIdI2c2SdaUnstable	i2c2_sda_unstable
kTopEgretPlicIrqIdI2c2CmdComplete	i2c2_cmd_complete
kTopEgretPlicIrqIdI2c2TxStretch	i2c2_tx_stretch
kTopEgretPlicIrqIdI2c2TxThreshold	i2c2_tx_threshold
kTopEgretPlicIrqIdI2c2AcqStretch	i2c2_acq_stretch
kTopEgretPlicIrqIdI2c2UnexpStop	i2c2_unexp_stop
kTopEgretPlicIrqIdI2c2HostTimeout	i2c2_host_timeout
kTopEgretPlicIrqIdPattgenDoneCh0	pattgen_done_ch0
kTopEgretPlicIrqIdPattgenDoneCh1	pattgen_done_ch1
kTopEgretPlicIrqIdRvTimerTimerExpiredHart0Timer0	rv_timer_timer_expired_hart0_timer0
kTopEgretPlicIrqIdOtpCtrlOtpOperationDone	otp_ctrl_otp_operation_done
kTopEgretPlicIrqIdOtpCtrlOtpError	otp_ctrl_otp_error
kTopEgretPlicIrqIdAlertHandlerClassa	alert_handler_classa
kTopEgretPlicIrqIdAlertHandlerClassb	alert_handler_classb
kTopEgretPlicIrqIdAlertHandlerClassc	alert_handler_classc
kTopEgretPlicIrqIdAlertHandlerClassd	alert_handler_classd
kTopEgretPlicIrqIdSpiHost0Error	spi_host0_error
kTopEgretPlicIrqIdSpiHost0SpiEvent	spi_host0_spi_event
kTopEgretPlicIrqIdSpiHost1Error	spi_host1_error
kTopEgretPlicIrqIdSpiHost1SpiEvent	spi_host1_spi_event
kTopEgretPlicIrqIdUsbdevPktReceived	usbdev_pkt_received
kTopEgretPlicIrqIdUsbdevPktSent	usbdev_pkt_sent
kTopEgretPlicIrqIdUsbdevDisconnected	usbdev_disconnected
kTopEgretPlicIrqIdUsbdevHostLost	usbdev_host_lost
kTopEgretPlicIrqIdUsbdevLinkReset	usbdev_link_reset
kTopEgretPlicIrqIdUsbdevLinkSuspend	usbdev_link_suspend
kTopEgretPlicIrqIdUsbdevLinkResume	usbdev_link_resume
kTopEgretPlicIrqIdUsbdevAvOutEmpty	usbdev_av_out_empty
kTopEgretPlicIrqIdUsbdevRxFull	usbdev_rx_full
kTopEgretPlicIrqIdUsbdevAvOverflow	usbdev_av_overflow
kTopEgretPlicIrqIdUsbdevLinkInErr	usbdev_link_in_err
kTopEgretPlicIrqIdUsbdevRxCrcErr	usbdev_rx_crc_err
kTopEgretPlicIrqIdUsbdevRxPidErr	usbdev_rx_pid_err
kTopEgretPlicIrqIdUsbdevRxBitstuffErr	usbdev_rx_bitstuff_err
kTopEgretPlicIrqIdUsbdevFrame	usbdev_frame
kTopEgretPlicIrqIdUsbdevPowered	usbdev_powered
kTopEgretPlicIrqIdUsbdevLinkOutErr	usbdev_link_out_err
kTopEgretPlicIrqIdUsbdevAvSetupEmpty	usbdev_av_setup_empty
kTopEgretPlicIrqIdPwrmgrAonWakeup	pwrmgr_aon_wakeup
kTopEgretPlicIrqIdSysrstCtrlAonEventDetected	sysrst_ctrl_aon_event_detected
kTopEgretPlicIrqIdAdcCtrlAonMatchPending	adc_ctrl_aon_match_pending
kTopEgretPlicIrqIdAonTimerAonWkupTimerExpired	aon_timer_aon_wkup_timer_expired
kTopEgretPlicIrqIdAonTimerAonWdogTimerBark	aon_timer_aon_wdog_timer_bark
kTopEgretPlicIrqIdSensorCtrlAonIoStatusChange	sensor_ctrl_aon_io_status_change
kTopEgretPlicIrqIdSensorCtrlAonInitStatusChange	sensor_ctrl_aon_init_status_change
kTopEgretPlicIrqIdFlashCtrlProgEmpty	flash_ctrl_prog_empty
kTopEgretPlicIrqIdFlashCtrlProgLvl	flash_ctrl_prog_lvl
kTopEgretPlicIrqIdFlashCtrlRdFull	flash_ctrl_rd_full
kTopEgretPlicIrqIdFlashCtrlRdLvl	flash_ctrl_rd_lvl
kTopEgretPlicIrqIdFlashCtrlOpDone	flash_ctrl_op_done
kTopEgretPlicIrqIdFlashCtrlCorrErr	flash_ctrl_corr_err
kTopEgretPlicIrqIdAccDone	acc_done
kTopEgretPlicIrqIdHmacHmacDone	hmac_hmac_done
kTopEgretPlicIrqIdHmacFifoEmpty	hmac_fifo_empty
kTopEgretPlicIrqIdHmacHmacErr	hmac_hmac_err
kTopEgretPlicIrqIdKmacKmacDone	kmac_kmac_done
kTopEgretPlicIrqIdKmacFifoEmpty	kmac_fifo_empty
kTopEgretPlicIrqIdKmacKmacErr	kmac_kmac_err
kTopEgretPlicIrqIdKeymgrOpDone	keymgr_op_done
kTopEgretPlicIrqIdCsrngCsCmdReqDone	csrng_cs_cmd_req_done
kTopEgretPlicIrqIdCsrngCsEntropyReq	csrng_cs_entropy_req
kTopEgretPlicIrqIdCsrngCsHwInstExc	csrng_cs_hw_inst_exc
kTopEgretPlicIrqIdCsrngCsFatalErr	csrng_cs_fatal_err
kTopEgretPlicIrqIdEntropySrcEsEntropyValid	entropy_src_es_entropy_valid
kTopEgretPlicIrqIdEntropySrcEsHealthTestFailed	entropy_src_es_health_test_failed
kTopEgretPlicIrqIdEntropySrcEsObserveFifoReady	entropy_src_es_observe_fifo_ready
kTopEgretPlicIrqIdEntropySrcEsFatalErr	entropy_src_es_fatal_err
kTopEgretPlicIrqIdEdn0EdnCmdReqDone	edn0_edn_cmd_req_done
kTopEgretPlicIrqIdEdn0EdnFatalErr	edn0_edn_fatal_err
kTopEgretPlicIrqIdEdn1EdnCmdReqDone	edn1_edn_cmd_req_done
kTopEgretPlicIrqIdEdn1EdnFatalErr	edn1_edn_fatal_err

Definition at line 986 of file top_egret.h.

◆ top_egret_plic_peripheral

enum top_egret_plic_peripheral

PLIC Interrupt Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding interrupt.

Enumerator
kTopEgretPlicPeripheralUnknown	Unknown Peripheral.
kTopEgretPlicPeripheralUart0	uart0
kTopEgretPlicPeripheralUart1	uart1
kTopEgretPlicPeripheralUart2	uart2
kTopEgretPlicPeripheralUart3	uart3
kTopEgretPlicPeripheralGpio	gpio
kTopEgretPlicPeripheralSpiDevice	spi_device
kTopEgretPlicPeripheralI2c0	i2c0
kTopEgretPlicPeripheralI2c1	i2c1
kTopEgretPlicPeripheralI2c2	i2c2
kTopEgretPlicPeripheralPattgen	pattgen
kTopEgretPlicPeripheralRvTimer	rv_timer
kTopEgretPlicPeripheralOtpCtrl	otp_ctrl
kTopEgretPlicPeripheralAlertHandler	alert_handler
kTopEgretPlicPeripheralSpiHost0	spi_host0
kTopEgretPlicPeripheralSpiHost1	spi_host1
kTopEgretPlicPeripheralUsbdev	usbdev
kTopEgretPlicPeripheralPwrmgrAon	pwrmgr_aon
kTopEgretPlicPeripheralSysrstCtrlAon	sysrst_ctrl_aon
kTopEgretPlicPeripheralAdcCtrlAon	adc_ctrl_aon
kTopEgretPlicPeripheralAonTimerAon	aon_timer_aon
kTopEgretPlicPeripheralSensorCtrlAon	sensor_ctrl_aon
kTopEgretPlicPeripheralFlashCtrl	flash_ctrl
kTopEgretPlicPeripheralAcc	acc
kTopEgretPlicPeripheralHmac	hmac
kTopEgretPlicPeripheralKmac	kmac
kTopEgretPlicPeripheralKeymgr	keymgr
kTopEgretPlicPeripheralCsrng	csrng
kTopEgretPlicPeripheralEntropySrc	entropy_src
kTopEgretPlicPeripheralEdn0	edn0
kTopEgretPlicPeripheralEdn1	edn1

Definition at line 945 of file top_egret.h.

◆ top_egret_plic_target

enum top_egret_plic_target

PLIC Interrupt Target.

Enumeration used to determine which set of IE, CC, threshold registers to access for a given interrupt target.

Enumerator
kTopEgretPlicTargetIbex0	Ibex Core 0.

Definition at line 1191 of file top_egret.h.

◆ top_egret_power_manager_reset_requests

enum top_egret_power_manager_reset_requests

Power Manager Reset Request Signals.

Definition at line 1709 of file top_egret.h.

◆ top_egret_power_manager_wake_ups

enum top_egret_power_manager_wake_ups

Power Manager Wakeup Signals.

Definition at line 1681 of file top_egret.h.

◆ top_egret_reset_manager_sw_resets

enum top_egret_reset_manager_sw_resets

Reset Manager Software Controlled Resets.

Definition at line 1694 of file top_egret.h.

Variable Documentation

◆ top_egret_alert_for_peripheral

const top_egret_alert_peripheral_t top_egret_alert_for_peripheral[65]

extern

Alert Handler Alert Source to Peripheral Map.

This array is a mapping from top_egret_alert_id_t to top_egret_alert_peripheral_t.

Definition at line 19 of file top_egret.c.

◆ top_egret_plic_interrupt_for_peripheral

const top_egret_plic_peripheral_t top_egret_plic_interrupt_for_peripheral[186]

extern

PLIC Interrupt Source to Peripheral Map.

This array is a mapping from top_egret_plic_irq_id_t to top_egret_plic_peripheral_t.

Definition at line 94 of file top_egret.c.

Macros

Typedefs

Enumerations

Variables

Detailed Description

Macro Definition Documentation

◆ NUM_DIO_PADS

◆ NUM_MIO_PADS

◆ PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET

◆ PINMUX_PERIPH_OUTSEL_IDX_OFFSET

◆ TOP_EGRET_ACC_BASE_ADDR

◆ TOP_EGRET_ACC_SIZE_BYTES

◆ TOP_EGRET_ADC_CTRL_AON_BASE_ADDR

◆ TOP_EGRET_ADC_CTRL_AON_SIZE_BYTES

◆ TOP_EGRET_AES_BASE_ADDR

◆ TOP_EGRET_AES_SIZE_BYTES

◆ TOP_EGRET_ALERT_HANDLER_BASE_ADDR

◆ TOP_EGRET_ALERT_HANDLER_SIZE_BYTES

◆ TOP_EGRET_AON_TIMER_AON_BASE_ADDR

◆ TOP_EGRET_AON_TIMER_AON_SIZE_BYTES

◆ TOP_EGRET_AST_BASE_ADDR

◆ TOP_EGRET_AST_SIZE_BYTES

◆ TOP_EGRET_CLKMGR_AON_BASE_ADDR

◆ TOP_EGRET_CLKMGR_AON_SIZE_BYTES

◆ TOP_EGRET_CSRNG_BASE_ADDR

◆ TOP_EGRET_CSRNG_SIZE_BYTES

◆ TOP_EGRET_EDN0_BASE_ADDR

◆ TOP_EGRET_EDN0_SIZE_BYTES

◆ TOP_EGRET_EDN1_BASE_ADDR

◆ TOP_EGRET_EDN1_SIZE_BYTES

◆ TOP_EGRET_ENTROPY_SRC_BASE_ADDR

◆ TOP_EGRET_ENTROPY_SRC_SIZE_BYTES

◆ TOP_EGRET_FLASH_CTRL_CORE_BASE_ADDR

◆ TOP_EGRET_FLASH_CTRL_CORE_SIZE_BYTES

◆ TOP_EGRET_FLASH_CTRL_MEM_BASE_ADDR

◆ TOP_EGRET_FLASH_CTRL_MEM_SIZE_BYTES

◆ TOP_EGRET_FLASH_MACRO_WRAPPER_BASE_ADDR

◆ TOP_EGRET_FLASH_MACRO_WRAPPER_SIZE_BYTES

◆ TOP_EGRET_GPIO_BASE_ADDR

◆ TOP_EGRET_GPIO_SIZE_BYTES

◆ TOP_EGRET_HMAC_BASE_ADDR

◆ TOP_EGRET_HMAC_SIZE_BYTES

◆ TOP_EGRET_I2C0_BASE_ADDR

◆ TOP_EGRET_I2C0_SIZE_BYTES

◆ TOP_EGRET_I2C1_BASE_ADDR

◆ TOP_EGRET_I2C1_SIZE_BYTES

◆ TOP_EGRET_I2C2_BASE_ADDR

◆ TOP_EGRET_I2C2_SIZE_BYTES

◆ TOP_EGRET_KEYMGR_BASE_ADDR

◆ TOP_EGRET_KEYMGR_SIZE_BYTES

◆ TOP_EGRET_KMAC_BASE_ADDR

◆ TOP_EGRET_KMAC_SIZE_BYTES

◆ TOP_EGRET_LC_CTRL_DMI_BASE_ADDR

◆ TOP_EGRET_LC_CTRL_DMI_SIZE_BYTES

◆ TOP_EGRET_LC_CTRL_REGS_BASE_ADDR

◆ TOP_EGRET_LC_CTRL_REGS_SIZE_BYTES

◆ TOP_EGRET_MMIO_BASE_ADDR

◆ TOP_EGRET_MMIO_SIZE_BYTES

◆ TOP_EGRET_OTP_CTRL_CORE_BASE_ADDR

◆ TOP_EGRET_OTP_CTRL_CORE_SIZE_BYTES

◆ TOP_EGRET_OTP_MACRO_PRIM_BASE_ADDR

◆ TOP_EGRET_OTP_MACRO_PRIM_SIZE_BYTES

◆ TOP_EGRET_PATTGEN_BASE_ADDR

◆ TOP_EGRET_PATTGEN_SIZE_BYTES

◆ TOP_EGRET_PINMUX_AON_BASE_ADDR

◆ TOP_EGRET_PINMUX_AON_SIZE_BYTES

◆ TOP_EGRET_PWM_AON_BASE_ADDR

◆ TOP_EGRET_PWM_AON_SIZE_BYTES

◆ TOP_EGRET_PWRMGR_AON_BASE_ADDR

◆ TOP_EGRET_PWRMGR_AON_SIZE_BYTES

◆ TOP_EGRET_ROM_CTRL_REGS_BASE_ADDR

◆ TOP_EGRET_ROM_CTRL_REGS_SIZE_BYTES

◆ TOP_EGRET_ROM_CTRL_ROM_BASE_ADDR

◆ TOP_EGRET_ROM_CTRL_ROM_SIZE_BYTES

◆ TOP_EGRET_RSTMGR_AON_BASE_ADDR

◆ TOP_EGRET_RSTMGR_AON_SIZE_BYTES

◆ TOP_EGRET_RV_CORE_IBEX_CFG_BASE_ADDR

◆ TOP_EGRET_RV_CORE_IBEX_CFG_SIZE_BYTES

◆ TOP_EGRET_RV_DM_DBG_BASE_ADDR

◆ TOP_EGRET_RV_DM_DBG_SIZE_BYTES