- Generated by
1.13.2
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Pavona Software APIs
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Generated register defines for dma. More...
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Generated register defines for dma.
Definition in file dma_regs.h.
| #define DMA_ADDR_SPACE_ID_DST_ASID_FIELD ((bitfield_field32_t) { .mask = DMA_ADDR_SPACE_ID_DST_ASID_MASK, .index = DMA_ADDR_SPACE_ID_DST_ASID_OFFSET }) |
Definition at line 89 of file dma_regs.h.
| #define DMA_ADDR_SPACE_ID_DST_ASID_MASK 0xfu |
Definition at line 87 of file dma_regs.h.
| #define DMA_ADDR_SPACE_ID_DST_ASID_OFFSET 4 |
Definition at line 88 of file dma_regs.h.
| #define DMA_ADDR_SPACE_ID_DST_ASID_VALUE_OT_ADDR 0x7 |
Definition at line 91 of file dma_regs.h.
| #define DMA_ADDR_SPACE_ID_DST_ASID_VALUE_SOC_ADDR 0xa |
Definition at line 92 of file dma_regs.h.
| #define DMA_ADDR_SPACE_ID_DST_ASID_VALUE_SYS_ADDR 0x9 |
Definition at line 93 of file dma_regs.h.
| #define DMA_ADDR_SPACE_ID_REG_OFFSET 0x20 |
Definition at line 78 of file dma_regs.h.
| #define DMA_ADDR_SPACE_ID_REG_RESVAL 0x77u |
Definition at line 79 of file dma_regs.h.
| #define DMA_ADDR_SPACE_ID_SRC_ASID_FIELD ((bitfield_field32_t) { .mask = DMA_ADDR_SPACE_ID_SRC_ASID_MASK, .index = DMA_ADDR_SPACE_ID_SRC_ASID_OFFSET }) |
Definition at line 82 of file dma_regs.h.
| #define DMA_ADDR_SPACE_ID_SRC_ASID_MASK 0xfu |
Definition at line 80 of file dma_regs.h.
| #define DMA_ADDR_SPACE_ID_SRC_ASID_OFFSET 0 |
Definition at line 81 of file dma_regs.h.
| #define DMA_ADDR_SPACE_ID_SRC_ASID_VALUE_OT_ADDR 0x7 |
Definition at line 84 of file dma_regs.h.
| #define DMA_ADDR_SPACE_ID_SRC_ASID_VALUE_SOC_ADDR 0xa |
Definition at line 85 of file dma_regs.h.
| #define DMA_ADDR_SPACE_ID_SRC_ASID_VALUE_SYS_ADDR 0x9 |
Definition at line 86 of file dma_regs.h.
| #define DMA_ALERT_TEST_FATAL_FAULT_BIT 0 |
Definition at line 57 of file dma_regs.h.
| #define DMA_ALERT_TEST_REG_OFFSET 0xc |
Definition at line 55 of file dma_regs.h.
| #define DMA_ALERT_TEST_REG_RESVAL 0x0u |
Definition at line 56 of file dma_regs.h.
| #define DMA_CFG_REGWEN_REG_OFFSET 0x34 |
Definition at line 122 of file dma_regs.h.
| #define DMA_CFG_REGWEN_REG_RESVAL 0x6u |
Definition at line 123 of file dma_regs.h.
| #define DMA_CFG_REGWEN_REGWEN_FIELD ((bitfield_field32_t) { .mask = DMA_CFG_REGWEN_REGWEN_MASK, .index = DMA_CFG_REGWEN_REGWEN_OFFSET }) |
Definition at line 126 of file dma_regs.h.
| #define DMA_CFG_REGWEN_REGWEN_MASK 0xfu |
Definition at line 124 of file dma_regs.h.
| #define DMA_CFG_REGWEN_REGWEN_OFFSET 0 |
Definition at line 125 of file dma_regs.h.
| #define DMA_CHUNK_DATA_SIZE_REG_OFFSET 0x3c |
Definition at line 135 of file dma_regs.h.
| #define DMA_CHUNK_DATA_SIZE_REG_RESVAL 0x0u |
Definition at line 136 of file dma_regs.h.
| #define DMA_CLEAR_INTR_BUS_BUS_FIELD ((bitfield_field32_t) { .mask = DMA_CLEAR_INTR_BUS_BUS_MASK, .index = DMA_CLEAR_INTR_BUS_BUS_OFFSET }) |
Definition at line 289 of file dma_regs.h.
| #define DMA_CLEAR_INTR_BUS_BUS_MASK 0x7ffu |
Definition at line 287 of file dma_regs.h.
| #define DMA_CLEAR_INTR_BUS_BUS_OFFSET 0 |
Definition at line 288 of file dma_regs.h.
| #define DMA_CLEAR_INTR_BUS_REG_OFFSET 0xa0 |
Definition at line 285 of file dma_regs.h.
| #define DMA_CLEAR_INTR_BUS_REG_RESVAL 0x0u |
Definition at line 286 of file dma_regs.h.
| #define DMA_CLEAR_INTR_SRC_REG_OFFSET 0x9c |
Definition at line 277 of file dma_regs.h.
| #define DMA_CLEAR_INTR_SRC_REG_RESVAL 0x0u |
Definition at line 278 of file dma_regs.h.
| #define DMA_CLEAR_INTR_SRC_SOURCE_FIELD ((bitfield_field32_t) { .mask = DMA_CLEAR_INTR_SRC_SOURCE_MASK, .index = DMA_CLEAR_INTR_SRC_SOURCE_OFFSET }) |
Definition at line 281 of file dma_regs.h.
| #define DMA_CLEAR_INTR_SRC_SOURCE_MASK 0x7ffu |
Definition at line 279 of file dma_regs.h.
| #define DMA_CLEAR_INTR_SRC_SOURCE_OFFSET 0 |
Definition at line 280 of file dma_regs.h.
| #define DMA_CONTROL_ABORT_BIT 27 |
Definition at line 163 of file dma_regs.h.
| #define DMA_CONTROL_DIGEST_SWAP_BIT 5 |
Definition at line 161 of file dma_regs.h.
| #define DMA_CONTROL_GO_BIT 31 |
Definition at line 164 of file dma_regs.h.
| #define DMA_CONTROL_HARDWARE_HANDSHAKE_ENABLE_BIT 4 |
Definition at line 160 of file dma_regs.h.
| #define DMA_CONTROL_INITIAL_TRANSFER_BIT 8 |
Definition at line 162 of file dma_regs.h.
| #define DMA_CONTROL_OPCODE_FIELD ((bitfield_field32_t) { .mask = DMA_CONTROL_OPCODE_MASK, .index = DMA_CONTROL_OPCODE_OFFSET }) |
Definition at line 154 of file dma_regs.h.
| #define DMA_CONTROL_OPCODE_MASK 0xfu |
Definition at line 152 of file dma_regs.h.
| #define DMA_CONTROL_OPCODE_OFFSET 0 |
Definition at line 153 of file dma_regs.h.
| #define DMA_CONTROL_OPCODE_VALUE_COPY 0x0 |
Definition at line 156 of file dma_regs.h.
| #define DMA_CONTROL_OPCODE_VALUE_SHA256 0x1 |
Definition at line 157 of file dma_regs.h.
| #define DMA_CONTROL_OPCODE_VALUE_SHA384 0x2 |
Definition at line 158 of file dma_regs.h.
| #define DMA_CONTROL_OPCODE_VALUE_SHA512 0x3 |
Definition at line 159 of file dma_regs.h.
| #define DMA_CONTROL_REG_OFFSET 0x44 |
Definition at line 150 of file dma_regs.h.
| #define DMA_CONTROL_REG_RESVAL 0x0u |
Definition at line 151 of file dma_regs.h.
| #define DMA_DST_ADDR_HI_REG_OFFSET 0x1c |
Definition at line 74 of file dma_regs.h.
| #define DMA_DST_ADDR_HI_REG_RESVAL 0x0u |
Definition at line 75 of file dma_regs.h.
| #define DMA_DST_ADDR_LO_REG_OFFSET 0x18 |
Definition at line 70 of file dma_regs.h.
| #define DMA_DST_ADDR_LO_REG_RESVAL 0x0u |
Definition at line 71 of file dma_regs.h.
| #define DMA_DST_CONFIG_INCREMENT_BIT 0 |
Definition at line 175 of file dma_regs.h.
| #define DMA_DST_CONFIG_REG_OFFSET 0x4c |
Definition at line 173 of file dma_regs.h.
| #define DMA_DST_CONFIG_REG_RESVAL 0x0u |
Definition at line 174 of file dma_regs.h.
| #define DMA_DST_CONFIG_WRAP_BIT 1 |
Definition at line 176 of file dma_regs.h.
| #define DMA_ENABLED_MEMORY_RANGE_BASE_REG_OFFSET 0x24 |
Definition at line 97 of file dma_regs.h.
| #define DMA_ENABLED_MEMORY_RANGE_BASE_REG_RESVAL 0x0u |
Definition at line 98 of file dma_regs.h.
| #define DMA_ENABLED_MEMORY_RANGE_LIMIT_REG_OFFSET 0x28 |
Definition at line 102 of file dma_regs.h.
| #define DMA_ENABLED_MEMORY_RANGE_LIMIT_REG_RESVAL 0x0u |
Definition at line 103 of file dma_regs.h.
| #define DMA_ERROR_CODE_ASID_ERROR_BIT 7 |
Definition at line 198 of file dma_regs.h.
| #define DMA_ERROR_CODE_BASE_LIMIT_ERROR_BIT 5 |
Definition at line 196 of file dma_regs.h.
| #define DMA_ERROR_CODE_BUS_ERROR_BIT 4 |
Definition at line 195 of file dma_regs.h.
| #define DMA_ERROR_CODE_DST_ADDR_ERROR_BIT 1 |
Definition at line 192 of file dma_regs.h.
| #define DMA_ERROR_CODE_OPCODE_ERROR_BIT 2 |
Definition at line 193 of file dma_regs.h.
| #define DMA_ERROR_CODE_RANGE_VALID_ERROR_BIT 6 |
Definition at line 197 of file dma_regs.h.
| #define DMA_ERROR_CODE_REG_OFFSET 0x54 |
Definition at line 189 of file dma_regs.h.
| #define DMA_ERROR_CODE_REG_RESVAL 0x0u |
Definition at line 190 of file dma_regs.h.
| #define DMA_ERROR_CODE_SIZE_ERROR_BIT 3 |
Definition at line 194 of file dma_regs.h.
| #define DMA_ERROR_CODE_SRC_ADDR_ERROR_BIT 0 |
Definition at line 191 of file dma_regs.h.
| #define DMA_HANDSHAKE_INTR_ENABLE_MASK_FIELD ((bitfield_field32_t) { .mask = DMA_HANDSHAKE_INTR_ENABLE_MASK_MASK, .index = DMA_HANDSHAKE_INTR_ENABLE_MASK_OFFSET }) |
Definition at line 273 of file dma_regs.h.
| #define DMA_HANDSHAKE_INTR_ENABLE_MASK_MASK 0x7ffu |
Definition at line 271 of file dma_regs.h.
| #define DMA_HANDSHAKE_INTR_ENABLE_MASK_OFFSET 0 |
Definition at line 272 of file dma_regs.h.
| #define DMA_HANDSHAKE_INTR_ENABLE_REG_OFFSET 0x98 |
Definition at line 269 of file dma_regs.h.
| #define DMA_HANDSHAKE_INTR_ENABLE_REG_RESVAL 0x7ffu |
Definition at line 270 of file dma_regs.h.
| #define DMA_INTR_COMMON_DMA_CHUNK_DONE_BIT 1 |
Definition at line 30 of file dma_regs.h.
| #define DMA_INTR_COMMON_DMA_DONE_BIT 0 |
Definition at line 29 of file dma_regs.h.
| #define DMA_INTR_COMMON_DMA_ERROR_BIT 2 |
Definition at line 31 of file dma_regs.h.
| #define DMA_INTR_ENABLE_DMA_CHUNK_DONE_BIT 1 |
Definition at line 44 of file dma_regs.h.
| #define DMA_INTR_ENABLE_DMA_DONE_BIT 0 |
Definition at line 43 of file dma_regs.h.
| #define DMA_INTR_ENABLE_DMA_ERROR_BIT 2 |
Definition at line 45 of file dma_regs.h.
| #define DMA_INTR_ENABLE_REG_OFFSET 0x4 |
Definition at line 41 of file dma_regs.h.
| #define DMA_INTR_ENABLE_REG_RESVAL 0x0u |
Definition at line 42 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_0_REG_OFFSET 0xa4 |
Definition at line 298 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_0_REG_RESVAL 0x0u |
Definition at line 299 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_10_REG_OFFSET 0xcc |
Definition at line 338 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_10_REG_RESVAL 0x0u |
Definition at line 339 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_1_REG_OFFSET 0xa8 |
Definition at line 302 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_1_REG_RESVAL 0x0u |
Definition at line 303 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_2_REG_OFFSET 0xac |
Definition at line 306 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_2_REG_RESVAL 0x0u |
Definition at line 307 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_3_REG_OFFSET 0xb0 |
Definition at line 310 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_3_REG_RESVAL 0x0u |
Definition at line 311 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_4_REG_OFFSET 0xb4 |
Definition at line 314 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_4_REG_RESVAL 0x0u |
Definition at line 315 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_5_REG_OFFSET 0xb8 |
Definition at line 318 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_5_REG_RESVAL 0x0u |
Definition at line 319 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_6_REG_OFFSET 0xbc |
Definition at line 322 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_6_REG_RESVAL 0x0u |
Definition at line 323 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_7_REG_OFFSET 0xc0 |
Definition at line 326 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_7_REG_RESVAL 0x0u |
Definition at line 327 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_8_REG_OFFSET 0xc4 |
Definition at line 330 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_8_REG_RESVAL 0x0u |
Definition at line 331 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_9_REG_OFFSET 0xc8 |
Definition at line 334 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_9_REG_RESVAL 0x0u |
Definition at line 335 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_ADDR_FIELD_WIDTH 32 |
Definition at line 294 of file dma_regs.h.
| #define DMA_INTR_SRC_ADDR_MULTIREG_COUNT 11 |
Definition at line 295 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_0_REG_OFFSET 0x124 |
Definition at line 346 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_0_REG_RESVAL 0x0u |
Definition at line 347 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_10_REG_OFFSET 0x14c |
Definition at line 386 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_10_REG_RESVAL 0x0u |
Definition at line 387 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_1_REG_OFFSET 0x128 |
Definition at line 350 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_1_REG_RESVAL 0x0u |
Definition at line 351 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_2_REG_OFFSET 0x12c |
Definition at line 354 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_2_REG_RESVAL 0x0u |
Definition at line 355 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_3_REG_OFFSET 0x130 |
Definition at line 358 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_3_REG_RESVAL 0x0u |
Definition at line 359 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_4_REG_OFFSET 0x134 |
Definition at line 362 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_4_REG_RESVAL 0x0u |
Definition at line 363 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_5_REG_OFFSET 0x138 |
Definition at line 366 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_5_REG_RESVAL 0x0u |
Definition at line 367 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_6_REG_OFFSET 0x13c |
Definition at line 370 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_6_REG_RESVAL 0x0u |
Definition at line 371 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_7_REG_OFFSET 0x140 |
Definition at line 374 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_7_REG_RESVAL 0x0u |
Definition at line 375 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_8_REG_OFFSET 0x144 |
Definition at line 378 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_8_REG_RESVAL 0x0u |
Definition at line 379 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_9_REG_OFFSET 0x148 |
Definition at line 382 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_9_REG_RESVAL 0x0u |
Definition at line 383 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_MULTIREG_COUNT 11 |
Definition at line 343 of file dma_regs.h.
| #define DMA_INTR_SRC_WR_VAL_WR_VAL_FIELD_WIDTH 32 |
Definition at line 342 of file dma_regs.h.
| #define DMA_INTR_STATE_DMA_CHUNK_DONE_BIT 1 |
Definition at line 37 of file dma_regs.h.
| #define DMA_INTR_STATE_DMA_DONE_BIT 0 |
Definition at line 36 of file dma_regs.h.
| #define DMA_INTR_STATE_DMA_ERROR_BIT 2 |
Definition at line 38 of file dma_regs.h.
| #define DMA_INTR_STATE_REG_OFFSET 0x0 |
Definition at line 34 of file dma_regs.h.
| #define DMA_INTR_STATE_REG_RESVAL 0x0u |
Definition at line 35 of file dma_regs.h.
| #define DMA_INTR_TEST_DMA_CHUNK_DONE_BIT 1 |
Definition at line 51 of file dma_regs.h.
| #define DMA_INTR_TEST_DMA_DONE_BIT 0 |
Definition at line 50 of file dma_regs.h.
| #define DMA_INTR_TEST_DMA_ERROR_BIT 2 |
Definition at line 52 of file dma_regs.h.
| #define DMA_INTR_TEST_REG_OFFSET 0x8 |
Definition at line 48 of file dma_regs.h.
| #define DMA_INTR_TEST_REG_RESVAL 0x0u |
Definition at line 49 of file dma_regs.h.
| #define DMA_PARAM_NUM_ALERTS 1 |
Definition at line 23 of file dma_regs.h.
| #define DMA_PARAM_NUM_INT_CLEAR_SOURCES 11 |
Definition at line 20 of file dma_regs.h.
| #define DMA_PARAM_REG_WIDTH 32 |
Definition at line 26 of file dma_regs.h.
| #define DMA_RANGE_REGWEN_REG_OFFSET 0x30 |
Definition at line 113 of file dma_regs.h.
| #define DMA_RANGE_REGWEN_REG_RESVAL 0x6u |
Definition at line 114 of file dma_regs.h.
| #define DMA_RANGE_REGWEN_REGWEN_FIELD ((bitfield_field32_t) { .mask = DMA_RANGE_REGWEN_REGWEN_MASK, .index = DMA_RANGE_REGWEN_REGWEN_OFFSET }) |
Definition at line 117 of file dma_regs.h.
| #define DMA_RANGE_REGWEN_REGWEN_MASK 0xfu |
Definition at line 115 of file dma_regs.h.
| #define DMA_RANGE_REGWEN_REGWEN_OFFSET 0 |
Definition at line 116 of file dma_regs.h.
| #define DMA_RANGE_VALID_RANGE_VALID_BIT 0 |
Definition at line 110 of file dma_regs.h.
| #define DMA_RANGE_VALID_REG_OFFSET 0x2c |
Definition at line 108 of file dma_regs.h.
| #define DMA_RANGE_VALID_REG_RESVAL 0x0u |
Definition at line 109 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_0_REG_OFFSET 0x58 |
Definition at line 205 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_0_REG_RESVAL 0x0u |
Definition at line 206 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_10_REG_OFFSET 0x80 |
Definition at line 245 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_10_REG_RESVAL 0x0u |
Definition at line 246 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_11_REG_OFFSET 0x84 |
Definition at line 249 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_11_REG_RESVAL 0x0u |
Definition at line 250 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_12_REG_OFFSET 0x88 |
Definition at line 253 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_12_REG_RESVAL 0x0u |
Definition at line 254 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_13_REG_OFFSET 0x8c |
Definition at line 257 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_13_REG_RESVAL 0x0u |
Definition at line 258 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_14_REG_OFFSET 0x90 |
Definition at line 261 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_14_REG_RESVAL 0x0u |
Definition at line 262 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_15_REG_OFFSET 0x94 |
Definition at line 265 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_15_REG_RESVAL 0x0u |
Definition at line 266 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_1_REG_OFFSET 0x5c |
Definition at line 209 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_1_REG_RESVAL 0x0u |
Definition at line 210 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_2_REG_OFFSET 0x60 |
Definition at line 213 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_2_REG_RESVAL 0x0u |
Definition at line 214 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_3_REG_OFFSET 0x64 |
Definition at line 217 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_3_REG_RESVAL 0x0u |
Definition at line 218 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_4_REG_OFFSET 0x68 |
Definition at line 221 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_4_REG_RESVAL 0x0u |
Definition at line 222 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_5_REG_OFFSET 0x6c |
Definition at line 225 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_5_REG_RESVAL 0x0u |
Definition at line 226 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_6_REG_OFFSET 0x70 |
Definition at line 229 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_6_REG_RESVAL 0x0u |
Definition at line 230 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_7_REG_OFFSET 0x74 |
Definition at line 233 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_7_REG_RESVAL 0x0u |
Definition at line 234 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_8_REG_OFFSET 0x78 |
Definition at line 237 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_8_REG_RESVAL 0x0u |
Definition at line 238 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_9_REG_OFFSET 0x7c |
Definition at line 241 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_9_REG_RESVAL 0x0u |
Definition at line 242 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_DATA_FIELD_WIDTH 32 |
Definition at line 201 of file dma_regs.h.
| #define DMA_SHA2_DIGEST_MULTIREG_COUNT 16 |
Definition at line 202 of file dma_regs.h.
| #define DMA_SRC_ADDR_HI_REG_OFFSET 0x14 |
Definition at line 65 of file dma_regs.h.
| #define DMA_SRC_ADDR_HI_REG_RESVAL 0x0u |
Definition at line 66 of file dma_regs.h.
| #define DMA_SRC_ADDR_LO_REG_OFFSET 0x10 |
Definition at line 61 of file dma_regs.h.
| #define DMA_SRC_ADDR_LO_REG_RESVAL 0x0u |
Definition at line 62 of file dma_regs.h.
| #define DMA_SRC_CONFIG_INCREMENT_BIT 0 |
Definition at line 169 of file dma_regs.h.
| #define DMA_SRC_CONFIG_REG_OFFSET 0x48 |
Definition at line 167 of file dma_regs.h.
| #define DMA_SRC_CONFIG_REG_RESVAL 0x0u |
Definition at line 168 of file dma_regs.h.
| #define DMA_SRC_CONFIG_WRAP_BIT 1 |
Definition at line 170 of file dma_regs.h.
| #define DMA_STATUS_ABORTED_BIT 2 |
Definition at line 183 of file dma_regs.h.
| #define DMA_STATUS_BUSY_BIT 0 |
Definition at line 181 of file dma_regs.h.
| #define DMA_STATUS_CHUNK_DONE_BIT 5 |
Definition at line 186 of file dma_regs.h.
| #define DMA_STATUS_DONE_BIT 1 |
Definition at line 182 of file dma_regs.h.
| #define DMA_STATUS_ERROR_BIT 3 |
Definition at line 184 of file dma_regs.h.
| #define DMA_STATUS_REG_OFFSET 0x50 |
Definition at line 179 of file dma_regs.h.
| #define DMA_STATUS_REG_RESVAL 0x0u |
Definition at line 180 of file dma_regs.h.
| #define DMA_STATUS_SHA2_DIGEST_VALID_BIT 4 |
Definition at line 185 of file dma_regs.h.
| #define DMA_TOTAL_DATA_SIZE_REG_OFFSET 0x38 |
Definition at line 130 of file dma_regs.h.
| #define DMA_TOTAL_DATA_SIZE_REG_RESVAL 0x0u |
Definition at line 131 of file dma_regs.h.
| #define DMA_TRANSFER_WIDTH_REG_OFFSET 0x40 |
Definition at line 139 of file dma_regs.h.
| #define DMA_TRANSFER_WIDTH_REG_RESVAL 0x2u |
Definition at line 140 of file dma_regs.h.
| #define DMA_TRANSFER_WIDTH_TRANSACTION_WIDTH_FIELD ((bitfield_field32_t) { .mask = DMA_TRANSFER_WIDTH_TRANSACTION_WIDTH_MASK, .index = DMA_TRANSFER_WIDTH_TRANSACTION_WIDTH_OFFSET }) |
Definition at line 143 of file dma_regs.h.
| #define DMA_TRANSFER_WIDTH_TRANSACTION_WIDTH_MASK 0x3u |
Definition at line 141 of file dma_regs.h.
| #define DMA_TRANSFER_WIDTH_TRANSACTION_WIDTH_OFFSET 0 |
Definition at line 142 of file dma_regs.h.
| #define DMA_TRANSFER_WIDTH_TRANSACTION_WIDTH_VALUE_FOUR_BYTE 0x2 |
Definition at line 147 of file dma_regs.h.
| #define DMA_TRANSFER_WIDTH_TRANSACTION_WIDTH_VALUE_ONE_BYTE 0x0 |
Definition at line 145 of file dma_regs.h.
| #define DMA_TRANSFER_WIDTH_TRANSACTION_WIDTH_VALUE_TWO_BYTE 0x1 |
Definition at line 146 of file dma_regs.h.
1.13.2