Pavona Software APIs
top_egret.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
6// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
7// util/topgen.py -t hw/top_egret/data/top_egret.hjson
8// -o hw/top_egret/
9
10#ifndef OPENTITAN_HW_TOP_EGRET_SW_AUTOGEN_TOP_EGRET_H_
11#define OPENTITAN_HW_TOP_EGRET_SW_AUTOGEN_TOP_EGRET_H_
12
13/**
14 * @file
15 * @brief Top-specific Definitions
16 *
17 * This file contains preprocessor and type definitions for use within the
18 * device C/C++ codebase.
19 *
20 * These definitions are for information that depends on the top-specific chip
21 * configuration, which includes:
22 * - Device Memory Information (for Peripherals and Memory)
23 * - PLIC Interrupt ID Names and Source Mappings
24 * - Alert ID Names and Source Mappings
25 * - Pinmux Pin/Select Names
26 * - Power Manager Wakeups
27 */
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
33/**
34 * Peripheral base address for uart0 in top egret.
35 *
36 * This should be used with #mmio_region_from_addr to access the memory-mapped
37 * registers associated with the peripheral (usually via a DIF).
38 */
39#define TOP_EGRET_UART0_BASE_ADDR 0x40000000u
40
41/**
42 * Peripheral size for uart0 in top egret.
43 *
44 * This is the size (in bytes) of the peripheral's reserved memory area. All
45 * memory-mapped registers associated with this peripheral should have an
46 * address between #TOP_EGRET_UART0_BASE_ADDR and
47 * `TOP_EGRET_UART0_BASE_ADDR + TOP_EGRET_UART0_SIZE_BYTES`.
48 */
49#define TOP_EGRET_UART0_SIZE_BYTES 0x40u
50
51/**
52 * Peripheral base address for uart1 in top egret.
53 *
54 * This should be used with #mmio_region_from_addr to access the memory-mapped
55 * registers associated with the peripheral (usually via a DIF).
56 */
57#define TOP_EGRET_UART1_BASE_ADDR 0x40010000u
58
59/**
60 * Peripheral size for uart1 in top egret.
61 *
62 * This is the size (in bytes) of the peripheral's reserved memory area. All
63 * memory-mapped registers associated with this peripheral should have an
64 * address between #TOP_EGRET_UART1_BASE_ADDR and
65 * `TOP_EGRET_UART1_BASE_ADDR + TOP_EGRET_UART1_SIZE_BYTES`.
66 */
67#define TOP_EGRET_UART1_SIZE_BYTES 0x40u
68
69/**
70 * Peripheral base address for uart2 in top egret.
71 *
72 * This should be used with #mmio_region_from_addr to access the memory-mapped
73 * registers associated with the peripheral (usually via a DIF).
74 */
75#define TOP_EGRET_UART2_BASE_ADDR 0x40020000u
76
77/**
78 * Peripheral size for uart2 in top egret.
79 *
80 * This is the size (in bytes) of the peripheral's reserved memory area. All
81 * memory-mapped registers associated with this peripheral should have an
82 * address between #TOP_EGRET_UART2_BASE_ADDR and
83 * `TOP_EGRET_UART2_BASE_ADDR + TOP_EGRET_UART2_SIZE_BYTES`.
84 */
85#define TOP_EGRET_UART2_SIZE_BYTES 0x40u
86
87/**
88 * Peripheral base address for uart3 in top egret.
89 *
90 * This should be used with #mmio_region_from_addr to access the memory-mapped
91 * registers associated with the peripheral (usually via a DIF).
92 */
93#define TOP_EGRET_UART3_BASE_ADDR 0x40030000u
94
95/**
96 * Peripheral size for uart3 in top egret.
97 *
98 * This is the size (in bytes) of the peripheral's reserved memory area. All
99 * memory-mapped registers associated with this peripheral should have an
100 * address between #TOP_EGRET_UART3_BASE_ADDR and
101 * `TOP_EGRET_UART3_BASE_ADDR + TOP_EGRET_UART3_SIZE_BYTES`.
102 */
103#define TOP_EGRET_UART3_SIZE_BYTES 0x40u
104
105/**
106 * Peripheral base address for gpio in top egret.
107 *
108 * This should be used with #mmio_region_from_addr to access the memory-mapped
109 * registers associated with the peripheral (usually via a DIF).
110 */
111#define TOP_EGRET_GPIO_BASE_ADDR 0x40040000u
112
113/**
114 * Peripheral size for gpio in top egret.
115 *
116 * This is the size (in bytes) of the peripheral's reserved memory area. All
117 * memory-mapped registers associated with this peripheral should have an
118 * address between #TOP_EGRET_GPIO_BASE_ADDR and
119 * `TOP_EGRET_GPIO_BASE_ADDR + TOP_EGRET_GPIO_SIZE_BYTES`.
120 */
121#define TOP_EGRET_GPIO_SIZE_BYTES 0x80u
122
123/**
124 * Peripheral base address for spi_device in top egret.
125 *
126 * This should be used with #mmio_region_from_addr to access the memory-mapped
127 * registers associated with the peripheral (usually via a DIF).
128 */
129#define TOP_EGRET_SPI_DEVICE_BASE_ADDR 0x40050000u
130
131/**
132 * Peripheral size for spi_device in top egret.
133 *
134 * This is the size (in bytes) of the peripheral's reserved memory area. All
135 * memory-mapped registers associated with this peripheral should have an
136 * address between #TOP_EGRET_SPI_DEVICE_BASE_ADDR and
137 * `TOP_EGRET_SPI_DEVICE_BASE_ADDR + TOP_EGRET_SPI_DEVICE_SIZE_BYTES`.
138 */
139#define TOP_EGRET_SPI_DEVICE_SIZE_BYTES 0x2000u
140
141/**
142 * Peripheral base address for i2c0 in top egret.
143 *
144 * This should be used with #mmio_region_from_addr to access the memory-mapped
145 * registers associated with the peripheral (usually via a DIF).
146 */
147#define TOP_EGRET_I2C0_BASE_ADDR 0x40080000u
148
149/**
150 * Peripheral size for i2c0 in top egret.
151 *
152 * This is the size (in bytes) of the peripheral's reserved memory area. All
153 * memory-mapped registers associated with this peripheral should have an
154 * address between #TOP_EGRET_I2C0_BASE_ADDR and
155 * `TOP_EGRET_I2C0_BASE_ADDR + TOP_EGRET_I2C0_SIZE_BYTES`.
156 */
157#define TOP_EGRET_I2C0_SIZE_BYTES 0x80u
158
159/**
160 * Peripheral base address for i2c1 in top egret.
161 *
162 * This should be used with #mmio_region_from_addr to access the memory-mapped
163 * registers associated with the peripheral (usually via a DIF).
164 */
165#define TOP_EGRET_I2C1_BASE_ADDR 0x40090000u
166
167/**
168 * Peripheral size for i2c1 in top egret.
169 *
170 * This is the size (in bytes) of the peripheral's reserved memory area. All
171 * memory-mapped registers associated with this peripheral should have an
172 * address between #TOP_EGRET_I2C1_BASE_ADDR and
173 * `TOP_EGRET_I2C1_BASE_ADDR + TOP_EGRET_I2C1_SIZE_BYTES`.
174 */
175#define TOP_EGRET_I2C1_SIZE_BYTES 0x80u
176
177/**
178 * Peripheral base address for i2c2 in top egret.
179 *
180 * This should be used with #mmio_region_from_addr to access the memory-mapped
181 * registers associated with the peripheral (usually via a DIF).
182 */
183#define TOP_EGRET_I2C2_BASE_ADDR 0x400A0000u
184
185/**
186 * Peripheral size for i2c2 in top egret.
187 *
188 * This is the size (in bytes) of the peripheral's reserved memory area. All
189 * memory-mapped registers associated with this peripheral should have an
190 * address between #TOP_EGRET_I2C2_BASE_ADDR and
191 * `TOP_EGRET_I2C2_BASE_ADDR + TOP_EGRET_I2C2_SIZE_BYTES`.
192 */
193#define TOP_EGRET_I2C2_SIZE_BYTES 0x80u
194
195/**
196 * Peripheral base address for pattgen in top egret.
197 *
198 * This should be used with #mmio_region_from_addr to access the memory-mapped
199 * registers associated with the peripheral (usually via a DIF).
200 */
201#define TOP_EGRET_PATTGEN_BASE_ADDR 0x400E0000u
202
203/**
204 * Peripheral size for pattgen in top egret.
205 *
206 * This is the size (in bytes) of the peripheral's reserved memory area. All
207 * memory-mapped registers associated with this peripheral should have an
208 * address between #TOP_EGRET_PATTGEN_BASE_ADDR and
209 * `TOP_EGRET_PATTGEN_BASE_ADDR + TOP_EGRET_PATTGEN_SIZE_BYTES`.
210 */
211#define TOP_EGRET_PATTGEN_SIZE_BYTES 0x40u
212
213/**
214 * Peripheral base address for rv_timer in top egret.
215 *
216 * This should be used with #mmio_region_from_addr to access the memory-mapped
217 * registers associated with the peripheral (usually via a DIF).
218 */
219#define TOP_EGRET_RV_TIMER_BASE_ADDR 0x40100000u
220
221/**
222 * Peripheral size for rv_timer in top egret.
223 *
224 * This is the size (in bytes) of the peripheral's reserved memory area. All
225 * memory-mapped registers associated with this peripheral should have an
226 * address between #TOP_EGRET_RV_TIMER_BASE_ADDR and
227 * `TOP_EGRET_RV_TIMER_BASE_ADDR + TOP_EGRET_RV_TIMER_SIZE_BYTES`.
228 */
229#define TOP_EGRET_RV_TIMER_SIZE_BYTES 0x200u
230
231/**
232 * Peripheral base address for core device on otp_ctrl in top egret.
233 *
234 * This should be used with #mmio_region_from_addr to access the memory-mapped
235 * registers associated with the peripheral (usually via a DIF).
236 */
237#define TOP_EGRET_OTP_CTRL_CORE_BASE_ADDR 0x40130000u
238
239/**
240 * Peripheral size for core device on otp_ctrl in top egret.
241 *
242 * This is the size (in bytes) of the peripheral's reserved memory area. All
243 * memory-mapped registers associated with this peripheral should have an
244 * address between #TOP_EGRET_OTP_CTRL_CORE_BASE_ADDR and
245 * `TOP_EGRET_OTP_CTRL_CORE_BASE_ADDR + TOP_EGRET_OTP_CTRL_CORE_SIZE_BYTES`.
246 */
247#define TOP_EGRET_OTP_CTRL_CORE_SIZE_BYTES 0x1000u
248
249/**
250 * Peripheral base address for prim device on otp_macro in top egret.
251 *
252 * This should be used with #mmio_region_from_addr to access the memory-mapped
253 * registers associated with the peripheral (usually via a DIF).
254 */
255#define TOP_EGRET_OTP_MACRO_PRIM_BASE_ADDR 0x40138000u
256
257/**
258 * Peripheral size for prim device on otp_macro in top egret.
259 *
260 * This is the size (in bytes) of the peripheral's reserved memory area. All
261 * memory-mapped registers associated with this peripheral should have an
262 * address between #TOP_EGRET_OTP_MACRO_PRIM_BASE_ADDR and
263 * `TOP_EGRET_OTP_MACRO_PRIM_BASE_ADDR + TOP_EGRET_OTP_MACRO_PRIM_SIZE_BYTES`.
264 */
265#define TOP_EGRET_OTP_MACRO_PRIM_SIZE_BYTES 0x20u
266
267/**
268 * Peripheral base address for regs device on lc_ctrl in top egret.
269 *
270 * This should be used with #mmio_region_from_addr to access the memory-mapped
271 * registers associated with the peripheral (usually via a DIF).
272 */
273#define TOP_EGRET_LC_CTRL_REGS_BASE_ADDR 0x40140000u
274
275/**
276 * Peripheral size for regs device on lc_ctrl in top egret.
277 *
278 * This is the size (in bytes) of the peripheral's reserved memory area. All
279 * memory-mapped registers associated with this peripheral should have an
280 * address between #TOP_EGRET_LC_CTRL_REGS_BASE_ADDR and
281 * `TOP_EGRET_LC_CTRL_REGS_BASE_ADDR + TOP_EGRET_LC_CTRL_REGS_SIZE_BYTES`.
282 */
283#define TOP_EGRET_LC_CTRL_REGS_SIZE_BYTES 0x100u
284
285/**
286 * Peripheral base address for dmi device on lc_ctrl in top egret.
287 *
288 * This should be used with #mmio_region_from_addr to access the memory-mapped
289 * registers associated with the peripheral (usually via a DIF).
290 */
291#define TOP_EGRET_LC_CTRL_DMI_BASE_ADDR 0x0u
292
293/**
294 * Peripheral size for dmi device on lc_ctrl in top egret.
295 *
296 * This is the size (in bytes) of the peripheral's reserved memory area. All
297 * memory-mapped registers associated with this peripheral should have an
298 * address between #TOP_EGRET_LC_CTRL_DMI_BASE_ADDR and
299 * `TOP_EGRET_LC_CTRL_DMI_BASE_ADDR + TOP_EGRET_LC_CTRL_DMI_SIZE_BYTES`.
300 */
301#define TOP_EGRET_LC_CTRL_DMI_SIZE_BYTES 0x1000u
302
303/**
304 * Peripheral base address for alert_handler in top egret.
305 *
306 * This should be used with #mmio_region_from_addr to access the memory-mapped
307 * registers associated with the peripheral (usually via a DIF).
308 */
309#define TOP_EGRET_ALERT_HANDLER_BASE_ADDR 0x40150000u
310
311/**
312 * Peripheral size for alert_handler in top egret.
313 *
314 * This is the size (in bytes) of the peripheral's reserved memory area. All
315 * memory-mapped registers associated with this peripheral should have an
316 * address between #TOP_EGRET_ALERT_HANDLER_BASE_ADDR and
317 * `TOP_EGRET_ALERT_HANDLER_BASE_ADDR + TOP_EGRET_ALERT_HANDLER_SIZE_BYTES`.
318 */
319#define TOP_EGRET_ALERT_HANDLER_SIZE_BYTES 0x800u
320
321/**
322 * Peripheral base address for spi_host0 in top egret.
323 *
324 * This should be used with #mmio_region_from_addr to access the memory-mapped
325 * registers associated with the peripheral (usually via a DIF).
326 */
327#define TOP_EGRET_SPI_HOST0_BASE_ADDR 0x40300000u
328
329/**
330 * Peripheral size for spi_host0 in top egret.
331 *
332 * This is the size (in bytes) of the peripheral's reserved memory area. All
333 * memory-mapped registers associated with this peripheral should have an
334 * address between #TOP_EGRET_SPI_HOST0_BASE_ADDR and
335 * `TOP_EGRET_SPI_HOST0_BASE_ADDR + TOP_EGRET_SPI_HOST0_SIZE_BYTES`.
336 */
337#define TOP_EGRET_SPI_HOST0_SIZE_BYTES 0x40u
338
339/**
340 * Peripheral base address for spi_host1 in top egret.
341 *
342 * This should be used with #mmio_region_from_addr to access the memory-mapped
343 * registers associated with the peripheral (usually via a DIF).
344 */
345#define TOP_EGRET_SPI_HOST1_BASE_ADDR 0x40310000u
346
347/**
348 * Peripheral size for spi_host1 in top egret.
349 *
350 * This is the size (in bytes) of the peripheral's reserved memory area. All
351 * memory-mapped registers associated with this peripheral should have an
352 * address between #TOP_EGRET_SPI_HOST1_BASE_ADDR and
353 * `TOP_EGRET_SPI_HOST1_BASE_ADDR + TOP_EGRET_SPI_HOST1_SIZE_BYTES`.
354 */
355#define TOP_EGRET_SPI_HOST1_SIZE_BYTES 0x40u
356
357/**
358 * Peripheral base address for usbdev in top egret.
359 *
360 * This should be used with #mmio_region_from_addr to access the memory-mapped
361 * registers associated with the peripheral (usually via a DIF).
362 */
363#define TOP_EGRET_USBDEV_BASE_ADDR 0x40320000u
364
365/**
366 * Peripheral size for usbdev in top egret.
367 *
368 * This is the size (in bytes) of the peripheral's reserved memory area. All
369 * memory-mapped registers associated with this peripheral should have an
370 * address between #TOP_EGRET_USBDEV_BASE_ADDR and
371 * `TOP_EGRET_USBDEV_BASE_ADDR + TOP_EGRET_USBDEV_SIZE_BYTES`.
372 */
373#define TOP_EGRET_USBDEV_SIZE_BYTES 0x1000u
374
375/**
376 * Peripheral base address for pwrmgr_aon in top egret.
377 *
378 * This should be used with #mmio_region_from_addr to access the memory-mapped
379 * registers associated with the peripheral (usually via a DIF).
380 */
381#define TOP_EGRET_PWRMGR_AON_BASE_ADDR 0x40400000u
382
383/**
384 * Peripheral size for pwrmgr_aon in top egret.
385 *
386 * This is the size (in bytes) of the peripheral's reserved memory area. All
387 * memory-mapped registers associated with this peripheral should have an
388 * address between #TOP_EGRET_PWRMGR_AON_BASE_ADDR and
389 * `TOP_EGRET_PWRMGR_AON_BASE_ADDR + TOP_EGRET_PWRMGR_AON_SIZE_BYTES`.
390 */
391#define TOP_EGRET_PWRMGR_AON_SIZE_BYTES 0x80u
392
393/**
394 * Peripheral base address for rstmgr_aon in top egret.
395 *
396 * This should be used with #mmio_region_from_addr to access the memory-mapped
397 * registers associated with the peripheral (usually via a DIF).
398 */
399#define TOP_EGRET_RSTMGR_AON_BASE_ADDR 0x40410000u
400
401/**
402 * Peripheral size for rstmgr_aon in top egret.
403 *
404 * This is the size (in bytes) of the peripheral's reserved memory area. All
405 * memory-mapped registers associated with this peripheral should have an
406 * address between #TOP_EGRET_RSTMGR_AON_BASE_ADDR and
407 * `TOP_EGRET_RSTMGR_AON_BASE_ADDR + TOP_EGRET_RSTMGR_AON_SIZE_BYTES`.
408 */
409#define TOP_EGRET_RSTMGR_AON_SIZE_BYTES 0x80u
410
411/**
412 * Peripheral base address for clkmgr_aon in top egret.
413 *
414 * This should be used with #mmio_region_from_addr to access the memory-mapped
415 * registers associated with the peripheral (usually via a DIF).
416 */
417#define TOP_EGRET_CLKMGR_AON_BASE_ADDR 0x40420000u
418
419/**
420 * Peripheral size for clkmgr_aon in top egret.
421 *
422 * This is the size (in bytes) of the peripheral's reserved memory area. All
423 * memory-mapped registers associated with this peripheral should have an
424 * address between #TOP_EGRET_CLKMGR_AON_BASE_ADDR and
425 * `TOP_EGRET_CLKMGR_AON_BASE_ADDR + TOP_EGRET_CLKMGR_AON_SIZE_BYTES`.
426 */
427#define TOP_EGRET_CLKMGR_AON_SIZE_BYTES 0x80u
428
429/**
430 * Peripheral base address for sysrst_ctrl_aon in top egret.
431 *
432 * This should be used with #mmio_region_from_addr to access the memory-mapped
433 * registers associated with the peripheral (usually via a DIF).
434 */
435#define TOP_EGRET_SYSRST_CTRL_AON_BASE_ADDR 0x40430000u
436
437/**
438 * Peripheral size for sysrst_ctrl_aon in top egret.
439 *
440 * This is the size (in bytes) of the peripheral's reserved memory area. All
441 * memory-mapped registers associated with this peripheral should have an
442 * address between #TOP_EGRET_SYSRST_CTRL_AON_BASE_ADDR and
443 * `TOP_EGRET_SYSRST_CTRL_AON_BASE_ADDR + TOP_EGRET_SYSRST_CTRL_AON_SIZE_BYTES`.
444 */
445#define TOP_EGRET_SYSRST_CTRL_AON_SIZE_BYTES 0x100u
446
447/**
448 * Peripheral base address for adc_ctrl_aon in top egret.
449 *
450 * This should be used with #mmio_region_from_addr to access the memory-mapped
451 * registers associated with the peripheral (usually via a DIF).
452 */
453#define TOP_EGRET_ADC_CTRL_AON_BASE_ADDR 0x40440000u
454
455/**
456 * Peripheral size for adc_ctrl_aon in top egret.
457 *
458 * This is the size (in bytes) of the peripheral's reserved memory area. All
459 * memory-mapped registers associated with this peripheral should have an
460 * address between #TOP_EGRET_ADC_CTRL_AON_BASE_ADDR and
461 * `TOP_EGRET_ADC_CTRL_AON_BASE_ADDR + TOP_EGRET_ADC_CTRL_AON_SIZE_BYTES`.
462 */
463#define TOP_EGRET_ADC_CTRL_AON_SIZE_BYTES 0x80u
464
465/**
466 * Peripheral base address for pwm_aon in top egret.
467 *
468 * This should be used with #mmio_region_from_addr to access the memory-mapped
469 * registers associated with the peripheral (usually via a DIF).
470 */
471#define TOP_EGRET_PWM_AON_BASE_ADDR 0x40450000u
472
473/**
474 * Peripheral size for pwm_aon in top egret.
475 *
476 * This is the size (in bytes) of the peripheral's reserved memory area. All
477 * memory-mapped registers associated with this peripheral should have an
478 * address between #TOP_EGRET_PWM_AON_BASE_ADDR and
479 * `TOP_EGRET_PWM_AON_BASE_ADDR + TOP_EGRET_PWM_AON_SIZE_BYTES`.
480 */
481#define TOP_EGRET_PWM_AON_SIZE_BYTES 0x80u
482
483/**
484 * Peripheral base address for pinmux_aon in top egret.
485 *
486 * This should be used with #mmio_region_from_addr to access the memory-mapped
487 * registers associated with the peripheral (usually via a DIF).
488 */
489#define TOP_EGRET_PINMUX_AON_BASE_ADDR 0x40460000u
490
491/**
492 * Peripheral size for pinmux_aon in top egret.
493 *
494 * This is the size (in bytes) of the peripheral's reserved memory area. All
495 * memory-mapped registers associated with this peripheral should have an
496 * address between #TOP_EGRET_PINMUX_AON_BASE_ADDR and
497 * `TOP_EGRET_PINMUX_AON_BASE_ADDR + TOP_EGRET_PINMUX_AON_SIZE_BYTES`.
498 */
499#define TOP_EGRET_PINMUX_AON_SIZE_BYTES 0x1000u
500
501/**
502 * Peripheral base address for aon_timer_aon in top egret.
503 *
504 * This should be used with #mmio_region_from_addr to access the memory-mapped
505 * registers associated with the peripheral (usually via a DIF).
506 */
507#define TOP_EGRET_AON_TIMER_AON_BASE_ADDR 0x40470000u
508
509/**
510 * Peripheral size for aon_timer_aon in top egret.
511 *
512 * This is the size (in bytes) of the peripheral's reserved memory area. All
513 * memory-mapped registers associated with this peripheral should have an
514 * address between #TOP_EGRET_AON_TIMER_AON_BASE_ADDR and
515 * `TOP_EGRET_AON_TIMER_AON_BASE_ADDR + TOP_EGRET_AON_TIMER_AON_SIZE_BYTES`.
516 */
517#define TOP_EGRET_AON_TIMER_AON_SIZE_BYTES 0x40u
518
519/**
520 * Peripheral base address for ast in top egret.
521 *
522 * This should be used with #mmio_region_from_addr to access the memory-mapped
523 * registers associated with the peripheral (usually via a DIF).
524 */
525#define TOP_EGRET_AST_BASE_ADDR 0x40480000u
526
527/**
528 * Peripheral size for ast in top egret.
529 *
530 * This is the size (in bytes) of the peripheral's reserved memory area. All
531 * memory-mapped registers associated with this peripheral should have an
532 * address between #TOP_EGRET_AST_BASE_ADDR and
533 * `TOP_EGRET_AST_BASE_ADDR + TOP_EGRET_AST_SIZE_BYTES`.
534 */
535#define TOP_EGRET_AST_SIZE_BYTES 0x400u
536
537/**
538 * Peripheral base address for sensor_ctrl_aon in top egret.
539 *
540 * This should be used with #mmio_region_from_addr to access the memory-mapped
541 * registers associated with the peripheral (usually via a DIF).
542 */
543#define TOP_EGRET_SENSOR_CTRL_AON_BASE_ADDR 0x40490000u
544
545/**
546 * Peripheral size for sensor_ctrl_aon in top egret.
547 *
548 * This is the size (in bytes) of the peripheral's reserved memory area. All
549 * memory-mapped registers associated with this peripheral should have an
550 * address between #TOP_EGRET_SENSOR_CTRL_AON_BASE_ADDR and
551 * `TOP_EGRET_SENSOR_CTRL_AON_BASE_ADDR + TOP_EGRET_SENSOR_CTRL_AON_SIZE_BYTES`.
552 */
553#define TOP_EGRET_SENSOR_CTRL_AON_SIZE_BYTES 0x80u
554
555/**
556 * Peripheral base address for regs device on sram_ctrl_ret_aon in top egret.
557 *
558 * This should be used with #mmio_region_from_addr to access the memory-mapped
559 * registers associated with the peripheral (usually via a DIF).
560 */
561#define TOP_EGRET_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x40500000u
562
563/**
564 * Peripheral size for regs device on sram_ctrl_ret_aon in top egret.
565 *
566 * This is the size (in bytes) of the peripheral's reserved memory area. All
567 * memory-mapped registers associated with this peripheral should have an
568 * address between #TOP_EGRET_SRAM_CTRL_RET_AON_REGS_BASE_ADDR and
569 * `TOP_EGRET_SRAM_CTRL_RET_AON_REGS_BASE_ADDR + TOP_EGRET_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES`.
570 */
571#define TOP_EGRET_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x40u
572
573/**
574 * Peripheral base address for core device on flash_ctrl in top egret.
575 *
576 * This should be used with #mmio_region_from_addr to access the memory-mapped
577 * registers associated with the peripheral (usually via a DIF).
578 */
579#define TOP_EGRET_FLASH_CTRL_CORE_BASE_ADDR 0x41000000u
580
581/**
582 * Peripheral size for core device on flash_ctrl in top egret.
583 *
584 * This is the size (in bytes) of the peripheral's reserved memory area. All
585 * memory-mapped registers associated with this peripheral should have an
586 * address between #TOP_EGRET_FLASH_CTRL_CORE_BASE_ADDR and
587 * `TOP_EGRET_FLASH_CTRL_CORE_BASE_ADDR + TOP_EGRET_FLASH_CTRL_CORE_SIZE_BYTES`.
588 */
589#define TOP_EGRET_FLASH_CTRL_CORE_SIZE_BYTES 0x200u
590
591/**
592 * Peripheral base address for flash_macro_wrapper in top egret.
593 *
594 * This should be used with #mmio_region_from_addr to access the memory-mapped
595 * registers associated with the peripheral (usually via a DIF).
596 */
597#define TOP_EGRET_FLASH_MACRO_WRAPPER_BASE_ADDR 0x41008000u
598
599/**
600 * Peripheral size for flash_macro_wrapper in top egret.
601 *
602 * This is the size (in bytes) of the peripheral's reserved memory area. All
603 * memory-mapped registers associated with this peripheral should have an
604 * address between #TOP_EGRET_FLASH_MACRO_WRAPPER_BASE_ADDR and
605 * `TOP_EGRET_FLASH_MACRO_WRAPPER_BASE_ADDR + TOP_EGRET_FLASH_MACRO_WRAPPER_SIZE_BYTES`.
606 */
607#define TOP_EGRET_FLASH_MACRO_WRAPPER_SIZE_BYTES 0x80u
608
609/**
610 * Peripheral base address for regs device on rv_dm in top egret.
611 *
612 * This should be used with #mmio_region_from_addr to access the memory-mapped
613 * registers associated with the peripheral (usually via a DIF).
614 */
615#define TOP_EGRET_RV_DM_REGS_BASE_ADDR 0x41200000u
616
617/**
618 * Peripheral size for regs device on rv_dm in top egret.
619 *
620 * This is the size (in bytes) of the peripheral's reserved memory area. All
621 * memory-mapped registers associated with this peripheral should have an
622 * address between #TOP_EGRET_RV_DM_REGS_BASE_ADDR and
623 * `TOP_EGRET_RV_DM_REGS_BASE_ADDR + TOP_EGRET_RV_DM_REGS_SIZE_BYTES`.
624 */
625#define TOP_EGRET_RV_DM_REGS_SIZE_BYTES 0x10u
626
627/**
628 * Peripheral base address for mem device on rv_dm in top egret.
629 *
630 * This should be used with #mmio_region_from_addr to access the memory-mapped
631 * registers associated with the peripheral (usually via a DIF).
632 */
633#define TOP_EGRET_RV_DM_MEM_BASE_ADDR 0x10000u
634
635/**
636 * Peripheral size for mem device on rv_dm in top egret.
637 *
638 * This is the size (in bytes) of the peripheral's reserved memory area. All
639 * memory-mapped registers associated with this peripheral should have an
640 * address between #TOP_EGRET_RV_DM_MEM_BASE_ADDR and
641 * `TOP_EGRET_RV_DM_MEM_BASE_ADDR + TOP_EGRET_RV_DM_MEM_SIZE_BYTES`.
642 */
643#define TOP_EGRET_RV_DM_MEM_SIZE_BYTES 0x1000u
644
645/**
646 * Peripheral base address for dbg device on rv_dm in top egret.
647 *
648 * This should be used with #mmio_region_from_addr to access the memory-mapped
649 * registers associated with the peripheral (usually via a DIF).
650 */
651#define TOP_EGRET_RV_DM_DBG_BASE_ADDR 0x1000u
652
653/**
654 * Peripheral size for dbg device on rv_dm in top egret.
655 *
656 * This is the size (in bytes) of the peripheral's reserved memory area. All
657 * memory-mapped registers associated with this peripheral should have an
658 * address between #TOP_EGRET_RV_DM_DBG_BASE_ADDR and
659 * `TOP_EGRET_RV_DM_DBG_BASE_ADDR + TOP_EGRET_RV_DM_DBG_SIZE_BYTES`.
660 */
661#define TOP_EGRET_RV_DM_DBG_SIZE_BYTES 0x200u
662
663/**
664 * Peripheral base address for rv_plic in top egret.
665 *
666 * This should be used with #mmio_region_from_addr to access the memory-mapped
667 * registers associated with the peripheral (usually via a DIF).
668 */
669#define TOP_EGRET_RV_PLIC_BASE_ADDR 0x48000000u
670
671/**
672 * Peripheral size for rv_plic in top egret.
673 *
674 * This is the size (in bytes) of the peripheral's reserved memory area. All
675 * memory-mapped registers associated with this peripheral should have an
676 * address between #TOP_EGRET_RV_PLIC_BASE_ADDR and
677 * `TOP_EGRET_RV_PLIC_BASE_ADDR + TOP_EGRET_RV_PLIC_SIZE_BYTES`.
678 */
679#define TOP_EGRET_RV_PLIC_SIZE_BYTES 0x8000000u
680
681/**
682 * Peripheral base address for acc in top egret.
683 *
684 * This should be used with #mmio_region_from_addr to access the memory-mapped
685 * registers associated with the peripheral (usually via a DIF).
686 */
687#define TOP_EGRET_ACC_BASE_ADDR 0x41300000u
688
689/**
690 * Peripheral size for acc in top egret.
691 *
692 * This is the size (in bytes) of the peripheral's reserved memory area. All
693 * memory-mapped registers associated with this peripheral should have an
694 * address between #TOP_EGRET_ACC_BASE_ADDR and
695 * `TOP_EGRET_ACC_BASE_ADDR + TOP_EGRET_ACC_SIZE_BYTES`.
696 */
697#define TOP_EGRET_ACC_SIZE_BYTES 0x20000u
698
699/**
700 * Peripheral base address for aes in top egret.
701 *
702 * This should be used with #mmio_region_from_addr to access the memory-mapped
703 * registers associated with the peripheral (usually via a DIF).
704 */
705#define TOP_EGRET_AES_BASE_ADDR 0x41100000u
706
707/**
708 * Peripheral size for aes in top egret.
709 *
710 * This is the size (in bytes) of the peripheral's reserved memory area. All
711 * memory-mapped registers associated with this peripheral should have an
712 * address between #TOP_EGRET_AES_BASE_ADDR and
713 * `TOP_EGRET_AES_BASE_ADDR + TOP_EGRET_AES_SIZE_BYTES`.
714 */
715#define TOP_EGRET_AES_SIZE_BYTES 0x100u
716
717/**
718 * Peripheral base address for hmac in top egret.
719 *
720 * This should be used with #mmio_region_from_addr to access the memory-mapped
721 * registers associated with the peripheral (usually via a DIF).
722 */
723#define TOP_EGRET_HMAC_BASE_ADDR 0x41110000u
724
725/**
726 * Peripheral size for hmac in top egret.
727 *
728 * This is the size (in bytes) of the peripheral's reserved memory area. All
729 * memory-mapped registers associated with this peripheral should have an
730 * address between #TOP_EGRET_HMAC_BASE_ADDR and
731 * `TOP_EGRET_HMAC_BASE_ADDR + TOP_EGRET_HMAC_SIZE_BYTES`.
732 */
733#define TOP_EGRET_HMAC_SIZE_BYTES 0x2000u
734
735/**
736 * Peripheral base address for kmac in top egret.
737 *
738 * This should be used with #mmio_region_from_addr to access the memory-mapped
739 * registers associated with the peripheral (usually via a DIF).
740 */
741#define TOP_EGRET_KMAC_BASE_ADDR 0x41120000u
742
743/**
744 * Peripheral size for kmac in top egret.
745 *
746 * This is the size (in bytes) of the peripheral's reserved memory area. All
747 * memory-mapped registers associated with this peripheral should have an
748 * address between #TOP_EGRET_KMAC_BASE_ADDR and
749 * `TOP_EGRET_KMAC_BASE_ADDR + TOP_EGRET_KMAC_SIZE_BYTES`.
750 */
751#define TOP_EGRET_KMAC_SIZE_BYTES 0x1000u
752
753/**
754 * Peripheral base address for keymgr in top egret.
755 *
756 * This should be used with #mmio_region_from_addr to access the memory-mapped
757 * registers associated with the peripheral (usually via a DIF).
758 */
759#define TOP_EGRET_KEYMGR_BASE_ADDR 0x41140000u
760
761/**
762 * Peripheral size for keymgr in top egret.
763 *
764 * This is the size (in bytes) of the peripheral's reserved memory area. All
765 * memory-mapped registers associated with this peripheral should have an
766 * address between #TOP_EGRET_KEYMGR_BASE_ADDR and
767 * `TOP_EGRET_KEYMGR_BASE_ADDR + TOP_EGRET_KEYMGR_SIZE_BYTES`.
768 */
769#define TOP_EGRET_KEYMGR_SIZE_BYTES 0x100u
770
771/**
772 * Peripheral base address for csrng in top egret.
773 *
774 * This should be used with #mmio_region_from_addr to access the memory-mapped
775 * registers associated with the peripheral (usually via a DIF).
776 */
777#define TOP_EGRET_CSRNG_BASE_ADDR 0x41150000u
778
779/**
780 * Peripheral size for csrng in top egret.
781 *
782 * This is the size (in bytes) of the peripheral's reserved memory area. All
783 * memory-mapped registers associated with this peripheral should have an
784 * address between #TOP_EGRET_CSRNG_BASE_ADDR and
785 * `TOP_EGRET_CSRNG_BASE_ADDR + TOP_EGRET_CSRNG_SIZE_BYTES`.
786 */
787#define TOP_EGRET_CSRNG_SIZE_BYTES 0x80u
788
789/**
790 * Peripheral base address for entropy_src in top egret.
791 *
792 * This should be used with #mmio_region_from_addr to access the memory-mapped
793 * registers associated with the peripheral (usually via a DIF).
794 */
795#define TOP_EGRET_ENTROPY_SRC_BASE_ADDR 0x41160000u
796
797/**
798 * Peripheral size for entropy_src in top egret.
799 *
800 * This is the size (in bytes) of the peripheral's reserved memory area. All
801 * memory-mapped registers associated with this peripheral should have an
802 * address between #TOP_EGRET_ENTROPY_SRC_BASE_ADDR and
803 * `TOP_EGRET_ENTROPY_SRC_BASE_ADDR + TOP_EGRET_ENTROPY_SRC_SIZE_BYTES`.
804 */
805#define TOP_EGRET_ENTROPY_SRC_SIZE_BYTES 0x100u
806
807/**
808 * Peripheral base address for edn0 in top egret.
809 *
810 * This should be used with #mmio_region_from_addr to access the memory-mapped
811 * registers associated with the peripheral (usually via a DIF).
812 */
813#define TOP_EGRET_EDN0_BASE_ADDR 0x41170000u
814
815/**
816 * Peripheral size for edn0 in top egret.
817 *
818 * This is the size (in bytes) of the peripheral's reserved memory area. All
819 * memory-mapped registers associated with this peripheral should have an
820 * address between #TOP_EGRET_EDN0_BASE_ADDR and
821 * `TOP_EGRET_EDN0_BASE_ADDR + TOP_EGRET_EDN0_SIZE_BYTES`.
822 */
823#define TOP_EGRET_EDN0_SIZE_BYTES 0x80u
824
825/**
826 * Peripheral base address for edn1 in top egret.
827 *
828 * This should be used with #mmio_region_from_addr to access the memory-mapped
829 * registers associated with the peripheral (usually via a DIF).
830 */
831#define TOP_EGRET_EDN1_BASE_ADDR 0x41180000u
832
833/**
834 * Peripheral size for edn1 in top egret.
835 *
836 * This is the size (in bytes) of the peripheral's reserved memory area. All
837 * memory-mapped registers associated with this peripheral should have an
838 * address between #TOP_EGRET_EDN1_BASE_ADDR and
839 * `TOP_EGRET_EDN1_BASE_ADDR + TOP_EGRET_EDN1_SIZE_BYTES`.
840 */
841#define TOP_EGRET_EDN1_SIZE_BYTES 0x80u
842
843/**
844 * Peripheral base address for regs device on sram_ctrl_main in top egret.
845 *
846 * This should be used with #mmio_region_from_addr to access the memory-mapped
847 * registers associated with the peripheral (usually via a DIF).
848 */
849#define TOP_EGRET_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000u
850
851/**
852 * Peripheral size for regs device on sram_ctrl_main in top egret.
853 *
854 * This is the size (in bytes) of the peripheral's reserved memory area. All
855 * memory-mapped registers associated with this peripheral should have an
856 * address between #TOP_EGRET_SRAM_CTRL_MAIN_REGS_BASE_ADDR and
857 * `TOP_EGRET_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_EGRET_SRAM_CTRL_MAIN_REGS_SIZE_BYTES`.
858 */
859#define TOP_EGRET_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40u
860
861/**
862 * Peripheral base address for regs device on rom_ctrl in top egret.
863 *
864 * This should be used with #mmio_region_from_addr to access the memory-mapped
865 * registers associated with the peripheral (usually via a DIF).
866 */
867#define TOP_EGRET_ROM_CTRL_REGS_BASE_ADDR 0x411E0000u
868
869/**
870 * Peripheral size for regs device on rom_ctrl in top egret.
871 *
872 * This is the size (in bytes) of the peripheral's reserved memory area. All
873 * memory-mapped registers associated with this peripheral should have an
874 * address between #TOP_EGRET_ROM_CTRL_REGS_BASE_ADDR and
875 * `TOP_EGRET_ROM_CTRL_REGS_BASE_ADDR + TOP_EGRET_ROM_CTRL_REGS_SIZE_BYTES`.
876 */
877#define TOP_EGRET_ROM_CTRL_REGS_SIZE_BYTES 0x80u
878
879/**
880 * Peripheral base address for cfg device on rv_core_ibex in top egret.
881 *
882 * This should be used with #mmio_region_from_addr to access the memory-mapped
883 * registers associated with the peripheral (usually via a DIF).
884 */
885#define TOP_EGRET_RV_CORE_IBEX_CFG_BASE_ADDR 0x411F0000u
886
887/**
888 * Peripheral size for cfg device on rv_core_ibex in top egret.
889 *
890 * This is the size (in bytes) of the peripheral's reserved memory area. All
891 * memory-mapped registers associated with this peripheral should have an
892 * address between #TOP_EGRET_RV_CORE_IBEX_CFG_BASE_ADDR and
893 * `TOP_EGRET_RV_CORE_IBEX_CFG_BASE_ADDR + TOP_EGRET_RV_CORE_IBEX_CFG_SIZE_BYTES`.
894 */
895#define TOP_EGRET_RV_CORE_IBEX_CFG_SIZE_BYTES 0x100u
896
897
898/**
899 * Memory base address for ram memory on sram_ctrl_ret_aon in top egret.
900 */
901#define TOP_EGRET_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x40600000u
902
903/**
904 * Memory size for ram memory on sram_ctrl_ret_aon in top egret.
905 */
906#define TOP_EGRET_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000u
907
908/**
909 * Memory base address for mem memory on flash_ctrl in top egret.
910 */
911#define TOP_EGRET_FLASH_CTRL_MEM_BASE_ADDR 0x20000000u
912
913/**
914 * Memory size for mem memory on flash_ctrl in top egret.
915 */
916#define TOP_EGRET_FLASH_CTRL_MEM_SIZE_BYTES 0x100000u
917
918/**
919 * Memory base address for ram memory on sram_ctrl_main in top egret.
920 */
921#define TOP_EGRET_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000u
922
923/**
924 * Memory size for ram memory on sram_ctrl_main in top egret.
925 */
926#define TOP_EGRET_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000u
927
928/**
929 * Memory base address for rom memory on rom_ctrl in top egret.
930 */
931#define TOP_EGRET_ROM_CTRL_ROM_BASE_ADDR 0x8000u
932
933/**
934 * Memory size for rom memory on rom_ctrl in top egret.
935 */
936#define TOP_EGRET_ROM_CTRL_ROM_SIZE_BYTES 0x8000u
937
938
939/**
940 * PLIC Interrupt Source Peripheral.
941 *
942 * Enumeration used to determine which peripheral asserted the corresponding
943 * interrupt.
944 */
946 kTopEgretPlicPeripheralUnknown = 0, /**< Unknown Peripheral */
952 kTopEgretPlicPeripheralSpiDevice = 6, /**< spi_device */
956 kTopEgretPlicPeripheralPattgen = 10, /**< pattgen */
957 kTopEgretPlicPeripheralRvTimer = 11, /**< rv_timer */
958 kTopEgretPlicPeripheralOtpCtrl = 12, /**< otp_ctrl */
959 kTopEgretPlicPeripheralAlertHandler = 13, /**< alert_handler */
960 kTopEgretPlicPeripheralSpiHost0 = 14, /**< spi_host0 */
961 kTopEgretPlicPeripheralSpiHost1 = 15, /**< spi_host1 */
962 kTopEgretPlicPeripheralUsbdev = 16, /**< usbdev */
963 kTopEgretPlicPeripheralPwrmgrAon = 17, /**< pwrmgr_aon */
964 kTopEgretPlicPeripheralSysrstCtrlAon = 18, /**< sysrst_ctrl_aon */
965 kTopEgretPlicPeripheralAdcCtrlAon = 19, /**< adc_ctrl_aon */
966 kTopEgretPlicPeripheralAonTimerAon = 20, /**< aon_timer_aon */
967 kTopEgretPlicPeripheralSensorCtrlAon = 21, /**< sensor_ctrl_aon */
968 kTopEgretPlicPeripheralFlashCtrl = 22, /**< flash_ctrl */
972 kTopEgretPlicPeripheralKeymgr = 26, /**< keymgr */
974 kTopEgretPlicPeripheralEntropySrc = 28, /**< entropy_src */
977 kTopEgretPlicPeripheralLast = 30, /**< \internal Final PLIC peripheral */
979
980/**
981 * PLIC Interrupt Source.
982 *
983 * Enumeration of all PLIC interrupt sources. The interrupt sources belonging to
984 * the same peripheral are guaranteed to be consecutive.
985 */
987 kTopEgretPlicIrqIdNone = 0, /**< No Interrupt */
988 kTopEgretPlicIrqIdUart0TxWatermark = 1, /**< uart0_tx_watermark */
989 kTopEgretPlicIrqIdUart0RxWatermark = 2, /**< uart0_rx_watermark */
990 kTopEgretPlicIrqIdUart0TxDone = 3, /**< uart0_tx_done */
991 kTopEgretPlicIrqIdUart0RxOverflow = 4, /**< uart0_rx_overflow */
992 kTopEgretPlicIrqIdUart0RxFrameErr = 5, /**< uart0_rx_frame_err */
993 kTopEgretPlicIrqIdUart0RxBreakErr = 6, /**< uart0_rx_break_err */
994 kTopEgretPlicIrqIdUart0RxTimeout = 7, /**< uart0_rx_timeout */
995 kTopEgretPlicIrqIdUart0RxParityErr = 8, /**< uart0_rx_parity_err */
996 kTopEgretPlicIrqIdUart0TxEmpty = 9, /**< uart0_tx_empty */
997 kTopEgretPlicIrqIdUart1TxWatermark = 10, /**< uart1_tx_watermark */
998 kTopEgretPlicIrqIdUart1RxWatermark = 11, /**< uart1_rx_watermark */
999 kTopEgretPlicIrqIdUart1TxDone = 12, /**< uart1_tx_done */
1000 kTopEgretPlicIrqIdUart1RxOverflow = 13, /**< uart1_rx_overflow */
1001 kTopEgretPlicIrqIdUart1RxFrameErr = 14, /**< uart1_rx_frame_err */
1002 kTopEgretPlicIrqIdUart1RxBreakErr = 15, /**< uart1_rx_break_err */
1003 kTopEgretPlicIrqIdUart1RxTimeout = 16, /**< uart1_rx_timeout */
1004 kTopEgretPlicIrqIdUart1RxParityErr = 17, /**< uart1_rx_parity_err */
1005 kTopEgretPlicIrqIdUart1TxEmpty = 18, /**< uart1_tx_empty */
1006 kTopEgretPlicIrqIdUart2TxWatermark = 19, /**< uart2_tx_watermark */
1007 kTopEgretPlicIrqIdUart2RxWatermark = 20, /**< uart2_rx_watermark */
1008 kTopEgretPlicIrqIdUart2TxDone = 21, /**< uart2_tx_done */
1009 kTopEgretPlicIrqIdUart2RxOverflow = 22, /**< uart2_rx_overflow */
1010 kTopEgretPlicIrqIdUart2RxFrameErr = 23, /**< uart2_rx_frame_err */
1011 kTopEgretPlicIrqIdUart2RxBreakErr = 24, /**< uart2_rx_break_err */
1012 kTopEgretPlicIrqIdUart2RxTimeout = 25, /**< uart2_rx_timeout */
1013 kTopEgretPlicIrqIdUart2RxParityErr = 26, /**< uart2_rx_parity_err */
1014 kTopEgretPlicIrqIdUart2TxEmpty = 27, /**< uart2_tx_empty */
1015 kTopEgretPlicIrqIdUart3TxWatermark = 28, /**< uart3_tx_watermark */
1016 kTopEgretPlicIrqIdUart3RxWatermark = 29, /**< uart3_rx_watermark */
1017 kTopEgretPlicIrqIdUart3TxDone = 30, /**< uart3_tx_done */
1018 kTopEgretPlicIrqIdUart3RxOverflow = 31, /**< uart3_rx_overflow */
1019 kTopEgretPlicIrqIdUart3RxFrameErr = 32, /**< uart3_rx_frame_err */
1020 kTopEgretPlicIrqIdUart3RxBreakErr = 33, /**< uart3_rx_break_err */
1021 kTopEgretPlicIrqIdUart3RxTimeout = 34, /**< uart3_rx_timeout */
1022 kTopEgretPlicIrqIdUart3RxParityErr = 35, /**< uart3_rx_parity_err */
1023 kTopEgretPlicIrqIdUart3TxEmpty = 36, /**< uart3_tx_empty */
1024 kTopEgretPlicIrqIdGpioGpio0 = 37, /**< gpio_gpio 0 */
1025 kTopEgretPlicIrqIdGpioGpio1 = 38, /**< gpio_gpio 1 */
1026 kTopEgretPlicIrqIdGpioGpio2 = 39, /**< gpio_gpio 2 */
1027 kTopEgretPlicIrqIdGpioGpio3 = 40, /**< gpio_gpio 3 */
1028 kTopEgretPlicIrqIdGpioGpio4 = 41, /**< gpio_gpio 4 */
1029 kTopEgretPlicIrqIdGpioGpio5 = 42, /**< gpio_gpio 5 */
1030 kTopEgretPlicIrqIdGpioGpio6 = 43, /**< gpio_gpio 6 */
1031 kTopEgretPlicIrqIdGpioGpio7 = 44, /**< gpio_gpio 7 */
1032 kTopEgretPlicIrqIdGpioGpio8 = 45, /**< gpio_gpio 8 */
1033 kTopEgretPlicIrqIdGpioGpio9 = 46, /**< gpio_gpio 9 */
1034 kTopEgretPlicIrqIdGpioGpio10 = 47, /**< gpio_gpio 10 */
1035 kTopEgretPlicIrqIdGpioGpio11 = 48, /**< gpio_gpio 11 */
1036 kTopEgretPlicIrqIdGpioGpio12 = 49, /**< gpio_gpio 12 */
1037 kTopEgretPlicIrqIdGpioGpio13 = 50, /**< gpio_gpio 13 */
1038 kTopEgretPlicIrqIdGpioGpio14 = 51, /**< gpio_gpio 14 */
1039 kTopEgretPlicIrqIdGpioGpio15 = 52, /**< gpio_gpio 15 */
1040 kTopEgretPlicIrqIdGpioGpio16 = 53, /**< gpio_gpio 16 */
1041 kTopEgretPlicIrqIdGpioGpio17 = 54, /**< gpio_gpio 17 */
1042 kTopEgretPlicIrqIdGpioGpio18 = 55, /**< gpio_gpio 18 */
1043 kTopEgretPlicIrqIdGpioGpio19 = 56, /**< gpio_gpio 19 */
1044 kTopEgretPlicIrqIdGpioGpio20 = 57, /**< gpio_gpio 20 */
1045 kTopEgretPlicIrqIdGpioGpio21 = 58, /**< gpio_gpio 21 */
1046 kTopEgretPlicIrqIdGpioGpio22 = 59, /**< gpio_gpio 22 */
1047 kTopEgretPlicIrqIdGpioGpio23 = 60, /**< gpio_gpio 23 */
1048 kTopEgretPlicIrqIdGpioGpio24 = 61, /**< gpio_gpio 24 */
1049 kTopEgretPlicIrqIdGpioGpio25 = 62, /**< gpio_gpio 25 */
1050 kTopEgretPlicIrqIdGpioGpio26 = 63, /**< gpio_gpio 26 */
1051 kTopEgretPlicIrqIdGpioGpio27 = 64, /**< gpio_gpio 27 */
1052 kTopEgretPlicIrqIdGpioGpio28 = 65, /**< gpio_gpio 28 */
1053 kTopEgretPlicIrqIdGpioGpio29 = 66, /**< gpio_gpio 29 */
1054 kTopEgretPlicIrqIdGpioGpio30 = 67, /**< gpio_gpio 30 */
1055 kTopEgretPlicIrqIdGpioGpio31 = 68, /**< gpio_gpio 31 */
1056 kTopEgretPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty = 69, /**< spi_device_upload_cmdfifo_not_empty */
1057 kTopEgretPlicIrqIdSpiDeviceUploadPayloadNotEmpty = 70, /**< spi_device_upload_payload_not_empty */
1058 kTopEgretPlicIrqIdSpiDeviceUploadPayloadOverflow = 71, /**< spi_device_upload_payload_overflow */
1059 kTopEgretPlicIrqIdSpiDeviceReadbufWatermark = 72, /**< spi_device_readbuf_watermark */
1060 kTopEgretPlicIrqIdSpiDeviceReadbufFlip = 73, /**< spi_device_readbuf_flip */
1061 kTopEgretPlicIrqIdSpiDeviceTpmHeaderNotEmpty = 74, /**< spi_device_tpm_header_not_empty */
1062 kTopEgretPlicIrqIdSpiDeviceTpmRdfifoCmdEnd = 75, /**< spi_device_tpm_rdfifo_cmd_end */
1063 kTopEgretPlicIrqIdSpiDeviceTpmRdfifoDrop = 76, /**< spi_device_tpm_rdfifo_drop */
1064 kTopEgretPlicIrqIdI2c0FmtThreshold = 77, /**< i2c0_fmt_threshold */
1065 kTopEgretPlicIrqIdI2c0RxThreshold = 78, /**< i2c0_rx_threshold */
1066 kTopEgretPlicIrqIdI2c0AcqThreshold = 79, /**< i2c0_acq_threshold */
1067 kTopEgretPlicIrqIdI2c0RxOverflow = 80, /**< i2c0_rx_overflow */
1068 kTopEgretPlicIrqIdI2c0ControllerHalt = 81, /**< i2c0_controller_halt */
1069 kTopEgretPlicIrqIdI2c0SclInterference = 82, /**< i2c0_scl_interference */
1070 kTopEgretPlicIrqIdI2c0SdaInterference = 83, /**< i2c0_sda_interference */
1071 kTopEgretPlicIrqIdI2c0StretchTimeout = 84, /**< i2c0_stretch_timeout */
1072 kTopEgretPlicIrqIdI2c0SdaUnstable = 85, /**< i2c0_sda_unstable */
1073 kTopEgretPlicIrqIdI2c0CmdComplete = 86, /**< i2c0_cmd_complete */
1074 kTopEgretPlicIrqIdI2c0TxStretch = 87, /**< i2c0_tx_stretch */
1075 kTopEgretPlicIrqIdI2c0TxThreshold = 88, /**< i2c0_tx_threshold */
1076 kTopEgretPlicIrqIdI2c0AcqStretch = 89, /**< i2c0_acq_stretch */
1077 kTopEgretPlicIrqIdI2c0UnexpStop = 90, /**< i2c0_unexp_stop */
1078 kTopEgretPlicIrqIdI2c0HostTimeout = 91, /**< i2c0_host_timeout */
1079 kTopEgretPlicIrqIdI2c1FmtThreshold = 92, /**< i2c1_fmt_threshold */
1080 kTopEgretPlicIrqIdI2c1RxThreshold = 93, /**< i2c1_rx_threshold */
1081 kTopEgretPlicIrqIdI2c1AcqThreshold = 94, /**< i2c1_acq_threshold */
1082 kTopEgretPlicIrqIdI2c1RxOverflow = 95, /**< i2c1_rx_overflow */
1083 kTopEgretPlicIrqIdI2c1ControllerHalt = 96, /**< i2c1_controller_halt */
1084 kTopEgretPlicIrqIdI2c1SclInterference = 97, /**< i2c1_scl_interference */
1085 kTopEgretPlicIrqIdI2c1SdaInterference = 98, /**< i2c1_sda_interference */
1086 kTopEgretPlicIrqIdI2c1StretchTimeout = 99, /**< i2c1_stretch_timeout */
1087 kTopEgretPlicIrqIdI2c1SdaUnstable = 100, /**< i2c1_sda_unstable */
1088 kTopEgretPlicIrqIdI2c1CmdComplete = 101, /**< i2c1_cmd_complete */
1089 kTopEgretPlicIrqIdI2c1TxStretch = 102, /**< i2c1_tx_stretch */
1090 kTopEgretPlicIrqIdI2c1TxThreshold = 103, /**< i2c1_tx_threshold */
1091 kTopEgretPlicIrqIdI2c1AcqStretch = 104, /**< i2c1_acq_stretch */
1092 kTopEgretPlicIrqIdI2c1UnexpStop = 105, /**< i2c1_unexp_stop */
1093 kTopEgretPlicIrqIdI2c1HostTimeout = 106, /**< i2c1_host_timeout */
1094 kTopEgretPlicIrqIdI2c2FmtThreshold = 107, /**< i2c2_fmt_threshold */
1095 kTopEgretPlicIrqIdI2c2RxThreshold = 108, /**< i2c2_rx_threshold */
1096 kTopEgretPlicIrqIdI2c2AcqThreshold = 109, /**< i2c2_acq_threshold */
1097 kTopEgretPlicIrqIdI2c2RxOverflow = 110, /**< i2c2_rx_overflow */
1098 kTopEgretPlicIrqIdI2c2ControllerHalt = 111, /**< i2c2_controller_halt */
1099 kTopEgretPlicIrqIdI2c2SclInterference = 112, /**< i2c2_scl_interference */
1100 kTopEgretPlicIrqIdI2c2SdaInterference = 113, /**< i2c2_sda_interference */
1101 kTopEgretPlicIrqIdI2c2StretchTimeout = 114, /**< i2c2_stretch_timeout */
1102 kTopEgretPlicIrqIdI2c2SdaUnstable = 115, /**< i2c2_sda_unstable */
1103 kTopEgretPlicIrqIdI2c2CmdComplete = 116, /**< i2c2_cmd_complete */
1104 kTopEgretPlicIrqIdI2c2TxStretch = 117, /**< i2c2_tx_stretch */
1105 kTopEgretPlicIrqIdI2c2TxThreshold = 118, /**< i2c2_tx_threshold */
1106 kTopEgretPlicIrqIdI2c2AcqStretch = 119, /**< i2c2_acq_stretch */
1107 kTopEgretPlicIrqIdI2c2UnexpStop = 120, /**< i2c2_unexp_stop */
1108 kTopEgretPlicIrqIdI2c2HostTimeout = 121, /**< i2c2_host_timeout */
1109 kTopEgretPlicIrqIdPattgenDoneCh0 = 122, /**< pattgen_done_ch0 */
1110 kTopEgretPlicIrqIdPattgenDoneCh1 = 123, /**< pattgen_done_ch1 */
1111 kTopEgretPlicIrqIdRvTimerTimerExpiredHart0Timer0 = 124, /**< rv_timer_timer_expired_hart0_timer0 */
1112 kTopEgretPlicIrqIdOtpCtrlOtpOperationDone = 125, /**< otp_ctrl_otp_operation_done */
1113 kTopEgretPlicIrqIdOtpCtrlOtpError = 126, /**< otp_ctrl_otp_error */
1114 kTopEgretPlicIrqIdAlertHandlerClassa = 127, /**< alert_handler_classa */
1115 kTopEgretPlicIrqIdAlertHandlerClassb = 128, /**< alert_handler_classb */
1116 kTopEgretPlicIrqIdAlertHandlerClassc = 129, /**< alert_handler_classc */
1117 kTopEgretPlicIrqIdAlertHandlerClassd = 130, /**< alert_handler_classd */
1118 kTopEgretPlicIrqIdSpiHost0Error = 131, /**< spi_host0_error */
1119 kTopEgretPlicIrqIdSpiHost0SpiEvent = 132, /**< spi_host0_spi_event */
1120 kTopEgretPlicIrqIdSpiHost1Error = 133, /**< spi_host1_error */
1121 kTopEgretPlicIrqIdSpiHost1SpiEvent = 134, /**< spi_host1_spi_event */
1122 kTopEgretPlicIrqIdUsbdevPktReceived = 135, /**< usbdev_pkt_received */
1123 kTopEgretPlicIrqIdUsbdevPktSent = 136, /**< usbdev_pkt_sent */
1124 kTopEgretPlicIrqIdUsbdevDisconnected = 137, /**< usbdev_disconnected */
1125 kTopEgretPlicIrqIdUsbdevHostLost = 138, /**< usbdev_host_lost */
1126 kTopEgretPlicIrqIdUsbdevLinkReset = 139, /**< usbdev_link_reset */
1127 kTopEgretPlicIrqIdUsbdevLinkSuspend = 140, /**< usbdev_link_suspend */
1128 kTopEgretPlicIrqIdUsbdevLinkResume = 141, /**< usbdev_link_resume */
1129 kTopEgretPlicIrqIdUsbdevAvOutEmpty = 142, /**< usbdev_av_out_empty */
1130 kTopEgretPlicIrqIdUsbdevRxFull = 143, /**< usbdev_rx_full */
1131 kTopEgretPlicIrqIdUsbdevAvOverflow = 144, /**< usbdev_av_overflow */
1132 kTopEgretPlicIrqIdUsbdevLinkInErr = 145, /**< usbdev_link_in_err */
1133 kTopEgretPlicIrqIdUsbdevRxCrcErr = 146, /**< usbdev_rx_crc_err */
1134 kTopEgretPlicIrqIdUsbdevRxPidErr = 147, /**< usbdev_rx_pid_err */
1135 kTopEgretPlicIrqIdUsbdevRxBitstuffErr = 148, /**< usbdev_rx_bitstuff_err */
1136 kTopEgretPlicIrqIdUsbdevFrame = 149, /**< usbdev_frame */
1137 kTopEgretPlicIrqIdUsbdevPowered = 150, /**< usbdev_powered */
1138 kTopEgretPlicIrqIdUsbdevLinkOutErr = 151, /**< usbdev_link_out_err */
1139 kTopEgretPlicIrqIdUsbdevAvSetupEmpty = 152, /**< usbdev_av_setup_empty */
1140 kTopEgretPlicIrqIdPwrmgrAonWakeup = 153, /**< pwrmgr_aon_wakeup */
1141 kTopEgretPlicIrqIdSysrstCtrlAonEventDetected = 154, /**< sysrst_ctrl_aon_event_detected */
1142 kTopEgretPlicIrqIdAdcCtrlAonMatchPending = 155, /**< adc_ctrl_aon_match_pending */
1143 kTopEgretPlicIrqIdAonTimerAonWkupTimerExpired = 156, /**< aon_timer_aon_wkup_timer_expired */
1144 kTopEgretPlicIrqIdAonTimerAonWdogTimerBark = 157, /**< aon_timer_aon_wdog_timer_bark */
1145 kTopEgretPlicIrqIdSensorCtrlAonIoStatusChange = 158, /**< sensor_ctrl_aon_io_status_change */
1146 kTopEgretPlicIrqIdSensorCtrlAonInitStatusChange = 159, /**< sensor_ctrl_aon_init_status_change */
1147 kTopEgretPlicIrqIdFlashCtrlProgEmpty = 160, /**< flash_ctrl_prog_empty */
1148 kTopEgretPlicIrqIdFlashCtrlProgLvl = 161, /**< flash_ctrl_prog_lvl */
1149 kTopEgretPlicIrqIdFlashCtrlRdFull = 162, /**< flash_ctrl_rd_full */
1150 kTopEgretPlicIrqIdFlashCtrlRdLvl = 163, /**< flash_ctrl_rd_lvl */
1151 kTopEgretPlicIrqIdFlashCtrlOpDone = 164, /**< flash_ctrl_op_done */
1152 kTopEgretPlicIrqIdFlashCtrlCorrErr = 165, /**< flash_ctrl_corr_err */
1153 kTopEgretPlicIrqIdAccDone = 166, /**< acc_done */
1154 kTopEgretPlicIrqIdHmacHmacDone = 167, /**< hmac_hmac_done */
1155 kTopEgretPlicIrqIdHmacFifoEmpty = 168, /**< hmac_fifo_empty */
1156 kTopEgretPlicIrqIdHmacHmacErr = 169, /**< hmac_hmac_err */
1157 kTopEgretPlicIrqIdKmacKmacDone = 170, /**< kmac_kmac_done */
1158 kTopEgretPlicIrqIdKmacFifoEmpty = 171, /**< kmac_fifo_empty */
1159 kTopEgretPlicIrqIdKmacKmacErr = 172, /**< kmac_kmac_err */
1160 kTopEgretPlicIrqIdKeymgrOpDone = 173, /**< keymgr_op_done */
1161 kTopEgretPlicIrqIdCsrngCsCmdReqDone = 174, /**< csrng_cs_cmd_req_done */
1162 kTopEgretPlicIrqIdCsrngCsEntropyReq = 175, /**< csrng_cs_entropy_req */
1163 kTopEgretPlicIrqIdCsrngCsHwInstExc = 176, /**< csrng_cs_hw_inst_exc */
1164 kTopEgretPlicIrqIdCsrngCsFatalErr = 177, /**< csrng_cs_fatal_err */
1165 kTopEgretPlicIrqIdEntropySrcEsEntropyValid = 178, /**< entropy_src_es_entropy_valid */
1166 kTopEgretPlicIrqIdEntropySrcEsHealthTestFailed = 179, /**< entropy_src_es_health_test_failed */
1167 kTopEgretPlicIrqIdEntropySrcEsObserveFifoReady = 180, /**< entropy_src_es_observe_fifo_ready */
1168 kTopEgretPlicIrqIdEntropySrcEsFatalErr = 181, /**< entropy_src_es_fatal_err */
1169 kTopEgretPlicIrqIdEdn0EdnCmdReqDone = 182, /**< edn0_edn_cmd_req_done */
1170 kTopEgretPlicIrqIdEdn0EdnFatalErr = 183, /**< edn0_edn_fatal_err */
1171 kTopEgretPlicIrqIdEdn1EdnCmdReqDone = 184, /**< edn1_edn_cmd_req_done */
1172 kTopEgretPlicIrqIdEdn1EdnFatalErr = 185, /**< edn1_edn_fatal_err */
1173 kTopEgretPlicIrqIdLast = 185, /**< \internal The Last Valid Interrupt ID. */
1175
1176/**
1177 * PLIC Interrupt Source to Peripheral Map
1178 *
1179 * This array is a mapping from `top_egret_plic_irq_id_t` to
1180 * `top_egret_plic_peripheral_t`.
1181 */
1182extern const top_egret_plic_peripheral_t
1183 top_egret_plic_interrupt_for_peripheral[186];
1184
1185/**
1186 * PLIC Interrupt Target.
1187 *
1188 * Enumeration used to determine which set of IE, CC, threshold registers to
1189 * access for a given interrupt target.
1190 */
1192 kTopEgretPlicTargetIbex0 = 0, /**< Ibex Core 0 */
1193 kTopEgretPlicTargetLast = 0, /**< \internal Final PLIC target */
1195
1196
1197/**
1198 * Alert Handler Source Peripheral.
1199 *
1200 * Enumeration used to determine which peripheral asserted the corresponding
1201 * alert.
1202 */
1204 kTopEgretAlertPeripheralExternal = 0, /**< External Peripheral */
1215 kTopEgretAlertPeripheralRvTimer = 11, /**< rv_timer */
1216 kTopEgretAlertPeripheralOtpCtrl = 12, /**< otp_ctrl */
1218 kTopEgretAlertPeripheralSpiHost0 = 14, /**< spi_host0 */
1219 kTopEgretAlertPeripheralSpiHost1 = 15, /**< spi_host1 */
1221 kTopEgretAlertPeripheralPwrmgrAon = 17, /**< pwrmgr_aon */
1222 kTopEgretAlertPeripheralRstmgrAon = 18, /**< rstmgr_aon */
1223 kTopEgretAlertPeripheralClkmgrAon = 19, /**< clkmgr_aon */
1224 kTopEgretAlertPeripheralSysrstCtrlAon = 20, /**< sysrst_ctrl_aon */
1225 kTopEgretAlertPeripheralAdcCtrlAon = 21, /**< adc_ctrl_aon */
1227 kTopEgretAlertPeripheralPinmuxAon = 23, /**< pinmux_aon */
1228 kTopEgretAlertPeripheralAonTimerAon = 24, /**< aon_timer_aon */
1229 kTopEgretAlertPeripheralSensorCtrlAon = 25, /**< sensor_ctrl_aon */
1230 kTopEgretAlertPeripheralSramCtrlRetAon = 26, /**< sram_ctrl_ret_aon */
1231 kTopEgretAlertPeripheralFlashCtrl = 27, /**< flash_ctrl */
1240 kTopEgretAlertPeripheralEntropySrc = 36, /**< entropy_src */
1243 kTopEgretAlertPeripheralSramCtrlMain = 39, /**< sram_ctrl_main */
1244 kTopEgretAlertPeripheralRomCtrl = 40, /**< rom_ctrl */
1245 kTopEgretAlertPeripheralRvCoreIbex = 41, /**< rv_core_ibex */
1246 kTopEgretAlertPeripheralLast = 41, /**< \internal Final Alert peripheral */
1248
1249/**
1250 * Alert Handler Alert Source.
1251 *
1252 * Enumeration of all Alert Handler Alert Sources. The alert sources belonging to
1253 * the same peripheral are guaranteed to be consecutive.
1254 */
1256 kTopEgretAlertIdUart0FatalFault = 0, /**< uart0_fatal_fault */
1257 kTopEgretAlertIdUart1FatalFault = 1, /**< uart1_fatal_fault */
1258 kTopEgretAlertIdUart2FatalFault = 2, /**< uart2_fatal_fault */
1259 kTopEgretAlertIdUart3FatalFault = 3, /**< uart3_fatal_fault */
1260 kTopEgretAlertIdGpioFatalFault = 4, /**< gpio_fatal_fault */
1261 kTopEgretAlertIdSpiDeviceFatalFault = 5, /**< spi_device_fatal_fault */
1262 kTopEgretAlertIdI2c0FatalFault = 6, /**< i2c0_fatal_fault */
1263 kTopEgretAlertIdI2c1FatalFault = 7, /**< i2c1_fatal_fault */
1264 kTopEgretAlertIdI2c2FatalFault = 8, /**< i2c2_fatal_fault */
1265 kTopEgretAlertIdPattgenFatalFault = 9, /**< pattgen_fatal_fault */
1266 kTopEgretAlertIdRvTimerFatalFault = 10, /**< rv_timer_fatal_fault */
1267 kTopEgretAlertIdOtpCtrlFatalMacroError = 11, /**< otp_ctrl_fatal_macro_error */
1268 kTopEgretAlertIdOtpCtrlFatalCheckError = 12, /**< otp_ctrl_fatal_check_error */
1269 kTopEgretAlertIdOtpCtrlFatalBusIntegError = 13, /**< otp_ctrl_fatal_bus_integ_error */
1270 kTopEgretAlertIdOtpCtrlFatalPrimOtpAlert = 14, /**< otp_ctrl_fatal_prim_otp_alert */
1271 kTopEgretAlertIdOtpCtrlRecovPrimOtpAlert = 15, /**< otp_ctrl_recov_prim_otp_alert */
1272 kTopEgretAlertIdLcCtrlFatalProgError = 16, /**< lc_ctrl_fatal_prog_error */
1273 kTopEgretAlertIdLcCtrlFatalStateError = 17, /**< lc_ctrl_fatal_state_error */
1274 kTopEgretAlertIdLcCtrlFatalBusIntegError = 18, /**< lc_ctrl_fatal_bus_integ_error */
1275 kTopEgretAlertIdSpiHost0FatalFault = 19, /**< spi_host0_fatal_fault */
1276 kTopEgretAlertIdSpiHost1FatalFault = 20, /**< spi_host1_fatal_fault */
1277 kTopEgretAlertIdUsbdevFatalFault = 21, /**< usbdev_fatal_fault */
1278 kTopEgretAlertIdPwrmgrAonFatalFault = 22, /**< pwrmgr_aon_fatal_fault */
1279 kTopEgretAlertIdRstmgrAonFatalFault = 23, /**< rstmgr_aon_fatal_fault */
1280 kTopEgretAlertIdRstmgrAonFatalCnstyFault = 24, /**< rstmgr_aon_fatal_cnsty_fault */
1281 kTopEgretAlertIdClkmgrAonRecovFault = 25, /**< clkmgr_aon_recov_fault */
1282 kTopEgretAlertIdClkmgrAonFatalFault = 26, /**< clkmgr_aon_fatal_fault */
1283 kTopEgretAlertIdSysrstCtrlAonFatalFault = 27, /**< sysrst_ctrl_aon_fatal_fault */
1284 kTopEgretAlertIdAdcCtrlAonFatalFault = 28, /**< adc_ctrl_aon_fatal_fault */
1285 kTopEgretAlertIdPwmAonFatalFault = 29, /**< pwm_aon_fatal_fault */
1286 kTopEgretAlertIdPinmuxAonFatalFault = 30, /**< pinmux_aon_fatal_fault */
1287 kTopEgretAlertIdAonTimerAonFatalFault = 31, /**< aon_timer_aon_fatal_fault */
1288 kTopEgretAlertIdSensorCtrlAonRecovAlert = 32, /**< sensor_ctrl_aon_recov_alert */
1289 kTopEgretAlertIdSensorCtrlAonFatalAlert = 33, /**< sensor_ctrl_aon_fatal_alert */
1290 kTopEgretAlertIdSramCtrlRetAonFatalError = 34, /**< sram_ctrl_ret_aon_fatal_error */
1291 kTopEgretAlertIdFlashCtrlRecovErr = 35, /**< flash_ctrl_recov_err */
1292 kTopEgretAlertIdFlashCtrlFatalStdErr = 36, /**< flash_ctrl_fatal_std_err */
1293 kTopEgretAlertIdFlashCtrlFatalErr = 37, /**< flash_ctrl_fatal_err */
1294 kTopEgretAlertIdFlashCtrlFatalPrimFlashAlert = 38, /**< flash_ctrl_fatal_prim_flash_alert */
1295 kTopEgretAlertIdFlashCtrlRecovPrimFlashAlert = 39, /**< flash_ctrl_recov_prim_flash_alert */
1296 kTopEgretAlertIdRvDmFatalFault = 40, /**< rv_dm_fatal_fault */
1297 kTopEgretAlertIdRvPlicFatalFault = 41, /**< rv_plic_fatal_fault */
1298 kTopEgretAlertIdAccFatal = 42, /**< acc_fatal */
1299 kTopEgretAlertIdAccRecov = 43, /**< acc_recov */
1300 kTopEgretAlertIdAesRecovCtrlUpdateErr = 44, /**< aes_recov_ctrl_update_err */
1301 kTopEgretAlertIdAesFatalFault = 45, /**< aes_fatal_fault */
1302 kTopEgretAlertIdHmacFatalFault = 46, /**< hmac_fatal_fault */
1303 kTopEgretAlertIdKmacRecovOperationErr = 47, /**< kmac_recov_operation_err */
1304 kTopEgretAlertIdKmacFatalFaultErr = 48, /**< kmac_fatal_fault_err */
1305 kTopEgretAlertIdKeymgrRecovOperationErr = 49, /**< keymgr_recov_operation_err */
1306 kTopEgretAlertIdKeymgrFatalFaultErr = 50, /**< keymgr_fatal_fault_err */
1307 kTopEgretAlertIdCsrngRecovAlert = 51, /**< csrng_recov_alert */
1308 kTopEgretAlertIdCsrngFatalAlert = 52, /**< csrng_fatal_alert */
1309 kTopEgretAlertIdEntropySrcRecovAlert = 53, /**< entropy_src_recov_alert */
1310 kTopEgretAlertIdEntropySrcFatalAlert = 54, /**< entropy_src_fatal_alert */
1311 kTopEgretAlertIdEdn0RecovAlert = 55, /**< edn0_recov_alert */
1312 kTopEgretAlertIdEdn0FatalAlert = 56, /**< edn0_fatal_alert */
1313 kTopEgretAlertIdEdn1RecovAlert = 57, /**< edn1_recov_alert */
1314 kTopEgretAlertIdEdn1FatalAlert = 58, /**< edn1_fatal_alert */
1315 kTopEgretAlertIdSramCtrlMainFatalError = 59, /**< sram_ctrl_main_fatal_error */
1316 kTopEgretAlertIdRomCtrlFatal = 60, /**< rom_ctrl_fatal */
1317 kTopEgretAlertIdRvCoreIbexFatalSwErr = 61, /**< rv_core_ibex_fatal_sw_err */
1318 kTopEgretAlertIdRvCoreIbexRecovSwErr = 62, /**< rv_core_ibex_recov_sw_err */
1319 kTopEgretAlertIdRvCoreIbexFatalHwErr = 63, /**< rv_core_ibex_fatal_hw_err */
1320 kTopEgretAlertIdRvCoreIbexRecovHwErr = 64, /**< rv_core_ibex_recov_hw_err */
1321 kTopEgretAlertIdLast = 64, /**< \internal The Last Valid Alert ID. */
1323
1324/**
1325 * Alert Handler Alert Source to Peripheral Map
1326 *
1327 * This array is a mapping from `top_egret_alert_id_t` to
1328 * `top_egret_alert_peripheral_t`.
1329 */
1331 top_egret_alert_for_peripheral[65];
1332
1333#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
1334
1335// PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1}
1336// 0 and 1 are tied to value 0 and 1
1337#define NUM_MIO_PADS 47
1338#define NUM_DIO_PADS 16
1339
1340#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3
1341
1342/**
1343 * Pinmux Peripheral Input.
1344 */
1346 kTopEgretPinmuxPeripheralInGpioGpio0 = 0, /**< Peripheral Input 0 */
1347 kTopEgretPinmuxPeripheralInGpioGpio1 = 1, /**< Peripheral Input 1 */
1348 kTopEgretPinmuxPeripheralInGpioGpio2 = 2, /**< Peripheral Input 2 */
1349 kTopEgretPinmuxPeripheralInGpioGpio3 = 3, /**< Peripheral Input 3 */
1350 kTopEgretPinmuxPeripheralInGpioGpio4 = 4, /**< Peripheral Input 4 */
1351 kTopEgretPinmuxPeripheralInGpioGpio5 = 5, /**< Peripheral Input 5 */
1352 kTopEgretPinmuxPeripheralInGpioGpio6 = 6, /**< Peripheral Input 6 */
1353 kTopEgretPinmuxPeripheralInGpioGpio7 = 7, /**< Peripheral Input 7 */
1354 kTopEgretPinmuxPeripheralInGpioGpio8 = 8, /**< Peripheral Input 8 */
1355 kTopEgretPinmuxPeripheralInGpioGpio9 = 9, /**< Peripheral Input 9 */
1356 kTopEgretPinmuxPeripheralInGpioGpio10 = 10, /**< Peripheral Input 10 */
1357 kTopEgretPinmuxPeripheralInGpioGpio11 = 11, /**< Peripheral Input 11 */
1358 kTopEgretPinmuxPeripheralInGpioGpio12 = 12, /**< Peripheral Input 12 */
1359 kTopEgretPinmuxPeripheralInGpioGpio13 = 13, /**< Peripheral Input 13 */
1360 kTopEgretPinmuxPeripheralInGpioGpio14 = 14, /**< Peripheral Input 14 */
1361 kTopEgretPinmuxPeripheralInGpioGpio15 = 15, /**< Peripheral Input 15 */
1362 kTopEgretPinmuxPeripheralInGpioGpio16 = 16, /**< Peripheral Input 16 */
1363 kTopEgretPinmuxPeripheralInGpioGpio17 = 17, /**< Peripheral Input 17 */
1364 kTopEgretPinmuxPeripheralInGpioGpio18 = 18, /**< Peripheral Input 18 */
1365 kTopEgretPinmuxPeripheralInGpioGpio19 = 19, /**< Peripheral Input 19 */
1366 kTopEgretPinmuxPeripheralInGpioGpio20 = 20, /**< Peripheral Input 20 */
1367 kTopEgretPinmuxPeripheralInGpioGpio21 = 21, /**< Peripheral Input 21 */
1368 kTopEgretPinmuxPeripheralInGpioGpio22 = 22, /**< Peripheral Input 22 */
1369 kTopEgretPinmuxPeripheralInGpioGpio23 = 23, /**< Peripheral Input 23 */
1370 kTopEgretPinmuxPeripheralInGpioGpio24 = 24, /**< Peripheral Input 24 */
1371 kTopEgretPinmuxPeripheralInGpioGpio25 = 25, /**< Peripheral Input 25 */
1372 kTopEgretPinmuxPeripheralInGpioGpio26 = 26, /**< Peripheral Input 26 */
1373 kTopEgretPinmuxPeripheralInGpioGpio27 = 27, /**< Peripheral Input 27 */
1374 kTopEgretPinmuxPeripheralInGpioGpio28 = 28, /**< Peripheral Input 28 */
1375 kTopEgretPinmuxPeripheralInGpioGpio29 = 29, /**< Peripheral Input 29 */
1376 kTopEgretPinmuxPeripheralInGpioGpio30 = 30, /**< Peripheral Input 30 */
1377 kTopEgretPinmuxPeripheralInGpioGpio31 = 31, /**< Peripheral Input 31 */
1378 kTopEgretPinmuxPeripheralInI2c0Sda = 32, /**< Peripheral Input 32 */
1379 kTopEgretPinmuxPeripheralInI2c0Scl = 33, /**< Peripheral Input 33 */
1380 kTopEgretPinmuxPeripheralInI2c1Sda = 34, /**< Peripheral Input 34 */
1381 kTopEgretPinmuxPeripheralInI2c1Scl = 35, /**< Peripheral Input 35 */
1382 kTopEgretPinmuxPeripheralInI2c2Sda = 36, /**< Peripheral Input 36 */
1383 kTopEgretPinmuxPeripheralInI2c2Scl = 37, /**< Peripheral Input 37 */
1384 kTopEgretPinmuxPeripheralInSpiHost1Sd0 = 38, /**< Peripheral Input 38 */
1385 kTopEgretPinmuxPeripheralInSpiHost1Sd1 = 39, /**< Peripheral Input 39 */
1386 kTopEgretPinmuxPeripheralInSpiHost1Sd2 = 40, /**< Peripheral Input 40 */
1387 kTopEgretPinmuxPeripheralInSpiHost1Sd3 = 41, /**< Peripheral Input 41 */
1388 kTopEgretPinmuxPeripheralInUart0Rx = 42, /**< Peripheral Input 42 */
1389 kTopEgretPinmuxPeripheralInUart1Rx = 43, /**< Peripheral Input 43 */
1390 kTopEgretPinmuxPeripheralInUart2Rx = 44, /**< Peripheral Input 44 */
1391 kTopEgretPinmuxPeripheralInUart3Rx = 45, /**< Peripheral Input 45 */
1392 kTopEgretPinmuxPeripheralInSpiDeviceTpmCsb = 46, /**< Peripheral Input 46 */
1393 kTopEgretPinmuxPeripheralInFlashMacroWrapperTck = 47, /**< Peripheral Input 47 */
1394 kTopEgretPinmuxPeripheralInFlashMacroWrapperTms = 48, /**< Peripheral Input 48 */
1395 kTopEgretPinmuxPeripheralInFlashMacroWrapperTdi = 49, /**< Peripheral Input 49 */
1397 kTopEgretPinmuxPeripheralInSysrstCtrlAonKey0In = 51, /**< Peripheral Input 51 */
1398 kTopEgretPinmuxPeripheralInSysrstCtrlAonKey1In = 52, /**< Peripheral Input 52 */
1399 kTopEgretPinmuxPeripheralInSysrstCtrlAonKey2In = 53, /**< Peripheral Input 53 */
1400 kTopEgretPinmuxPeripheralInSysrstCtrlAonPwrbIn = 54, /**< Peripheral Input 54 */
1401 kTopEgretPinmuxPeripheralInSysrstCtrlAonLidOpen = 55, /**< Peripheral Input 55 */
1402 kTopEgretPinmuxPeripheralInUsbdevSense = 56, /**< Peripheral Input 56 */
1403 kTopEgretPinmuxPeripheralInLast = 56, /**< \internal Last valid peripheral input */
1405
1406/**
1407 * Pinmux MIO Input Selector.
1408 */
1410 kTopEgretPinmuxInselConstantZero = 0, /**< Tie constantly to zero */
1411 kTopEgretPinmuxInselConstantOne = 1, /**< Tie constantly to one */
1412 kTopEgretPinmuxInselIoa0 = 2, /**< MIO Pad 0 */
1413 kTopEgretPinmuxInselIoa1 = 3, /**< MIO Pad 1 */
1414 kTopEgretPinmuxInselIoa2 = 4, /**< MIO Pad 2 */
1415 kTopEgretPinmuxInselIoa3 = 5, /**< MIO Pad 3 */
1416 kTopEgretPinmuxInselIoa4 = 6, /**< MIO Pad 4 */
1417 kTopEgretPinmuxInselIoa5 = 7, /**< MIO Pad 5 */
1418 kTopEgretPinmuxInselIoa6 = 8, /**< MIO Pad 6 */
1419 kTopEgretPinmuxInselIoa7 = 9, /**< MIO Pad 7 */
1420 kTopEgretPinmuxInselIoa8 = 10, /**< MIO Pad 8 */
1421 kTopEgretPinmuxInselIob0 = 11, /**< MIO Pad 9 */
1422 kTopEgretPinmuxInselIob1 = 12, /**< MIO Pad 10 */
1423 kTopEgretPinmuxInselIob2 = 13, /**< MIO Pad 11 */
1424 kTopEgretPinmuxInselIob3 = 14, /**< MIO Pad 12 */
1425 kTopEgretPinmuxInselIob4 = 15, /**< MIO Pad 13 */
1426 kTopEgretPinmuxInselIob5 = 16, /**< MIO Pad 14 */
1427 kTopEgretPinmuxInselIob6 = 17, /**< MIO Pad 15 */
1428 kTopEgretPinmuxInselIob7 = 18, /**< MIO Pad 16 */
1429 kTopEgretPinmuxInselIob8 = 19, /**< MIO Pad 17 */
1430 kTopEgretPinmuxInselIob9 = 20, /**< MIO Pad 18 */
1431 kTopEgretPinmuxInselIob10 = 21, /**< MIO Pad 19 */
1432 kTopEgretPinmuxInselIob11 = 22, /**< MIO Pad 20 */
1433 kTopEgretPinmuxInselIob12 = 23, /**< MIO Pad 21 */
1434 kTopEgretPinmuxInselIoc0 = 24, /**< MIO Pad 22 */
1435 kTopEgretPinmuxInselIoc1 = 25, /**< MIO Pad 23 */
1436 kTopEgretPinmuxInselIoc2 = 26, /**< MIO Pad 24 */
1437 kTopEgretPinmuxInselIoc3 = 27, /**< MIO Pad 25 */
1438 kTopEgretPinmuxInselIoc4 = 28, /**< MIO Pad 26 */
1439 kTopEgretPinmuxInselIoc5 = 29, /**< MIO Pad 27 */
1440 kTopEgretPinmuxInselIoc6 = 30, /**< MIO Pad 28 */
1441 kTopEgretPinmuxInselIoc7 = 31, /**< MIO Pad 29 */
1442 kTopEgretPinmuxInselIoc8 = 32, /**< MIO Pad 30 */
1443 kTopEgretPinmuxInselIoc9 = 33, /**< MIO Pad 31 */
1444 kTopEgretPinmuxInselIoc10 = 34, /**< MIO Pad 32 */
1445 kTopEgretPinmuxInselIoc11 = 35, /**< MIO Pad 33 */
1446 kTopEgretPinmuxInselIoc12 = 36, /**< MIO Pad 34 */
1447 kTopEgretPinmuxInselIor0 = 37, /**< MIO Pad 35 */
1448 kTopEgretPinmuxInselIor1 = 38, /**< MIO Pad 36 */
1449 kTopEgretPinmuxInselIor2 = 39, /**< MIO Pad 37 */
1450 kTopEgretPinmuxInselIor3 = 40, /**< MIO Pad 38 */
1451 kTopEgretPinmuxInselIor4 = 41, /**< MIO Pad 39 */
1452 kTopEgretPinmuxInselIor5 = 42, /**< MIO Pad 40 */
1453 kTopEgretPinmuxInselIor6 = 43, /**< MIO Pad 41 */
1454 kTopEgretPinmuxInselIor7 = 44, /**< MIO Pad 42 */
1455 kTopEgretPinmuxInselIor10 = 45, /**< MIO Pad 43 */
1456 kTopEgretPinmuxInselIor11 = 46, /**< MIO Pad 44 */
1457 kTopEgretPinmuxInselIor12 = 47, /**< MIO Pad 45 */
1458 kTopEgretPinmuxInselIor13 = 48, /**< MIO Pad 46 */
1459 kTopEgretPinmuxInselLast = 48, /**< \internal Last valid insel value */
1461
1462/**
1463 * Pinmux MIO Output.
1464 */
1466 kTopEgretPinmuxMioOutIoa0 = 0, /**< MIO Pad 0 */
1467 kTopEgretPinmuxMioOutIoa1 = 1, /**< MIO Pad 1 */
1468 kTopEgretPinmuxMioOutIoa2 = 2, /**< MIO Pad 2 */
1469 kTopEgretPinmuxMioOutIoa3 = 3, /**< MIO Pad 3 */
1470 kTopEgretPinmuxMioOutIoa4 = 4, /**< MIO Pad 4 */
1471 kTopEgretPinmuxMioOutIoa5 = 5, /**< MIO Pad 5 */
1472 kTopEgretPinmuxMioOutIoa6 = 6, /**< MIO Pad 6 */
1473 kTopEgretPinmuxMioOutIoa7 = 7, /**< MIO Pad 7 */
1474 kTopEgretPinmuxMioOutIoa8 = 8, /**< MIO Pad 8 */
1475 kTopEgretPinmuxMioOutIob0 = 9, /**< MIO Pad 9 */
1476 kTopEgretPinmuxMioOutIob1 = 10, /**< MIO Pad 10 */
1477 kTopEgretPinmuxMioOutIob2 = 11, /**< MIO Pad 11 */
1478 kTopEgretPinmuxMioOutIob3 = 12, /**< MIO Pad 12 */
1479 kTopEgretPinmuxMioOutIob4 = 13, /**< MIO Pad 13 */
1480 kTopEgretPinmuxMioOutIob5 = 14, /**< MIO Pad 14 */
1481 kTopEgretPinmuxMioOutIob6 = 15, /**< MIO Pad 15 */
1482 kTopEgretPinmuxMioOutIob7 = 16, /**< MIO Pad 16 */
1483 kTopEgretPinmuxMioOutIob8 = 17, /**< MIO Pad 17 */
1484 kTopEgretPinmuxMioOutIob9 = 18, /**< MIO Pad 18 */
1485 kTopEgretPinmuxMioOutIob10 = 19, /**< MIO Pad 19 */
1486 kTopEgretPinmuxMioOutIob11 = 20, /**< MIO Pad 20 */
1487 kTopEgretPinmuxMioOutIob12 = 21, /**< MIO Pad 21 */
1488 kTopEgretPinmuxMioOutIoc0 = 22, /**< MIO Pad 22 */
1489 kTopEgretPinmuxMioOutIoc1 = 23, /**< MIO Pad 23 */
1490 kTopEgretPinmuxMioOutIoc2 = 24, /**< MIO Pad 24 */
1491 kTopEgretPinmuxMioOutIoc3 = 25, /**< MIO Pad 25 */
1492 kTopEgretPinmuxMioOutIoc4 = 26, /**< MIO Pad 26 */
1493 kTopEgretPinmuxMioOutIoc5 = 27, /**< MIO Pad 27 */
1494 kTopEgretPinmuxMioOutIoc6 = 28, /**< MIO Pad 28 */
1495 kTopEgretPinmuxMioOutIoc7 = 29, /**< MIO Pad 29 */
1496 kTopEgretPinmuxMioOutIoc8 = 30, /**< MIO Pad 30 */
1497 kTopEgretPinmuxMioOutIoc9 = 31, /**< MIO Pad 31 */
1498 kTopEgretPinmuxMioOutIoc10 = 32, /**< MIO Pad 32 */
1499 kTopEgretPinmuxMioOutIoc11 = 33, /**< MIO Pad 33 */
1500 kTopEgretPinmuxMioOutIoc12 = 34, /**< MIO Pad 34 */
1501 kTopEgretPinmuxMioOutIor0 = 35, /**< MIO Pad 35 */
1502 kTopEgretPinmuxMioOutIor1 = 36, /**< MIO Pad 36 */
1503 kTopEgretPinmuxMioOutIor2 = 37, /**< MIO Pad 37 */
1504 kTopEgretPinmuxMioOutIor3 = 38, /**< MIO Pad 38 */
1505 kTopEgretPinmuxMioOutIor4 = 39, /**< MIO Pad 39 */
1506 kTopEgretPinmuxMioOutIor5 = 40, /**< MIO Pad 40 */
1507 kTopEgretPinmuxMioOutIor6 = 41, /**< MIO Pad 41 */
1508 kTopEgretPinmuxMioOutIor7 = 42, /**< MIO Pad 42 */
1509 kTopEgretPinmuxMioOutIor10 = 43, /**< MIO Pad 43 */
1510 kTopEgretPinmuxMioOutIor11 = 44, /**< MIO Pad 44 */
1511 kTopEgretPinmuxMioOutIor12 = 45, /**< MIO Pad 45 */
1512 kTopEgretPinmuxMioOutIor13 = 46, /**< MIO Pad 46 */
1513 kTopEgretPinmuxMioOutLast = 46, /**< \internal Last valid mio output */
1515
1516/**
1517 * Pinmux Peripheral Output Selector.
1518 */
1520 kTopEgretPinmuxOutselConstantZero = 0, /**< Tie constantly to zero */
1521 kTopEgretPinmuxOutselConstantOne = 1, /**< Tie constantly to one */
1522 kTopEgretPinmuxOutselConstantHighZ = 2, /**< Tie constantly to high-Z */
1523 kTopEgretPinmuxOutselGpioGpio0 = 3, /**< Peripheral Output 0 */
1524 kTopEgretPinmuxOutselGpioGpio1 = 4, /**< Peripheral Output 1 */
1525 kTopEgretPinmuxOutselGpioGpio2 = 5, /**< Peripheral Output 2 */
1526 kTopEgretPinmuxOutselGpioGpio3 = 6, /**< Peripheral Output 3 */
1527 kTopEgretPinmuxOutselGpioGpio4 = 7, /**< Peripheral Output 4 */
1528 kTopEgretPinmuxOutselGpioGpio5 = 8, /**< Peripheral Output 5 */
1529 kTopEgretPinmuxOutselGpioGpio6 = 9, /**< Peripheral Output 6 */
1530 kTopEgretPinmuxOutselGpioGpio7 = 10, /**< Peripheral Output 7 */
1531 kTopEgretPinmuxOutselGpioGpio8 = 11, /**< Peripheral Output 8 */
1532 kTopEgretPinmuxOutselGpioGpio9 = 12, /**< Peripheral Output 9 */
1533 kTopEgretPinmuxOutselGpioGpio10 = 13, /**< Peripheral Output 10 */
1534 kTopEgretPinmuxOutselGpioGpio11 = 14, /**< Peripheral Output 11 */
1535 kTopEgretPinmuxOutselGpioGpio12 = 15, /**< Peripheral Output 12 */
1536 kTopEgretPinmuxOutselGpioGpio13 = 16, /**< Peripheral Output 13 */
1537 kTopEgretPinmuxOutselGpioGpio14 = 17, /**< Peripheral Output 14 */
1538 kTopEgretPinmuxOutselGpioGpio15 = 18, /**< Peripheral Output 15 */
1539 kTopEgretPinmuxOutselGpioGpio16 = 19, /**< Peripheral Output 16 */
1540 kTopEgretPinmuxOutselGpioGpio17 = 20, /**< Peripheral Output 17 */
1541 kTopEgretPinmuxOutselGpioGpio18 = 21, /**< Peripheral Output 18 */
1542 kTopEgretPinmuxOutselGpioGpio19 = 22, /**< Peripheral Output 19 */
1543 kTopEgretPinmuxOutselGpioGpio20 = 23, /**< Peripheral Output 20 */
1544 kTopEgretPinmuxOutselGpioGpio21 = 24, /**< Peripheral Output 21 */
1545 kTopEgretPinmuxOutselGpioGpio22 = 25, /**< Peripheral Output 22 */
1546 kTopEgretPinmuxOutselGpioGpio23 = 26, /**< Peripheral Output 23 */
1547 kTopEgretPinmuxOutselGpioGpio24 = 27, /**< Peripheral Output 24 */
1548 kTopEgretPinmuxOutselGpioGpio25 = 28, /**< Peripheral Output 25 */
1549 kTopEgretPinmuxOutselGpioGpio26 = 29, /**< Peripheral Output 26 */
1550 kTopEgretPinmuxOutselGpioGpio27 = 30, /**< Peripheral Output 27 */
1551 kTopEgretPinmuxOutselGpioGpio28 = 31, /**< Peripheral Output 28 */
1552 kTopEgretPinmuxOutselGpioGpio29 = 32, /**< Peripheral Output 29 */
1553 kTopEgretPinmuxOutselGpioGpio30 = 33, /**< Peripheral Output 30 */
1554 kTopEgretPinmuxOutselGpioGpio31 = 34, /**< Peripheral Output 31 */
1555 kTopEgretPinmuxOutselI2c0Sda = 35, /**< Peripheral Output 32 */
1556 kTopEgretPinmuxOutselI2c0Scl = 36, /**< Peripheral Output 33 */
1557 kTopEgretPinmuxOutselI2c1Sda = 37, /**< Peripheral Output 34 */
1558 kTopEgretPinmuxOutselI2c1Scl = 38, /**< Peripheral Output 35 */
1559 kTopEgretPinmuxOutselI2c2Sda = 39, /**< Peripheral Output 36 */
1560 kTopEgretPinmuxOutselI2c2Scl = 40, /**< Peripheral Output 37 */
1561 kTopEgretPinmuxOutselSpiHost1Sd0 = 41, /**< Peripheral Output 38 */
1562 kTopEgretPinmuxOutselSpiHost1Sd1 = 42, /**< Peripheral Output 39 */
1563 kTopEgretPinmuxOutselSpiHost1Sd2 = 43, /**< Peripheral Output 40 */
1564 kTopEgretPinmuxOutselSpiHost1Sd3 = 44, /**< Peripheral Output 41 */
1565 kTopEgretPinmuxOutselUart0Tx = 45, /**< Peripheral Output 42 */
1566 kTopEgretPinmuxOutselUart1Tx = 46, /**< Peripheral Output 43 */
1567 kTopEgretPinmuxOutselUart2Tx = 47, /**< Peripheral Output 44 */
1568 kTopEgretPinmuxOutselUart3Tx = 48, /**< Peripheral Output 45 */
1569 kTopEgretPinmuxOutselPattgenPda0Tx = 49, /**< Peripheral Output 46 */
1570 kTopEgretPinmuxOutselPattgenPcl0Tx = 50, /**< Peripheral Output 47 */
1571 kTopEgretPinmuxOutselPattgenPda1Tx = 51, /**< Peripheral Output 48 */
1572 kTopEgretPinmuxOutselPattgenPcl1Tx = 52, /**< Peripheral Output 49 */
1573 kTopEgretPinmuxOutselSpiHost1Sck = 53, /**< Peripheral Output 50 */
1574 kTopEgretPinmuxOutselSpiHost1Csb = 54, /**< Peripheral Output 51 */
1575 kTopEgretPinmuxOutselFlashMacroWrapperTdo = 55, /**< Peripheral Output 52 */
1576 kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut0 = 56, /**< Peripheral Output 53 */
1577 kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut1 = 57, /**< Peripheral Output 54 */
1578 kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut2 = 58, /**< Peripheral Output 55 */
1579 kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut3 = 59, /**< Peripheral Output 56 */
1580 kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut4 = 60, /**< Peripheral Output 57 */
1581 kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut5 = 61, /**< Peripheral Output 58 */
1582 kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut6 = 62, /**< Peripheral Output 59 */
1583 kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut7 = 63, /**< Peripheral Output 60 */
1584 kTopEgretPinmuxOutselSensorCtrlAonAstDebugOut8 = 64, /**< Peripheral Output 61 */
1585 kTopEgretPinmuxOutselPwmAonPwm0 = 65, /**< Peripheral Output 62 */
1586 kTopEgretPinmuxOutselPwmAonPwm1 = 66, /**< Peripheral Output 63 */
1587 kTopEgretPinmuxOutselPwmAonPwm2 = 67, /**< Peripheral Output 64 */
1588 kTopEgretPinmuxOutselPwmAonPwm3 = 68, /**< Peripheral Output 65 */
1589 kTopEgretPinmuxOutselPwmAonPwm4 = 69, /**< Peripheral Output 66 */
1590 kTopEgretPinmuxOutselPwmAonPwm5 = 70, /**< Peripheral Output 67 */
1591 kTopEgretPinmuxOutselOtpMacroTest0 = 71, /**< Peripheral Output 68 */
1592 kTopEgretPinmuxOutselSysrstCtrlAonBatDisable = 72, /**< Peripheral Output 69 */
1593 kTopEgretPinmuxOutselSysrstCtrlAonKey0Out = 73, /**< Peripheral Output 70 */
1594 kTopEgretPinmuxOutselSysrstCtrlAonKey1Out = 74, /**< Peripheral Output 71 */
1595 kTopEgretPinmuxOutselSysrstCtrlAonKey2Out = 75, /**< Peripheral Output 72 */
1596 kTopEgretPinmuxOutselSysrstCtrlAonPwrbOut = 76, /**< Peripheral Output 73 */
1597 kTopEgretPinmuxOutselSysrstCtrlAonZ3Wakeup = 77, /**< Peripheral Output 74 */
1598 kTopEgretPinmuxOutselLast = 77, /**< \internal Last valid outsel value */
1600
1601/**
1602 * Dedicated Pad Selects
1603 */
1605 kTopEgretDirectPadsUsbdevUsbDp = 0, /**< */
1606 kTopEgretDirectPadsUsbdevUsbDn = 1, /**< */
1607 kTopEgretDirectPadsSpiHost0Sd0 = 2, /**< */
1608 kTopEgretDirectPadsSpiHost0Sd1 = 3, /**< */
1609 kTopEgretDirectPadsSpiHost0Sd2 = 4, /**< */
1610 kTopEgretDirectPadsSpiHost0Sd3 = 5, /**< */
1611 kTopEgretDirectPadsSpiDeviceSd0 = 6, /**< */
1612 kTopEgretDirectPadsSpiDeviceSd1 = 7, /**< */
1613 kTopEgretDirectPadsSpiDeviceSd2 = 8, /**< */
1614 kTopEgretDirectPadsSpiDeviceSd3 = 9, /**< */
1615 kTopEgretDirectPadsSysrstCtrlAonEcRstL = 10, /**< */
1616 kTopEgretDirectPadsSysrstCtrlAonFlashWpL = 11, /**< */
1617 kTopEgretDirectPadsSpiDeviceSck = 12, /**< */
1618 kTopEgretDirectPadsSpiDeviceCsb = 13, /**< */
1619 kTopEgretDirectPadsSpiHost0Sck = 14, /**< */
1620 kTopEgretDirectPadsSpiHost0Csb = 15, /**< */
1621 kTopEgretDirectPadsLast = 15, /**< \internal Last valid direct pad */
1623
1624/**
1625 * Muxed Pad Selects
1626 */
1628 kTopEgretMuxedPadsIoa0 = 0, /**< */
1629 kTopEgretMuxedPadsIoa1 = 1, /**< */
1630 kTopEgretMuxedPadsIoa2 = 2, /**< */
1631 kTopEgretMuxedPadsIoa3 = 3, /**< */
1632 kTopEgretMuxedPadsIoa4 = 4, /**< */
1633 kTopEgretMuxedPadsIoa5 = 5, /**< */
1634 kTopEgretMuxedPadsIoa6 = 6, /**< */
1635 kTopEgretMuxedPadsIoa7 = 7, /**< */
1636 kTopEgretMuxedPadsIoa8 = 8, /**< */
1637 kTopEgretMuxedPadsIob0 = 9, /**< */
1638 kTopEgretMuxedPadsIob1 = 10, /**< */
1639 kTopEgretMuxedPadsIob2 = 11, /**< */
1640 kTopEgretMuxedPadsIob3 = 12, /**< */
1641 kTopEgretMuxedPadsIob4 = 13, /**< */
1642 kTopEgretMuxedPadsIob5 = 14, /**< */
1643 kTopEgretMuxedPadsIob6 = 15, /**< */
1644 kTopEgretMuxedPadsIob7 = 16, /**< */
1645 kTopEgretMuxedPadsIob8 = 17, /**< */
1646 kTopEgretMuxedPadsIob9 = 18, /**< */
1647 kTopEgretMuxedPadsIob10 = 19, /**< */
1648 kTopEgretMuxedPadsIob11 = 20, /**< */
1649 kTopEgretMuxedPadsIob12 = 21, /**< */
1650 kTopEgretMuxedPadsIoc0 = 22, /**< */
1651 kTopEgretMuxedPadsIoc1 = 23, /**< */
1652 kTopEgretMuxedPadsIoc2 = 24, /**< */
1653 kTopEgretMuxedPadsIoc3 = 25, /**< */
1654 kTopEgretMuxedPadsIoc4 = 26, /**< */
1655 kTopEgretMuxedPadsIoc5 = 27, /**< */
1656 kTopEgretMuxedPadsIoc6 = 28, /**< */
1657 kTopEgretMuxedPadsIoc7 = 29, /**< */
1658 kTopEgretMuxedPadsIoc8 = 30, /**< */
1659 kTopEgretMuxedPadsIoc9 = 31, /**< */
1660 kTopEgretMuxedPadsIoc10 = 32, /**< */
1661 kTopEgretMuxedPadsIoc11 = 33, /**< */
1662 kTopEgretMuxedPadsIoc12 = 34, /**< */
1663 kTopEgretMuxedPadsIor0 = 35, /**< */
1664 kTopEgretMuxedPadsIor1 = 36, /**< */
1665 kTopEgretMuxedPadsIor2 = 37, /**< */
1666 kTopEgretMuxedPadsIor3 = 38, /**< */
1667 kTopEgretMuxedPadsIor4 = 39, /**< */
1668 kTopEgretMuxedPadsIor5 = 40, /**< */
1669 kTopEgretMuxedPadsIor6 = 41, /**< */
1670 kTopEgretMuxedPadsIor7 = 42, /**< */
1671 kTopEgretMuxedPadsIor10 = 43, /**< */
1672 kTopEgretMuxedPadsIor11 = 44, /**< */
1673 kTopEgretMuxedPadsIor12 = 45, /**< */
1674 kTopEgretMuxedPadsIor13 = 46, /**< */
1675 kTopEgretMuxedPadsLast = 46, /**< \internal Last valid muxed pad */
1677
1678/**
1679 * Power Manager Wakeup Signals
1680 */
1682 kTopEgretPowerManagerWakeUpsSysrstCtrlAonWkupReq = 0, /**< */
1683 kTopEgretPowerManagerWakeUpsAdcCtrlAonWkupReq = 1, /**< */
1684 kTopEgretPowerManagerWakeUpsPinmuxAonPinWkupReq = 2, /**< */
1685 kTopEgretPowerManagerWakeUpsPinmuxAonUsbWkupReq = 3, /**< */
1686 kTopEgretPowerManagerWakeUpsAonTimerAonWkupReq = 4, /**< */
1687 kTopEgretPowerManagerWakeUpsSensorCtrlAonWkupReq = 5, /**< */
1688 kTopEgretPowerManagerWakeUpsLast = 5, /**< \internal Last valid pwrmgr wakeup signal */
1690
1691/**
1692 * Reset Manager Software Controlled Resets
1693 */
1695 kTopEgretResetManagerSwResetsSpiDevice = 0, /**< */
1696 kTopEgretResetManagerSwResetsSpiHost0 = 1, /**< */
1697 kTopEgretResetManagerSwResetsSpiHost1 = 2, /**< */
1698 kTopEgretResetManagerSwResetsUsb = 3, /**< */
1699 kTopEgretResetManagerSwResetsUsbAon = 4, /**< */
1700 kTopEgretResetManagerSwResetsI2c0 = 5, /**< */
1701 kTopEgretResetManagerSwResetsI2c1 = 6, /**< */
1702 kTopEgretResetManagerSwResetsI2c2 = 7, /**< */
1703 kTopEgretResetManagerSwResetsLast = 7, /**< \internal Last valid rstmgr software reset request */
1705
1706/**
1707 * Power Manager Reset Request Signals
1708 */
1710 kTopEgretPowerManagerResetRequestsSysrstCtrlAonRstReq = 0, /**< */
1711 kTopEgretPowerManagerResetRequestsAonTimerAonAonTimerRstReq = 1, /**< */
1712 kTopEgretPowerManagerResetRequestsLast = 1, /**< \internal Last valid pwrmgr reset_request signal */
1714
1715/**
1716 * Clock Manager Software-Controlled ("Gated") Clocks.
1717 *
1718 * The Software has full control over these clocks.
1719 */
1721 kTopEgretGateableClocksIoDiv4Peri = 0, /**< Clock clk_io_div4_peri in group peri */
1722 kTopEgretGateableClocksIoDiv2Peri = 1, /**< Clock clk_io_div2_peri in group peri */
1723 kTopEgretGateableClocksIoPeri = 2, /**< Clock clk_io_peri in group peri */
1724 kTopEgretGateableClocksUsbPeri = 3, /**< Clock clk_usb_peri in group peri */
1725 kTopEgretGateableClocksLast = 3, /**< \internal Last Valid Gateable Clock */
1727
1728/**
1729 * Clock Manager Software-Hinted Clocks.
1730 *
1731 * The Software has partial control over these clocks. It can ask them to stop,
1732 * but the clock manager is in control of whether the clock actually is stopped.
1733 */
1735 kTopEgretHintableClocksMainAcc = 0, /**< Clock clk_main_acc in group trans */
1736 kTopEgretHintableClocksMainAes = 1, /**< Clock clk_main_aes in group trans */
1737 kTopEgretHintableClocksMainHmac = 2, /**< Clock clk_main_hmac in group trans */
1738 kTopEgretHintableClocksMainKmac = 3, /**< Clock clk_main_kmac in group trans */
1739 kTopEgretHintableClocksLast = 3, /**< \internal Last Valid Hintable Clock */
1741
1742/**
1743 * MMIO Region
1744 *
1745 * MMIO region excludes any memory that is separate from the module
1746 * configuration space, i.e. ROM, main SRAM, and flash are excluded but
1747 * retention SRAM, spi_device memory, or usbdev memory are included.
1748 */
1749#define TOP_EGRET_MMIO_BASE_ADDR 0x40000000u
1750#define TOP_EGRET_MMIO_SIZE_BYTES 0x10000000u
1751
1752// Header Extern Guard
1753#ifdef __cplusplus
1754} // extern "C"
1755#endif
1756
1757#endif // OPENTITAN_HW_TOP_EGRET_SW_AUTOGEN_TOP_EGRET_H_