Pavona Software APIs
top_scafi_deprecated.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
6// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
7// util/topgen.py -t hw/top_scafi_deprecated/data/top_scafi_deprecated.hjson
8// -o hw/top_scafi_deprecated/
9
10#ifndef OPENTITAN_HW_TOP_SCAFI_DEPRECATED_SW_AUTOGEN_TOP_SCAFI_DEPRECATED_H_
11#define OPENTITAN_HW_TOP_SCAFI_DEPRECATED_SW_AUTOGEN_TOP_SCAFI_DEPRECATED_H_
12
13/**
14 * @file
15 * @brief Top-specific Definitions
16 *
17 * This file contains preprocessor and type definitions for use within the
18 * device C/C++ codebase.
19 *
20 * These definitions are for information that depends on the top-specific chip
21 * configuration, which includes:
22 * - Device Memory Information (for Peripherals and Memory)
23 * - PLIC Interrupt ID Names and Source Mappings
24 * - Pinmux Pin/Select Names
25 * - Power Manager Wakeups
26 */
27
28#ifdef __cplusplus
29extern "C" {
30#endif
31
32/**
33 * Peripheral base address for uart0 in top scafi_deprecated.
34 *
35 * This should be used with #mmio_region_from_addr to access the memory-mapped
36 * registers associated with the peripheral (usually via a DIF).
37 */
38#define TOP_SCAFI_DEPRECATED_UART0_BASE_ADDR 0x40000000u
39
40/**
41 * Peripheral size for uart0 in top scafi_deprecated.
42 *
43 * This is the size (in bytes) of the peripheral's reserved memory area. All
44 * memory-mapped registers associated with this peripheral should have an
45 * address between #TOP_SCAFI_DEPRECATED_UART0_BASE_ADDR and
46 * `TOP_SCAFI_DEPRECATED_UART0_BASE_ADDR + TOP_SCAFI_DEPRECATED_UART0_SIZE_BYTES`.
47 */
48#define TOP_SCAFI_DEPRECATED_UART0_SIZE_BYTES 0x40u
49
50/**
51 * Peripheral base address for uart1 in top scafi_deprecated.
52 *
53 * This should be used with #mmio_region_from_addr to access the memory-mapped
54 * registers associated with the peripheral (usually via a DIF).
55 */
56#define TOP_SCAFI_DEPRECATED_UART1_BASE_ADDR 0x40010000u
57
58/**
59 * Peripheral size for uart1 in top scafi_deprecated.
60 *
61 * This is the size (in bytes) of the peripheral's reserved memory area. All
62 * memory-mapped registers associated with this peripheral should have an
63 * address between #TOP_SCAFI_DEPRECATED_UART1_BASE_ADDR and
64 * `TOP_SCAFI_DEPRECATED_UART1_BASE_ADDR + TOP_SCAFI_DEPRECATED_UART1_SIZE_BYTES`.
65 */
66#define TOP_SCAFI_DEPRECATED_UART1_SIZE_BYTES 0x40u
67
68/**
69 * Peripheral base address for gpio in top scafi_deprecated.
70 *
71 * This should be used with #mmio_region_from_addr to access the memory-mapped
72 * registers associated with the peripheral (usually via a DIF).
73 */
74#define TOP_SCAFI_DEPRECATED_GPIO_BASE_ADDR 0x40040000u
75
76/**
77 * Peripheral size for gpio in top scafi_deprecated.
78 *
79 * This is the size (in bytes) of the peripheral's reserved memory area. All
80 * memory-mapped registers associated with this peripheral should have an
81 * address between #TOP_SCAFI_DEPRECATED_GPIO_BASE_ADDR and
82 * `TOP_SCAFI_DEPRECATED_GPIO_BASE_ADDR + TOP_SCAFI_DEPRECATED_GPIO_SIZE_BYTES`.
83 */
84#define TOP_SCAFI_DEPRECATED_GPIO_SIZE_BYTES 0x80u
85
86/**
87 * Peripheral base address for spi_device in top scafi_deprecated.
88 *
89 * This should be used with #mmio_region_from_addr to access the memory-mapped
90 * registers associated with the peripheral (usually via a DIF).
91 */
92#define TOP_SCAFI_DEPRECATED_SPI_DEVICE_BASE_ADDR 0x40050000u
93
94/**
95 * Peripheral size for spi_device in top scafi_deprecated.
96 *
97 * This is the size (in bytes) of the peripheral's reserved memory area. All
98 * memory-mapped registers associated with this peripheral should have an
99 * address between #TOP_SCAFI_DEPRECATED_SPI_DEVICE_BASE_ADDR and
100 * `TOP_SCAFI_DEPRECATED_SPI_DEVICE_BASE_ADDR + TOP_SCAFI_DEPRECATED_SPI_DEVICE_SIZE_BYTES`.
101 */
102#define TOP_SCAFI_DEPRECATED_SPI_DEVICE_SIZE_BYTES 0x2000u
103
104/**
105 * Peripheral base address for spi_host0 in top scafi_deprecated.
106 *
107 * This should be used with #mmio_region_from_addr to access the memory-mapped
108 * registers associated with the peripheral (usually via a DIF).
109 */
110#define TOP_SCAFI_DEPRECATED_SPI_HOST0_BASE_ADDR 0x40060000u
111
112/**
113 * Peripheral size for spi_host0 in top scafi_deprecated.
114 *
115 * This is the size (in bytes) of the peripheral's reserved memory area. All
116 * memory-mapped registers associated with this peripheral should have an
117 * address between #TOP_SCAFI_DEPRECATED_SPI_HOST0_BASE_ADDR and
118 * `TOP_SCAFI_DEPRECATED_SPI_HOST0_BASE_ADDR + TOP_SCAFI_DEPRECATED_SPI_HOST0_SIZE_BYTES`.
119 */
120#define TOP_SCAFI_DEPRECATED_SPI_HOST0_SIZE_BYTES 0x40u
121
122/**
123 * Peripheral base address for rv_timer in top scafi_deprecated.
124 *
125 * This should be used with #mmio_region_from_addr to access the memory-mapped
126 * registers associated with the peripheral (usually via a DIF).
127 */
128#define TOP_SCAFI_DEPRECATED_RV_TIMER_BASE_ADDR 0x40100000u
129
130/**
131 * Peripheral size for rv_timer in top scafi_deprecated.
132 *
133 * This is the size (in bytes) of the peripheral's reserved memory area. All
134 * memory-mapped registers associated with this peripheral should have an
135 * address between #TOP_SCAFI_DEPRECATED_RV_TIMER_BASE_ADDR and
136 * `TOP_SCAFI_DEPRECATED_RV_TIMER_BASE_ADDR + TOP_SCAFI_DEPRECATED_RV_TIMER_SIZE_BYTES`.
137 */
138#define TOP_SCAFI_DEPRECATED_RV_TIMER_SIZE_BYTES 0x200u
139
140/**
141 * Peripheral base address for usbdev in top scafi_deprecated.
142 *
143 * This should be used with #mmio_region_from_addr to access the memory-mapped
144 * registers associated with the peripheral (usually via a DIF).
145 */
146#define TOP_SCAFI_DEPRECATED_USBDEV_BASE_ADDR 0x40320000u
147
148/**
149 * Peripheral size for usbdev in top scafi_deprecated.
150 *
151 * This is the size (in bytes) of the peripheral's reserved memory area. All
152 * memory-mapped registers associated with this peripheral should have an
153 * address between #TOP_SCAFI_DEPRECATED_USBDEV_BASE_ADDR and
154 * `TOP_SCAFI_DEPRECATED_USBDEV_BASE_ADDR + TOP_SCAFI_DEPRECATED_USBDEV_SIZE_BYTES`.
155 */
156#define TOP_SCAFI_DEPRECATED_USBDEV_SIZE_BYTES 0x1000u
157
158/**
159 * Peripheral base address for pwrmgr_aon in top scafi_deprecated.
160 *
161 * This should be used with #mmio_region_from_addr to access the memory-mapped
162 * registers associated with the peripheral (usually via a DIF).
163 */
164#define TOP_SCAFI_DEPRECATED_PWRMGR_AON_BASE_ADDR 0x40400000u
165
166/**
167 * Peripheral size for pwrmgr_aon in top scafi_deprecated.
168 *
169 * This is the size (in bytes) of the peripheral's reserved memory area. All
170 * memory-mapped registers associated with this peripheral should have an
171 * address between #TOP_SCAFI_DEPRECATED_PWRMGR_AON_BASE_ADDR and
172 * `TOP_SCAFI_DEPRECATED_PWRMGR_AON_BASE_ADDR + TOP_SCAFI_DEPRECATED_PWRMGR_AON_SIZE_BYTES`.
173 */
174#define TOP_SCAFI_DEPRECATED_PWRMGR_AON_SIZE_BYTES 0x80u
175
176/**
177 * Peripheral base address for rstmgr_aon in top scafi_deprecated.
178 *
179 * This should be used with #mmio_region_from_addr to access the memory-mapped
180 * registers associated with the peripheral (usually via a DIF).
181 */
182#define TOP_SCAFI_DEPRECATED_RSTMGR_AON_BASE_ADDR 0x40410000u
183
184/**
185 * Peripheral size for rstmgr_aon in top scafi_deprecated.
186 *
187 * This is the size (in bytes) of the peripheral's reserved memory area. All
188 * memory-mapped registers associated with this peripheral should have an
189 * address between #TOP_SCAFI_DEPRECATED_RSTMGR_AON_BASE_ADDR and
190 * `TOP_SCAFI_DEPRECATED_RSTMGR_AON_BASE_ADDR + TOP_SCAFI_DEPRECATED_RSTMGR_AON_SIZE_BYTES`.
191 */
192#define TOP_SCAFI_DEPRECATED_RSTMGR_AON_SIZE_BYTES 0x80u
193
194/**
195 * Peripheral base address for clkmgr_aon in top scafi_deprecated.
196 *
197 * This should be used with #mmio_region_from_addr to access the memory-mapped
198 * registers associated with the peripheral (usually via a DIF).
199 */
200#define TOP_SCAFI_DEPRECATED_CLKMGR_AON_BASE_ADDR 0x40420000u
201
202/**
203 * Peripheral size for clkmgr_aon in top scafi_deprecated.
204 *
205 * This is the size (in bytes) of the peripheral's reserved memory area. All
206 * memory-mapped registers associated with this peripheral should have an
207 * address between #TOP_SCAFI_DEPRECATED_CLKMGR_AON_BASE_ADDR and
208 * `TOP_SCAFI_DEPRECATED_CLKMGR_AON_BASE_ADDR + TOP_SCAFI_DEPRECATED_CLKMGR_AON_SIZE_BYTES`.
209 */
210#define TOP_SCAFI_DEPRECATED_CLKMGR_AON_SIZE_BYTES 0x80u
211
212/**
213 * Peripheral base address for pinmux_aon in top scafi_deprecated.
214 *
215 * This should be used with #mmio_region_from_addr to access the memory-mapped
216 * registers associated with the peripheral (usually via a DIF).
217 */
218#define TOP_SCAFI_DEPRECATED_PINMUX_AON_BASE_ADDR 0x40460000u
219
220/**
221 * Peripheral size for pinmux_aon in top scafi_deprecated.
222 *
223 * This is the size (in bytes) of the peripheral's reserved memory area. All
224 * memory-mapped registers associated with this peripheral should have an
225 * address between #TOP_SCAFI_DEPRECATED_PINMUX_AON_BASE_ADDR and
226 * `TOP_SCAFI_DEPRECATED_PINMUX_AON_BASE_ADDR + TOP_SCAFI_DEPRECATED_PINMUX_AON_SIZE_BYTES`.
227 */
228#define TOP_SCAFI_DEPRECATED_PINMUX_AON_SIZE_BYTES 0x1000u
229
230/**
231 * Peripheral base address for aon_timer_aon in top scafi_deprecated.
232 *
233 * This should be used with #mmio_region_from_addr to access the memory-mapped
234 * registers associated with the peripheral (usually via a DIF).
235 */
236#define TOP_SCAFI_DEPRECATED_AON_TIMER_AON_BASE_ADDR 0x40470000u
237
238/**
239 * Peripheral size for aon_timer_aon in top scafi_deprecated.
240 *
241 * This is the size (in bytes) of the peripheral's reserved memory area. All
242 * memory-mapped registers associated with this peripheral should have an
243 * address between #TOP_SCAFI_DEPRECATED_AON_TIMER_AON_BASE_ADDR and
244 * `TOP_SCAFI_DEPRECATED_AON_TIMER_AON_BASE_ADDR + TOP_SCAFI_DEPRECATED_AON_TIMER_AON_SIZE_BYTES`.
245 */
246#define TOP_SCAFI_DEPRECATED_AON_TIMER_AON_SIZE_BYTES 0x40u
247
248/**
249 * Peripheral base address for ast in top scafi_deprecated.
250 *
251 * This should be used with #mmio_region_from_addr to access the memory-mapped
252 * registers associated with the peripheral (usually via a DIF).
253 */
254#define TOP_SCAFI_DEPRECATED_AST_BASE_ADDR 0x40480000u
255
256/**
257 * Peripheral size for ast in top scafi_deprecated.
258 *
259 * This is the size (in bytes) of the peripheral's reserved memory area. All
260 * memory-mapped registers associated with this peripheral should have an
261 * address between #TOP_SCAFI_DEPRECATED_AST_BASE_ADDR and
262 * `TOP_SCAFI_DEPRECATED_AST_BASE_ADDR + TOP_SCAFI_DEPRECATED_AST_SIZE_BYTES`.
263 */
264#define TOP_SCAFI_DEPRECATED_AST_SIZE_BYTES 0x400u
265
266/**
267 * Peripheral base address for core device on flash_ctrl in top scafi_deprecated.
268 *
269 * This should be used with #mmio_region_from_addr to access the memory-mapped
270 * registers associated with the peripheral (usually via a DIF).
271 */
272#define TOP_SCAFI_DEPRECATED_FLASH_CTRL_CORE_BASE_ADDR 0x41000000u
273
274/**
275 * Peripheral size for core device on flash_ctrl in top scafi_deprecated.
276 *
277 * This is the size (in bytes) of the peripheral's reserved memory area. All
278 * memory-mapped registers associated with this peripheral should have an
279 * address between #TOP_SCAFI_DEPRECATED_FLASH_CTRL_CORE_BASE_ADDR and
280 * `TOP_SCAFI_DEPRECATED_FLASH_CTRL_CORE_BASE_ADDR + TOP_SCAFI_DEPRECATED_FLASH_CTRL_CORE_SIZE_BYTES`.
281 */
282#define TOP_SCAFI_DEPRECATED_FLASH_CTRL_CORE_SIZE_BYTES 0x200u
283
284/**
285 * Peripheral base address for flash_macro_wrapper in top scafi_deprecated.
286 *
287 * This should be used with #mmio_region_from_addr to access the memory-mapped
288 * registers associated with the peripheral (usually via a DIF).
289 */
290#define TOP_SCAFI_DEPRECATED_FLASH_MACRO_WRAPPER_BASE_ADDR 0x41008000u
291
292/**
293 * Peripheral size for flash_macro_wrapper in top scafi_deprecated.
294 *
295 * This is the size (in bytes) of the peripheral's reserved memory area. All
296 * memory-mapped registers associated with this peripheral should have an
297 * address between #TOP_SCAFI_DEPRECATED_FLASH_MACRO_WRAPPER_BASE_ADDR and
298 * `TOP_SCAFI_DEPRECATED_FLASH_MACRO_WRAPPER_BASE_ADDR + TOP_SCAFI_DEPRECATED_FLASH_MACRO_WRAPPER_SIZE_BYTES`.
299 */
300#define TOP_SCAFI_DEPRECATED_FLASH_MACRO_WRAPPER_SIZE_BYTES 0x80u
301
302/**
303 * Peripheral base address for rv_plic in top scafi_deprecated.
304 *
305 * This should be used with #mmio_region_from_addr to access the memory-mapped
306 * registers associated with the peripheral (usually via a DIF).
307 */
308#define TOP_SCAFI_DEPRECATED_RV_PLIC_BASE_ADDR 0x48000000u
309
310/**
311 * Peripheral size for rv_plic in top scafi_deprecated.
312 *
313 * This is the size (in bytes) of the peripheral's reserved memory area. All
314 * memory-mapped registers associated with this peripheral should have an
315 * address between #TOP_SCAFI_DEPRECATED_RV_PLIC_BASE_ADDR and
316 * `TOP_SCAFI_DEPRECATED_RV_PLIC_BASE_ADDR + TOP_SCAFI_DEPRECATED_RV_PLIC_SIZE_BYTES`.
317 */
318#define TOP_SCAFI_DEPRECATED_RV_PLIC_SIZE_BYTES 0x8000000u
319
320/**
321 * Peripheral base address for aes in top scafi_deprecated.
322 *
323 * This should be used with #mmio_region_from_addr to access the memory-mapped
324 * registers associated with the peripheral (usually via a DIF).
325 */
326#define TOP_SCAFI_DEPRECATED_AES_BASE_ADDR 0x41100000u
327
328/**
329 * Peripheral size for aes in top scafi_deprecated.
330 *
331 * This is the size (in bytes) of the peripheral's reserved memory area. All
332 * memory-mapped registers associated with this peripheral should have an
333 * address between #TOP_SCAFI_DEPRECATED_AES_BASE_ADDR and
334 * `TOP_SCAFI_DEPRECATED_AES_BASE_ADDR + TOP_SCAFI_DEPRECATED_AES_SIZE_BYTES`.
335 */
336#define TOP_SCAFI_DEPRECATED_AES_SIZE_BYTES 0x100u
337
338/**
339 * Peripheral base address for regs device on sram_ctrl_main in top scafi_deprecated.
340 *
341 * This should be used with #mmio_region_from_addr to access the memory-mapped
342 * registers associated with the peripheral (usually via a DIF).
343 */
344#define TOP_SCAFI_DEPRECATED_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000u
345
346/**
347 * Peripheral size for regs device on sram_ctrl_main in top scafi_deprecated.
348 *
349 * This is the size (in bytes) of the peripheral's reserved memory area. All
350 * memory-mapped registers associated with this peripheral should have an
351 * address between #TOP_SCAFI_DEPRECATED_SRAM_CTRL_MAIN_REGS_BASE_ADDR and
352 * `TOP_SCAFI_DEPRECATED_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_SCAFI_DEPRECATED_SRAM_CTRL_MAIN_REGS_SIZE_BYTES`.
353 */
354#define TOP_SCAFI_DEPRECATED_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40u
355
356/**
357 * Peripheral base address for regs device on rom_ctrl in top scafi_deprecated.
358 *
359 * This should be used with #mmio_region_from_addr to access the memory-mapped
360 * registers associated with the peripheral (usually via a DIF).
361 */
362#define TOP_SCAFI_DEPRECATED_ROM_CTRL_REGS_BASE_ADDR 0x411E0000u
363
364/**
365 * Peripheral size for regs device on rom_ctrl in top scafi_deprecated.
366 *
367 * This is the size (in bytes) of the peripheral's reserved memory area. All
368 * memory-mapped registers associated with this peripheral should have an
369 * address between #TOP_SCAFI_DEPRECATED_ROM_CTRL_REGS_BASE_ADDR and
370 * `TOP_SCAFI_DEPRECATED_ROM_CTRL_REGS_BASE_ADDR + TOP_SCAFI_DEPRECATED_ROM_CTRL_REGS_SIZE_BYTES`.
371 */
372#define TOP_SCAFI_DEPRECATED_ROM_CTRL_REGS_SIZE_BYTES 0x80u
373
374/**
375 * Peripheral base address for cfg device on rv_core_ibex in top scafi_deprecated.
376 *
377 * This should be used with #mmio_region_from_addr to access the memory-mapped
378 * registers associated with the peripheral (usually via a DIF).
379 */
380#define TOP_SCAFI_DEPRECATED_RV_CORE_IBEX_CFG_BASE_ADDR 0x411F0000u
381
382/**
383 * Peripheral size for cfg device on rv_core_ibex in top scafi_deprecated.
384 *
385 * This is the size (in bytes) of the peripheral's reserved memory area. All
386 * memory-mapped registers associated with this peripheral should have an
387 * address between #TOP_SCAFI_DEPRECATED_RV_CORE_IBEX_CFG_BASE_ADDR and
388 * `TOP_SCAFI_DEPRECATED_RV_CORE_IBEX_CFG_BASE_ADDR + TOP_SCAFI_DEPRECATED_RV_CORE_IBEX_CFG_SIZE_BYTES`.
389 */
390#define TOP_SCAFI_DEPRECATED_RV_CORE_IBEX_CFG_SIZE_BYTES 0x100u
391
392
393/**
394 * Memory base address for mem memory on flash_ctrl in top scafi_deprecated.
395 */
396#define TOP_SCAFI_DEPRECATED_FLASH_CTRL_MEM_BASE_ADDR 0x20000000u
397
398/**
399 * Memory size for mem memory on flash_ctrl in top scafi_deprecated.
400 */
401#define TOP_SCAFI_DEPRECATED_FLASH_CTRL_MEM_SIZE_BYTES 0x10000u
402
403/**
404 * Memory base address for ram memory on sram_ctrl_main in top scafi_deprecated.
405 */
406#define TOP_SCAFI_DEPRECATED_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000u
407
408/**
409 * Memory size for ram memory on sram_ctrl_main in top scafi_deprecated.
410 */
411#define TOP_SCAFI_DEPRECATED_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000u
412
413/**
414 * Memory base address for rom memory on rom_ctrl in top scafi_deprecated.
415 */
416#define TOP_SCAFI_DEPRECATED_ROM_CTRL_ROM_BASE_ADDR 0x8000u
417
418/**
419 * Memory size for rom memory on rom_ctrl in top scafi_deprecated.
420 */
421#define TOP_SCAFI_DEPRECATED_ROM_CTRL_ROM_SIZE_BYTES 0x8000u
422
423
424/**
425 * PLIC Interrupt Source Peripheral.
426 *
427 * Enumeration used to determine which peripheral asserted the corresponding
428 * interrupt.
429 */
443
444/**
445 * PLIC Interrupt Source.
446 *
447 * Enumeration of all PLIC interrupt sources. The interrupt sources belonging to
448 * the same peripheral are guaranteed to be consecutive.
449 */
451 kTopScafiDeprecatedPlicIrqIdNone = 0, /**< No Interrupt */
452 kTopScafiDeprecatedPlicIrqIdUart0TxWatermark = 1, /**< uart0_tx_watermark */
453 kTopScafiDeprecatedPlicIrqIdUart0RxWatermark = 2, /**< uart0_rx_watermark */
455 kTopScafiDeprecatedPlicIrqIdUart0RxOverflow = 4, /**< uart0_rx_overflow */
456 kTopScafiDeprecatedPlicIrqIdUart0RxFrameErr = 5, /**< uart0_rx_frame_err */
457 kTopScafiDeprecatedPlicIrqIdUart0RxBreakErr = 6, /**< uart0_rx_break_err */
458 kTopScafiDeprecatedPlicIrqIdUart0RxTimeout = 7, /**< uart0_rx_timeout */
459 kTopScafiDeprecatedPlicIrqIdUart0RxParityErr = 8, /**< uart0_rx_parity_err */
461 kTopScafiDeprecatedPlicIrqIdUart1TxWatermark = 10, /**< uart1_tx_watermark */
462 kTopScafiDeprecatedPlicIrqIdUart1RxWatermark = 11, /**< uart1_rx_watermark */
463 kTopScafiDeprecatedPlicIrqIdUart1TxDone = 12, /**< uart1_tx_done */
464 kTopScafiDeprecatedPlicIrqIdUart1RxOverflow = 13, /**< uart1_rx_overflow */
465 kTopScafiDeprecatedPlicIrqIdUart1RxFrameErr = 14, /**< uart1_rx_frame_err */
466 kTopScafiDeprecatedPlicIrqIdUart1RxBreakErr = 15, /**< uart1_rx_break_err */
467 kTopScafiDeprecatedPlicIrqIdUart1RxTimeout = 16, /**< uart1_rx_timeout */
468 kTopScafiDeprecatedPlicIrqIdUart1RxParityErr = 17, /**< uart1_rx_parity_err */
469 kTopScafiDeprecatedPlicIrqIdUart1TxEmpty = 18, /**< uart1_tx_empty */
480 kTopScafiDeprecatedPlicIrqIdGpioGpio10 = 29, /**< gpio_gpio 10 */
481 kTopScafiDeprecatedPlicIrqIdGpioGpio11 = 30, /**< gpio_gpio 11 */
482 kTopScafiDeprecatedPlicIrqIdGpioGpio12 = 31, /**< gpio_gpio 12 */
483 kTopScafiDeprecatedPlicIrqIdGpioGpio13 = 32, /**< gpio_gpio 13 */
484 kTopScafiDeprecatedPlicIrqIdGpioGpio14 = 33, /**< gpio_gpio 14 */
485 kTopScafiDeprecatedPlicIrqIdGpioGpio15 = 34, /**< gpio_gpio 15 */
486 kTopScafiDeprecatedPlicIrqIdGpioGpio16 = 35, /**< gpio_gpio 16 */
487 kTopScafiDeprecatedPlicIrqIdGpioGpio17 = 36, /**< gpio_gpio 17 */
488 kTopScafiDeprecatedPlicIrqIdGpioGpio18 = 37, /**< gpio_gpio 18 */
489 kTopScafiDeprecatedPlicIrqIdGpioGpio19 = 38, /**< gpio_gpio 19 */
490 kTopScafiDeprecatedPlicIrqIdGpioGpio20 = 39, /**< gpio_gpio 20 */
491 kTopScafiDeprecatedPlicIrqIdGpioGpio21 = 40, /**< gpio_gpio 21 */
492 kTopScafiDeprecatedPlicIrqIdGpioGpio22 = 41, /**< gpio_gpio 22 */
493 kTopScafiDeprecatedPlicIrqIdGpioGpio23 = 42, /**< gpio_gpio 23 */
494 kTopScafiDeprecatedPlicIrqIdGpioGpio24 = 43, /**< gpio_gpio 24 */
495 kTopScafiDeprecatedPlicIrqIdGpioGpio25 = 44, /**< gpio_gpio 25 */
496 kTopScafiDeprecatedPlicIrqIdGpioGpio26 = 45, /**< gpio_gpio 26 */
497 kTopScafiDeprecatedPlicIrqIdGpioGpio27 = 46, /**< gpio_gpio 27 */
498 kTopScafiDeprecatedPlicIrqIdGpioGpio28 = 47, /**< gpio_gpio 28 */
499 kTopScafiDeprecatedPlicIrqIdGpioGpio29 = 48, /**< gpio_gpio 29 */
500 kTopScafiDeprecatedPlicIrqIdGpioGpio30 = 49, /**< gpio_gpio 30 */
501 kTopScafiDeprecatedPlicIrqIdGpioGpio31 = 50, /**< gpio_gpio 31 */
502 kTopScafiDeprecatedPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty = 51, /**< spi_device_upload_cmdfifo_not_empty */
503 kTopScafiDeprecatedPlicIrqIdSpiDeviceUploadPayloadNotEmpty = 52, /**< spi_device_upload_payload_not_empty */
504 kTopScafiDeprecatedPlicIrqIdSpiDeviceUploadPayloadOverflow = 53, /**< spi_device_upload_payload_overflow */
505 kTopScafiDeprecatedPlicIrqIdSpiDeviceReadbufWatermark = 54, /**< spi_device_readbuf_watermark */
506 kTopScafiDeprecatedPlicIrqIdSpiDeviceReadbufFlip = 55, /**< spi_device_readbuf_flip */
507 kTopScafiDeprecatedPlicIrqIdSpiDeviceTpmHeaderNotEmpty = 56, /**< spi_device_tpm_header_not_empty */
508 kTopScafiDeprecatedPlicIrqIdSpiDeviceTpmRdfifoCmdEnd = 57, /**< spi_device_tpm_rdfifo_cmd_end */
509 kTopScafiDeprecatedPlicIrqIdSpiDeviceTpmRdfifoDrop = 58, /**< spi_device_tpm_rdfifo_drop */
510 kTopScafiDeprecatedPlicIrqIdSpiHost0Error = 59, /**< spi_host0_error */
511 kTopScafiDeprecatedPlicIrqIdSpiHost0SpiEvent = 60, /**< spi_host0_spi_event */
512 kTopScafiDeprecatedPlicIrqIdUsbdevPktReceived = 61, /**< usbdev_pkt_received */
513 kTopScafiDeprecatedPlicIrqIdUsbdevPktSent = 62, /**< usbdev_pkt_sent */
514 kTopScafiDeprecatedPlicIrqIdUsbdevDisconnected = 63, /**< usbdev_disconnected */
515 kTopScafiDeprecatedPlicIrqIdUsbdevHostLost = 64, /**< usbdev_host_lost */
516 kTopScafiDeprecatedPlicIrqIdUsbdevLinkReset = 65, /**< usbdev_link_reset */
517 kTopScafiDeprecatedPlicIrqIdUsbdevLinkSuspend = 66, /**< usbdev_link_suspend */
518 kTopScafiDeprecatedPlicIrqIdUsbdevLinkResume = 67, /**< usbdev_link_resume */
519 kTopScafiDeprecatedPlicIrqIdUsbdevAvOutEmpty = 68, /**< usbdev_av_out_empty */
520 kTopScafiDeprecatedPlicIrqIdUsbdevRxFull = 69, /**< usbdev_rx_full */
521 kTopScafiDeprecatedPlicIrqIdUsbdevAvOverflow = 70, /**< usbdev_av_overflow */
522 kTopScafiDeprecatedPlicIrqIdUsbdevLinkInErr = 71, /**< usbdev_link_in_err */
523 kTopScafiDeprecatedPlicIrqIdUsbdevRxCrcErr = 72, /**< usbdev_rx_crc_err */
524 kTopScafiDeprecatedPlicIrqIdUsbdevRxPidErr = 73, /**< usbdev_rx_pid_err */
525 kTopScafiDeprecatedPlicIrqIdUsbdevRxBitstuffErr = 74, /**< usbdev_rx_bitstuff_err */
527 kTopScafiDeprecatedPlicIrqIdUsbdevPowered = 76, /**< usbdev_powered */
528 kTopScafiDeprecatedPlicIrqIdUsbdevLinkOutErr = 77, /**< usbdev_link_out_err */
529 kTopScafiDeprecatedPlicIrqIdUsbdevAvSetupEmpty = 78, /**< usbdev_av_setup_empty */
530 kTopScafiDeprecatedPlicIrqIdPwrmgrAonWakeup = 79, /**< pwrmgr_aon_wakeup */
531 kTopScafiDeprecatedPlicIrqIdAonTimerAonWkupTimerExpired = 80, /**< aon_timer_aon_wkup_timer_expired */
532 kTopScafiDeprecatedPlicIrqIdAonTimerAonWdogTimerBark = 81, /**< aon_timer_aon_wdog_timer_bark */
533 kTopScafiDeprecatedPlicIrqIdFlashCtrlProgEmpty = 82, /**< flash_ctrl_prog_empty */
534 kTopScafiDeprecatedPlicIrqIdFlashCtrlProgLvl = 83, /**< flash_ctrl_prog_lvl */
535 kTopScafiDeprecatedPlicIrqIdFlashCtrlRdFull = 84, /**< flash_ctrl_rd_full */
536 kTopScafiDeprecatedPlicIrqIdFlashCtrlRdLvl = 85, /**< flash_ctrl_rd_lvl */
537 kTopScafiDeprecatedPlicIrqIdFlashCtrlOpDone = 86, /**< flash_ctrl_op_done */
538 kTopScafiDeprecatedPlicIrqIdFlashCtrlCorrErr = 87, /**< flash_ctrl_corr_err */
539 kTopScafiDeprecatedPlicIrqIdLast = 87, /**< \internal The Last Valid Interrupt ID. */
541
542/**
543 * PLIC Interrupt Source to Peripheral Map
544 *
545 * This array is a mapping from `top_scafi_deprecated_plic_irq_id_t` to
546 * `top_scafi_deprecated_plic_peripheral_t`.
547 */
549 top_scafi_deprecated_plic_interrupt_for_peripheral[88];
550
551/**
552 * PLIC Interrupt Target.
553 *
554 * Enumeration used to determine which set of IE, CC, threshold registers to
555 * access for a given interrupt target.
556 */
558 kTopScafiDeprecatedPlicTargetIbex0 = 0, /**< Ibex Core 0 */
559 kTopScafiDeprecatedPlicTargetLast = 0, /**< \internal Final PLIC target */
561
562
563#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
564
565// PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1}
566// 0 and 1 are tied to value 0 and 1
567#define NUM_MIO_PADS 47
568#define NUM_DIO_PADS 14
569
570#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3
571
572/**
573 * Pinmux Peripheral Input.
574 */
586 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio10 = 10, /**< Peripheral Input 10 */
587 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio11 = 11, /**< Peripheral Input 11 */
588 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio12 = 12, /**< Peripheral Input 12 */
589 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio13 = 13, /**< Peripheral Input 13 */
590 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio14 = 14, /**< Peripheral Input 14 */
591 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio15 = 15, /**< Peripheral Input 15 */
592 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio16 = 16, /**< Peripheral Input 16 */
593 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio17 = 17, /**< Peripheral Input 17 */
594 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio18 = 18, /**< Peripheral Input 18 */
595 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio19 = 19, /**< Peripheral Input 19 */
596 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio20 = 20, /**< Peripheral Input 20 */
597 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio21 = 21, /**< Peripheral Input 21 */
598 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio22 = 22, /**< Peripheral Input 22 */
599 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio23 = 23, /**< Peripheral Input 23 */
600 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio24 = 24, /**< Peripheral Input 24 */
601 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio25 = 25, /**< Peripheral Input 25 */
602 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio26 = 26, /**< Peripheral Input 26 */
603 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio27 = 27, /**< Peripheral Input 27 */
604 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio28 = 28, /**< Peripheral Input 28 */
605 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio29 = 29, /**< Peripheral Input 29 */
606 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio30 = 30, /**< Peripheral Input 30 */
607 kTopScafiDeprecatedPinmuxPeripheralInGpioGpio31 = 31, /**< Peripheral Input 31 */
608 kTopScafiDeprecatedPinmuxPeripheralInUart0Rx = 32, /**< Peripheral Input 32 */
609 kTopScafiDeprecatedPinmuxPeripheralInUart1Rx = 33, /**< Peripheral Input 33 */
610 kTopScafiDeprecatedPinmuxPeripheralInUsbdevSense = 34, /**< Peripheral Input 34 */
611 kTopScafiDeprecatedPinmuxPeripheralInLast = 34, /**< \internal Last valid peripheral input */
613
614/**
615 * Pinmux MIO Input Selector.
616 */
618 kTopScafiDeprecatedPinmuxInselConstantZero = 0, /**< Tie constantly to zero */
619 kTopScafiDeprecatedPinmuxInselConstantOne = 1, /**< Tie constantly to one */
630 kTopScafiDeprecatedPinmuxInselIob1 = 12, /**< MIO Pad 10 */
631 kTopScafiDeprecatedPinmuxInselIob2 = 13, /**< MIO Pad 11 */
632 kTopScafiDeprecatedPinmuxInselIob3 = 14, /**< MIO Pad 12 */
633 kTopScafiDeprecatedPinmuxInselIob4 = 15, /**< MIO Pad 13 */
634 kTopScafiDeprecatedPinmuxInselIob5 = 16, /**< MIO Pad 14 */
635 kTopScafiDeprecatedPinmuxInselIob6 = 17, /**< MIO Pad 15 */
636 kTopScafiDeprecatedPinmuxInselIob7 = 18, /**< MIO Pad 16 */
637 kTopScafiDeprecatedPinmuxInselIob8 = 19, /**< MIO Pad 17 */
638 kTopScafiDeprecatedPinmuxInselIob9 = 20, /**< MIO Pad 18 */
639 kTopScafiDeprecatedPinmuxInselIob10 = 21, /**< MIO Pad 19 */
640 kTopScafiDeprecatedPinmuxInselIob11 = 22, /**< MIO Pad 20 */
641 kTopScafiDeprecatedPinmuxInselIob12 = 23, /**< MIO Pad 21 */
642 kTopScafiDeprecatedPinmuxInselIoc0 = 24, /**< MIO Pad 22 */
643 kTopScafiDeprecatedPinmuxInselIoc1 = 25, /**< MIO Pad 23 */
644 kTopScafiDeprecatedPinmuxInselIoc2 = 26, /**< MIO Pad 24 */
645 kTopScafiDeprecatedPinmuxInselIoc3 = 27, /**< MIO Pad 25 */
646 kTopScafiDeprecatedPinmuxInselIoc4 = 28, /**< MIO Pad 26 */
647 kTopScafiDeprecatedPinmuxInselIoc5 = 29, /**< MIO Pad 27 */
648 kTopScafiDeprecatedPinmuxInselIoc6 = 30, /**< MIO Pad 28 */
649 kTopScafiDeprecatedPinmuxInselIoc7 = 31, /**< MIO Pad 29 */
650 kTopScafiDeprecatedPinmuxInselIoc8 = 32, /**< MIO Pad 30 */
651 kTopScafiDeprecatedPinmuxInselIoc9 = 33, /**< MIO Pad 31 */
652 kTopScafiDeprecatedPinmuxInselIoc10 = 34, /**< MIO Pad 32 */
653 kTopScafiDeprecatedPinmuxInselIoc11 = 35, /**< MIO Pad 33 */
654 kTopScafiDeprecatedPinmuxInselIoc12 = 36, /**< MIO Pad 34 */
655 kTopScafiDeprecatedPinmuxInselIor0 = 37, /**< MIO Pad 35 */
656 kTopScafiDeprecatedPinmuxInselIor1 = 38, /**< MIO Pad 36 */
657 kTopScafiDeprecatedPinmuxInselIor2 = 39, /**< MIO Pad 37 */
658 kTopScafiDeprecatedPinmuxInselIor3 = 40, /**< MIO Pad 38 */
659 kTopScafiDeprecatedPinmuxInselIor4 = 41, /**< MIO Pad 39 */
660 kTopScafiDeprecatedPinmuxInselIor5 = 42, /**< MIO Pad 40 */
661 kTopScafiDeprecatedPinmuxInselIor6 = 43, /**< MIO Pad 41 */
662 kTopScafiDeprecatedPinmuxInselIor7 = 44, /**< MIO Pad 42 */
663 kTopScafiDeprecatedPinmuxInselIor10 = 45, /**< MIO Pad 43 */
664 kTopScafiDeprecatedPinmuxInselIor11 = 46, /**< MIO Pad 44 */
665 kTopScafiDeprecatedPinmuxInselIor12 = 47, /**< MIO Pad 45 */
666 kTopScafiDeprecatedPinmuxInselIor13 = 48, /**< MIO Pad 46 */
667 kTopScafiDeprecatedPinmuxInselLast = 48, /**< \internal Last valid insel value */
669
670/**
671 * Pinmux MIO Output.
672 */
684 kTopScafiDeprecatedPinmuxMioOutIob1 = 10, /**< MIO Pad 10 */
685 kTopScafiDeprecatedPinmuxMioOutIob2 = 11, /**< MIO Pad 11 */
686 kTopScafiDeprecatedPinmuxMioOutIob3 = 12, /**< MIO Pad 12 */
687 kTopScafiDeprecatedPinmuxMioOutIob4 = 13, /**< MIO Pad 13 */
688 kTopScafiDeprecatedPinmuxMioOutIob5 = 14, /**< MIO Pad 14 */
689 kTopScafiDeprecatedPinmuxMioOutIob6 = 15, /**< MIO Pad 15 */
690 kTopScafiDeprecatedPinmuxMioOutIob7 = 16, /**< MIO Pad 16 */
691 kTopScafiDeprecatedPinmuxMioOutIob8 = 17, /**< MIO Pad 17 */
692 kTopScafiDeprecatedPinmuxMioOutIob9 = 18, /**< MIO Pad 18 */
696 kTopScafiDeprecatedPinmuxMioOutIoc0 = 22, /**< MIO Pad 22 */
697 kTopScafiDeprecatedPinmuxMioOutIoc1 = 23, /**< MIO Pad 23 */
698 kTopScafiDeprecatedPinmuxMioOutIoc2 = 24, /**< MIO Pad 24 */
699 kTopScafiDeprecatedPinmuxMioOutIoc3 = 25, /**< MIO Pad 25 */
700 kTopScafiDeprecatedPinmuxMioOutIoc4 = 26, /**< MIO Pad 26 */
701 kTopScafiDeprecatedPinmuxMioOutIoc5 = 27, /**< MIO Pad 27 */
702 kTopScafiDeprecatedPinmuxMioOutIoc6 = 28, /**< MIO Pad 28 */
703 kTopScafiDeprecatedPinmuxMioOutIoc7 = 29, /**< MIO Pad 29 */
704 kTopScafiDeprecatedPinmuxMioOutIoc8 = 30, /**< MIO Pad 30 */
705 kTopScafiDeprecatedPinmuxMioOutIoc9 = 31, /**< MIO Pad 31 */
709 kTopScafiDeprecatedPinmuxMioOutIor0 = 35, /**< MIO Pad 35 */
710 kTopScafiDeprecatedPinmuxMioOutIor1 = 36, /**< MIO Pad 36 */
711 kTopScafiDeprecatedPinmuxMioOutIor2 = 37, /**< MIO Pad 37 */
712 kTopScafiDeprecatedPinmuxMioOutIor3 = 38, /**< MIO Pad 38 */
713 kTopScafiDeprecatedPinmuxMioOutIor4 = 39, /**< MIO Pad 39 */
714 kTopScafiDeprecatedPinmuxMioOutIor5 = 40, /**< MIO Pad 40 */
715 kTopScafiDeprecatedPinmuxMioOutIor6 = 41, /**< MIO Pad 41 */
716 kTopScafiDeprecatedPinmuxMioOutIor7 = 42, /**< MIO Pad 42 */
721 kTopScafiDeprecatedPinmuxMioOutLast = 46, /**< \internal Last valid mio output */
723
724/**
725 * Pinmux Peripheral Output Selector.
726 */
728 kTopScafiDeprecatedPinmuxOutselConstantZero = 0, /**< Tie constantly to zero */
729 kTopScafiDeprecatedPinmuxOutselConstantOne = 1, /**< Tie constantly to one */
730 kTopScafiDeprecatedPinmuxOutselConstantHighZ = 2, /**< Tie constantly to high-Z */
731 kTopScafiDeprecatedPinmuxOutselGpioGpio0 = 3, /**< Peripheral Output 0 */
732 kTopScafiDeprecatedPinmuxOutselGpioGpio1 = 4, /**< Peripheral Output 1 */
733 kTopScafiDeprecatedPinmuxOutselGpioGpio2 = 5, /**< Peripheral Output 2 */
734 kTopScafiDeprecatedPinmuxOutselGpioGpio3 = 6, /**< Peripheral Output 3 */
735 kTopScafiDeprecatedPinmuxOutselGpioGpio4 = 7, /**< Peripheral Output 4 */
736 kTopScafiDeprecatedPinmuxOutselGpioGpio5 = 8, /**< Peripheral Output 5 */
737 kTopScafiDeprecatedPinmuxOutselGpioGpio6 = 9, /**< Peripheral Output 6 */
738 kTopScafiDeprecatedPinmuxOutselGpioGpio7 = 10, /**< Peripheral Output 7 */
739 kTopScafiDeprecatedPinmuxOutselGpioGpio8 = 11, /**< Peripheral Output 8 */
740 kTopScafiDeprecatedPinmuxOutselGpioGpio9 = 12, /**< Peripheral Output 9 */
741 kTopScafiDeprecatedPinmuxOutselGpioGpio10 = 13, /**< Peripheral Output 10 */
742 kTopScafiDeprecatedPinmuxOutselGpioGpio11 = 14, /**< Peripheral Output 11 */
743 kTopScafiDeprecatedPinmuxOutselGpioGpio12 = 15, /**< Peripheral Output 12 */
744 kTopScafiDeprecatedPinmuxOutselGpioGpio13 = 16, /**< Peripheral Output 13 */
745 kTopScafiDeprecatedPinmuxOutselGpioGpio14 = 17, /**< Peripheral Output 14 */
746 kTopScafiDeprecatedPinmuxOutselGpioGpio15 = 18, /**< Peripheral Output 15 */
747 kTopScafiDeprecatedPinmuxOutselGpioGpio16 = 19, /**< Peripheral Output 16 */
748 kTopScafiDeprecatedPinmuxOutselGpioGpio17 = 20, /**< Peripheral Output 17 */
749 kTopScafiDeprecatedPinmuxOutselGpioGpio18 = 21, /**< Peripheral Output 18 */
750 kTopScafiDeprecatedPinmuxOutselGpioGpio19 = 22, /**< Peripheral Output 19 */
751 kTopScafiDeprecatedPinmuxOutselGpioGpio20 = 23, /**< Peripheral Output 20 */
752 kTopScafiDeprecatedPinmuxOutselGpioGpio21 = 24, /**< Peripheral Output 21 */
753 kTopScafiDeprecatedPinmuxOutselGpioGpio22 = 25, /**< Peripheral Output 22 */
754 kTopScafiDeprecatedPinmuxOutselGpioGpio23 = 26, /**< Peripheral Output 23 */
755 kTopScafiDeprecatedPinmuxOutselGpioGpio24 = 27, /**< Peripheral Output 24 */
756 kTopScafiDeprecatedPinmuxOutselGpioGpio25 = 28, /**< Peripheral Output 25 */
757 kTopScafiDeprecatedPinmuxOutselGpioGpio26 = 29, /**< Peripheral Output 26 */
758 kTopScafiDeprecatedPinmuxOutselGpioGpio27 = 30, /**< Peripheral Output 27 */
759 kTopScafiDeprecatedPinmuxOutselGpioGpio28 = 31, /**< Peripheral Output 28 */
760 kTopScafiDeprecatedPinmuxOutselGpioGpio29 = 32, /**< Peripheral Output 29 */
761 kTopScafiDeprecatedPinmuxOutselGpioGpio30 = 33, /**< Peripheral Output 30 */
762 kTopScafiDeprecatedPinmuxOutselGpioGpio31 = 34, /**< Peripheral Output 31 */
763 kTopScafiDeprecatedPinmuxOutselUart0Tx = 35, /**< Peripheral Output 32 */
764 kTopScafiDeprecatedPinmuxOutselUart1Tx = 36, /**< Peripheral Output 33 */
765 kTopScafiDeprecatedPinmuxOutselLast = 36, /**< \internal Last valid outsel value */
767
768/**
769 * Dedicated Pad Selects
770 */
772 kTopScafiDeprecatedDirectPadsSpiHost0Sd0 = 0, /**< */
773 kTopScafiDeprecatedDirectPadsSpiHost0Sd1 = 1, /**< */
774 kTopScafiDeprecatedDirectPadsSpiHost0Sd2 = 2, /**< */
775 kTopScafiDeprecatedDirectPadsSpiHost0Sd3 = 3, /**< */
776 kTopScafiDeprecatedDirectPadsSpiDeviceSd0 = 4, /**< */
777 kTopScafiDeprecatedDirectPadsSpiDeviceSd1 = 5, /**< */
778 kTopScafiDeprecatedDirectPadsSpiDeviceSd2 = 6, /**< */
779 kTopScafiDeprecatedDirectPadsSpiDeviceSd3 = 7, /**< */
780 kTopScafiDeprecatedDirectPadsUsbdevUsbDp = 8, /**< */
781 kTopScafiDeprecatedDirectPadsUsbdevUsbDn = 9, /**< */
782 kTopScafiDeprecatedDirectPadsSpiDeviceSck = 10, /**< */
783 kTopScafiDeprecatedDirectPadsSpiDeviceCsb = 11, /**< */
784 kTopScafiDeprecatedDirectPadsSpiHost0Sck = 12, /**< */
785 kTopScafiDeprecatedDirectPadsSpiHost0Csb = 13, /**< */
786 kTopScafiDeprecatedDirectPadsLast = 13, /**< \internal Last valid direct pad */
788
789/**
790 * Muxed Pad Selects
791 */
793 kTopScafiDeprecatedMuxedPadsIoa0 = 0, /**< */
794 kTopScafiDeprecatedMuxedPadsIoa1 = 1, /**< */
795 kTopScafiDeprecatedMuxedPadsIoa2 = 2, /**< */
796 kTopScafiDeprecatedMuxedPadsIoa3 = 3, /**< */
797 kTopScafiDeprecatedMuxedPadsIoa4 = 4, /**< */
798 kTopScafiDeprecatedMuxedPadsIoa5 = 5, /**< */
799 kTopScafiDeprecatedMuxedPadsIoa6 = 6, /**< */
800 kTopScafiDeprecatedMuxedPadsIoa7 = 7, /**< */
801 kTopScafiDeprecatedMuxedPadsIoa8 = 8, /**< */
802 kTopScafiDeprecatedMuxedPadsIob0 = 9, /**< */
803 kTopScafiDeprecatedMuxedPadsIob1 = 10, /**< */
804 kTopScafiDeprecatedMuxedPadsIob2 = 11, /**< */
805 kTopScafiDeprecatedMuxedPadsIob3 = 12, /**< */
806 kTopScafiDeprecatedMuxedPadsIob4 = 13, /**< */
807 kTopScafiDeprecatedMuxedPadsIob5 = 14, /**< */
808 kTopScafiDeprecatedMuxedPadsIob6 = 15, /**< */
809 kTopScafiDeprecatedMuxedPadsIob7 = 16, /**< */
810 kTopScafiDeprecatedMuxedPadsIob8 = 17, /**< */
811 kTopScafiDeprecatedMuxedPadsIob9 = 18, /**< */
812 kTopScafiDeprecatedMuxedPadsIob10 = 19, /**< */
813 kTopScafiDeprecatedMuxedPadsIob11 = 20, /**< */
814 kTopScafiDeprecatedMuxedPadsIob12 = 21, /**< */
815 kTopScafiDeprecatedMuxedPadsIoc0 = 22, /**< */
816 kTopScafiDeprecatedMuxedPadsIoc1 = 23, /**< */
817 kTopScafiDeprecatedMuxedPadsIoc2 = 24, /**< */
818 kTopScafiDeprecatedMuxedPadsIoc3 = 25, /**< */
819 kTopScafiDeprecatedMuxedPadsIoc4 = 26, /**< */
820 kTopScafiDeprecatedMuxedPadsIoc5 = 27, /**< */
821 kTopScafiDeprecatedMuxedPadsIoc6 = 28, /**< */
822 kTopScafiDeprecatedMuxedPadsIoc7 = 29, /**< */
823 kTopScafiDeprecatedMuxedPadsIoc8 = 30, /**< */
824 kTopScafiDeprecatedMuxedPadsIoc9 = 31, /**< */
825 kTopScafiDeprecatedMuxedPadsIoc10 = 32, /**< */
826 kTopScafiDeprecatedMuxedPadsIoc11 = 33, /**< */
827 kTopScafiDeprecatedMuxedPadsIoc12 = 34, /**< */
828 kTopScafiDeprecatedMuxedPadsIor0 = 35, /**< */
829 kTopScafiDeprecatedMuxedPadsIor1 = 36, /**< */
830 kTopScafiDeprecatedMuxedPadsIor2 = 37, /**< */
831 kTopScafiDeprecatedMuxedPadsIor3 = 38, /**< */
832 kTopScafiDeprecatedMuxedPadsIor4 = 39, /**< */
833 kTopScafiDeprecatedMuxedPadsIor5 = 40, /**< */
834 kTopScafiDeprecatedMuxedPadsIor6 = 41, /**< */
835 kTopScafiDeprecatedMuxedPadsIor7 = 42, /**< */
836 kTopScafiDeprecatedMuxedPadsIor10 = 43, /**< */
837 kTopScafiDeprecatedMuxedPadsIor11 = 44, /**< */
838 kTopScafiDeprecatedMuxedPadsIor12 = 45, /**< */
839 kTopScafiDeprecatedMuxedPadsIor13 = 46, /**< */
840 kTopScafiDeprecatedMuxedPadsLast = 46, /**< \internal Last valid muxed pad */
842
843/**
844 * Power Manager Wakeup Signals
845 */
847 kTopScafiDeprecatedPowerManagerWakeUpsPinmuxAonPinWkupReq = 0, /**< */
848 kTopScafiDeprecatedPowerManagerWakeUpsPinmuxAonUsbWkupReq = 1, /**< */
849 kTopScafiDeprecatedPowerManagerWakeUpsAonTimerAonWkupReq = 2, /**< */
850 kTopScafiDeprecatedPowerManagerWakeUpsLast = 2, /**< \internal Last valid pwrmgr wakeup signal */
852
853/**
854 * Reset Manager Software Controlled Resets
855 */
857 kTopScafiDeprecatedResetManagerSwResetsSpiDevice = 0, /**< */
858 kTopScafiDeprecatedResetManagerSwResetsSpiHost0 = 1, /**< */
859 kTopScafiDeprecatedResetManagerSwResetsUsb = 2, /**< */
860 kTopScafiDeprecatedResetManagerSwResetsLast = 2, /**< \internal Last valid rstmgr software reset request */
862
863/**
864 * Power Manager Reset Request Signals
865 */
867 kTopScafiDeprecatedPowerManagerResetRequestsAonTimerAonAonTimerRstReq = 0, /**< */
868 kTopScafiDeprecatedPowerManagerResetRequestsLast = 0, /**< \internal Last valid pwrmgr reset_request signal */
870
871/**
872 * Clock Manager Software-Controlled ("Gated") Clocks.
873 *
874 * The Software has full control over these clocks.
875 */
877 kTopScafiDeprecatedGateableClocksIoDiv4Peri = 0, /**< Clock clk_io_div4_peri in group peri */
878 kTopScafiDeprecatedGateableClocksIoDiv2Peri = 1, /**< Clock clk_io_div2_peri in group peri */
879 kTopScafiDeprecatedGateableClocksIoPeri = 2, /**< Clock clk_io_peri in group peri */
880 kTopScafiDeprecatedGateableClocksUsbPeri = 3, /**< Clock clk_usb_peri in group peri */
881 kTopScafiDeprecatedGateableClocksLast = 3, /**< \internal Last Valid Gateable Clock */
883
884/**
885 * Clock Manager Software-Hinted Clocks.
886 *
887 * The Software has partial control over these clocks. It can ask them to stop,
888 * but the clock manager is in control of whether the clock actually is stopped.
889 */
891 kTopScafiDeprecatedHintableClocksMainAes = 0, /**< Clock clk_main_aes in group trans */
892 kTopScafiDeprecatedHintableClocksLast = 0, /**< \internal Last Valid Hintable Clock */
894
895/**
896 * MMIO Region
897 *
898 * MMIO region excludes any memory that is separate from the module
899 * configuration space, i.e. ROM, main SRAM, and flash are excluded but
900 * retention SRAM, spi_device memory, or usbdev memory are included.
901 */
902#define TOP_SCAFI_DEPRECATED_MMIO_BASE_ADDR 0x40000000u
903#define TOP_SCAFI_DEPRECATED_MMIO_SIZE_BYTES 0x10000000u
904
905// Header Extern Guard
906#ifdef __cplusplus
907} // extern "C"
908#endif
909
910#endif // OPENTITAN_HW_TOP_SCAFI_DEPRECATED_SW_AUTOGEN_TOP_SCAFI_DEPRECATED_H_