Glossary

A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z

A

  • ACC: Asymmetric Cryptographic Coprocessor, a RISC-V-like programmable coprocessor for cyptographic algorithms.

  • ACE: Architectural Composition Engine, the tooling in Pavona that generates a system from its component specifications.

  • ADC: Analog-to-Digital Converter.

  • AES: Advanced Encryption Standard.

  • Airgapped: Isolated from the surrounding environment, particularly from networks or the operating system.

  • AON: Always On.

  • ASM: Assembly code.

  • Attestation: The process of a device taking some measurement and checking it matches what is expected.

B

  • Baud: Unit of measurement for “symbols per second” where symbols are some unit being communicated over a channel.

Often abbreviated to Bd, kBd (1000 Bd), MBd (1000 kBd), and GBd (1000 MBd).

  • BFV: Boot Fault Value.

C

  • CIP: Comportable (hardware) Intellectual Property.

  • Comportable: See the comportability specification.

  • CP: Circuit Probe.

  • CRC: Cyclic Redundancy Check.

  • CSR: Control/Status Register.

  • CSRNG: Cryptographically Secure Random Number Generator.

  • CTAP: Client to Authenticator Protocol.

A protocol for authentication devices to communicate with a host computer.

D

  • Dragonfly: A reference top-level system that can be integrated into a larger SOC.

  • DD: Digital Design.

  • DIF: Device Interface Function.

  • DV: Design Verification.

  • dvsim: Design verification simulator tool.

E

  • E2E: End-to-End.

Egret

A reference top-level system intended for implementation as a discrete chip. See Egret for a the full specification.

  • EDA: Electronic Design Automation.

  • EDN: Entropy Distribution Network.

  • ePIC: Embedded Position Independent Code.

  • ePMP: Enhanced Physical Memory Protection. A RISC-V extension to the physical memory protection part of the RISC-V privileged architecture specification. Also known as “Smepmp”.

F

  • FI: Fault Injection.

  • FIDO2: Fast Identity Online version 2. A collection of protocol specifications for authenticating a user with a device or server.

  • FIPS: Federal Information Process Standards.

  • Flash: A type of non-volatile reprogrammable memory.

  • FPGA: Field Programmable Gate Array.

  • FPV: Formal Property Verification.

  • FT: Final Test.

G

  • GCM: Galois/Counter Mode.

  • GF2: Galois Field of order 2.

  • GPIO: General-Purpose Input/Output.

H

  • HDL: Hardware Description Language.

  • HMAC: Hash-based Message Authentication Code.

  • HSM: Hardware Security Module.

  • HyperDebug: A custom development harness for testing and debugging deployments on CW310 and CW340 FPGA boards.

I

  • I2C: Inter-Integrated Circuit.

  • Ibex: A 32-bit RISC-V core.

  • IP: Intellectual Property.

  • IRQ: Interrupt (request).

  • IV: Initialization vector.

K

  • KMAC: Keccak Message Authentication Code.

L

  • LC: Life-Cycle (controller).

  • LCV: Life Cycle Value.

M

  • Mask ROM: Read-Only Memory encoded into the “mask” used to fabricate silicon.

  • MCU: Microcontroller Unit.

  • Mux: Multiplexer.

N

  • Netlist: A list of connections between nodes of a circuit.

  • NMI: Non-Maskable Interrupt.

O

  • OTP: One-Time Programmable (memory).

P

  • PIC: Position-Independent Code.

  • Pinmux: Pin Multiplexer.

  • PKI: Public Key Infrastructure.

  • PLIC: Platform Level Interrupt Controller.

  • PMP: Physical Memory Protection.

  • POR: Power-On Reset.

  • PQC: Post-Quantum Cryptography.

  • PRNG: Pseudorandom Number Generator.

  • PWM: Pulse-Width Modulation.

R

  • RAM: Random-Access Memory.

  • RFC: Request For Comments.

  • RISC-V: An open source instruction set architecture.

  • RNG: Random Number Generator.

  • ROM: Read-Only Memory.

  • RoT: Root of Trust.

  • RTL: Register-Transfer Level.

  • RV DM: RISC-V Debug Module.

S

  • SCA: Side-Channel Analysis.

  • SHA: Secure Hash Algorithms.

  • Silicon: The semiconductor material that most microchips are made from.

  • Smoketest: A simple test used to check that some feature works to some degree, even if not in depth.

  • SoC: System on a Chip.

  • SPI: Serial Peripheral Interface.

  • SRAM: Static Random-Access Memory.

  • Configuration Straps / Pin Straps: Externally-exposed pins used to provide early-boot configuration.

T

  • TAP: Test Access Port.

  • Tapeout: The process of fabricating a chip.

  • TCB: Trusted Computing Base.

  • TL-UL: TileLink Uncached Lightweight (bus/crossbar).

  • Tock: An embedded operating system implemented in Rust.

  • Top(-level): A full chip design, including all its components and external connections.

  • TPM: Trusted Platform Module.

U

  • UART: Universal Asynchronous Receiver-Transmitter.

V

  • VER: Version.