Hardware

This is the landing page for all hardware development.

This page describes the directory structure, presents the comportable hardware IP block dashboard, lists supported CPU cores, and lists supported top-level designs.

Directory organization

Hardware development happens at both the top-level and the block-level.

Top-level designs serve as reference designs instantiating a specific combination and connection of hardware IP blocks. The present top-level designs – Egret, Dragonfly, and Scafi_Deprecated – are found in top_egret/, top_dragonfly/, and top_scafi_deprecated/ respectively. These top-level designs are by no means fixed; they serve as suggested starting points for further development and experimentation.

Hardware IP blocks can be top-agnostic or top-specific, and the organization of this directory reflects this distinction. The ip/ directory contains blocks that are generically useful to any top. Primitive libraries (e.g. prim_fifo) are found in ip/prim/. Technology-specific primitive libraries (e.g. FPGA-specific specialized primitives) also belong to ip/prim_*/. Hardware IP blocks that are specific to a given top belong in that top’s top_*/ip/ directory.

Some hardware IP blocks require parameterization beyond the capabilities of ordinary SystemVerilog parameters. To carry out parameterization, these IP blocks’ files are written in Mako templates and are indicated with filenames ending in *.tpl. These hardware IP blocks are said to be “templatized”. Templatized hardware IP blocks are found in the ip_templates/ directory. Prior to compilation, the templates for these hardware IP blocks are filled for a given top and copied in that top’s top_*/ip_autogen/ directory.

For a more complete description of the remaining directories, see Directory Structure

Comportable hardware IP block dashboard

The following autogenerated table contains links to design/verification specifications for each hardware IP block. See the Hardware Development Stages for a description of the hardware stages and how they are determined.

Design Spec DV Document Spec Version Development Stage Notes
acc DV 0.1.0 L1 D1 V1 S1

 
1.1.0 L1 D2S V2S S2

 
adc_ctrl DV 2.0.0 L1 D2S V2S S2
aes DV 1.0.1 L1 D2S V2S S2

 
aon_timer DV 2.0.0 L1 D3 V2S S2

 
csrng DV 3.0.0 L1 D1 V1 S2

 
edn DV 2.0.0 L1 D2S V2S S2

 
entropy_src DV 3.0.0 L1 D2S V2S S2

 
hmac DV 0.5.0 L2 D3 V3 -

 
1.0.0 L1 D3 V2S S2

 
2.0.1 L1 D3 V2S S1

 
i2c DV 2.1.0 L1 D2S V2S S2

Verification Stage is V2S qualified by the given exceptions in PR#22108. This broadly excludes verif. of multi-controller features.
keymgr DV 2.0.0 L1 D2S V2S S2

 
kmac DV 2.1.0 L1 D2S V2S S2

 
lc_ctrl DV 2.1.1 L1 D3 V1 S2

 
pattgen DV 1.1.0 L1 D2S V2S S2

 
rom_ctrl DV 1.0.1 L1 D3 V2S S2

 
rv_dm DV 1.2.1 L1 D2S V1 -

 
rv_timer DV 0.5.0 L2 D3 V3 -

 
1.0.0 L1 D3 V3 S2

D3 Reviewed @ 2025-05-09, V3 Reviewed @ 2025-05-09
spi_device DV 0.5.0 L1 D1 V1 S0

 
1.0.0 L1 D2S V2S S2

 
2.0.0 L1 D2S V2S S1

 
spi_host DV 3.0.0 L1 D0 V0 S1

 
sram_ctrl DV 1.1.0 L1 D3 V2S S2

 
sysrst_ctrl DV 2.0.0 L1 D3 V2S S2

 
uart DV 1.0.0 L2 D3 V3 -

 
1.1.0 L1 D3 V2S S2

 
2.1.0 L1 D2S V2S S2

 
usbdev DV 2.0.0 L1 D2S V2S S2

 

Processor cores

Ibex

The Ibex core (at ip_templates/rv_core_ibex/) is a 32-bit RISC-V CPU core. Ibex is an in-order, 2- or 3-stage (configurable) pipelined processor that can support the compressed and bit manipulation instruction set extensions (RV32IMCB).

Top-level designs

Egret top-level

Egret-specific comportable IPs

Design Spec DV Document Spec Version Development Stage Notes
sensor_ctrl DV 2.0.0 L1 D3 N/A -

Verified at the top-level.
alert_handler DV 1.0.1 L1 D3 V2S S2

Use both FPV and DV to perform block level verification.
clkmgr DV 1.0.1 L1 D3 V2S S2

 
flash_ctrl DV 0.1.0 L1 D1 V1 -

 
2.0.0 L1 D2S V2S S2

 
gpio DV 1.0.0 L2 D3 V3 -

 
1.2.0 L1 D3 V2S S2

 
otp_ctrl DV 0.1.0 L1 D2 V2 S1

 
1.0.0 L1 D3 V2S S2

 
3.0.0 L1 D1 V1 S2

 
pinmux DV 1.1.1 L1 D3 V2S S2

Use FPV to perform block level verification.
pwm DV 1.0.0 L1 D2S V2S S2

 
pwrmgr DV 0.1.0 L1 D1 V0 S0

 
1.0.1 L1 D3 V2S S2

 
rstmgr DV 1.0.0 L1 D3 V2S S2

 
rv_core_ibex DV 2.1.0 L1 D2S V2S S2

Ibex Verification is tracked in the Ibex documentation.
rv_plic DV 2.0.0 L1 D3 V2 S2

Use FPV to perform block level verification.

Dragonfly top-level